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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
24 */␊
25static uint64_t measure_tsc_frequency(void)␊
26{␊
27␉uint64_t tscStart;␊
28␉uint64_t tscEnd;␊
29␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
30␉unsigned long pollCount;␊
31␉uint64_t retval = 0;␊
32␉int i;␊
33␊
34␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
35␉ * counter 2. We run this loop 3 times to make sure the cache␊
36␉ * is hot and we take the minimum delta from all of the runs.␊
37␉ * That is to say that we're biased towards measuring the minimum␊
38␉ * number of TSC ticks that occur while waiting for the timer to␊
39␉ * expire. That theoretically helps avoid inconsistencies when␊
40␉ * running under a VM if the TSC is not virtualized and the host␊
41␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
42␉ */␊
43␉for(i = 0; i < 10; ++i)␊
44␉{␊
45␉␉enable_PIT2();␊
46␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
47␉␉tscStart = rdtsc64();␊
48␉␉pollCount = poll_PIT2_gate();␊
49␉␉tscEnd = rdtsc64();␊
50␉␉/* The poll loop must have run at least a few times for accuracy */␊
51␉␉if (pollCount <= 1)␊
52␉␉{␊
53␉␉␉continue;␊
54␉␉}␊
55␉␉/* The TSC must increment at LEAST once every millisecond.␊
56␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
57␉␉ * be >= 30. Anything less and the processor is way too slow.␊
58␉␉ */␊
59␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
60␉␉{␊
61␉␉␉continue;␊
62␉␉}␊
63␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
64␉␉if ( (tscEnd - tscStart) < tscDelta )␊
65␉␉{␊
66␉␉␉tscDelta = tscEnd - tscStart;␊
67␉␉}␊
68␉}␊
69␉/* tscDelta is now the least number of TSC ticks the processor made in␊
70␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
71␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
72␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
73␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
74␉ * dividing by the milliseconds, we simply multiply by 1000.␊
75␉ */␊
76␊
77␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
78␉ * that we're going to multiply by 1000 first so we do need at least some␊
79␉ * arithmetic headroom. For now, 32-bit should be enough.␊
80␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
81␉ */␊
82␉if (tscDelta > (1ULL<<32))␊
83␉{␊
84␉␉retval = 0;␊
85␉}␊
86␉else␊
87␉{␊
88␉␉retval = tscDelta * 1000 / 30;␊
89␉}␊
90␉disable_PIT2();␊
91␉return retval;␊
92}␊
93␊
94/*␊
95 * timeRDTSC()␊
96 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
97 * It pauses until the value is latched in the counter␊
98 * and then reads the time stamp counter to return to the caller.␊
99 */␊
100static uint64_t timeRDTSC(void)␊
101{␊
102␉int␉␉attempts = 0;␊
103␉uint64_t latchTime;␊
104␉uint64_t␉saveTime,intermediate;␊
105␉unsigned int timerValue, lastValue;␊
106␉//boolean_t␉int_enabled;␊
107␉/*␊
108␉ * Table of correction factors to account for␊
109␉ *␉ - timer counter quantization errors, and␊
110␉ *␉ - undercounts 0..5␊
111␉ */␊
112#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
113#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
114#define SAMPLE_NSECS␉␉(2000000000LL)␊
115#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
116#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
117␉uint64_t␉scale[6] = {␊
118␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
119␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
120␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
121␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
122␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
123␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
124␉};␊
125␊
126␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊
127␊
128restart:␊
129␉if (attempts >= 9) // increase to up to 9 attempts.␊
130␉{␊
131␉ // This will flash-reboot. TODO: Use tscPanic instead.␊
132␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
133␉}␊
134␉attempts++;␊
135␉enable_PIT2();␉␉// turn on PIT2␊
136␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
137␉latchTime = rdtsc64();␉// get the time stamp to time ␊
138␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
139␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
140␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
141␉get_PIT2(&lastValue);␊
142␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
143␉do {␊
144␉␉intermediate = get_PIT2(&timerValue);␊
145␉␉if (timerValue > lastValue)␊
146␉␉{␊
147␉␉␉// Timer wrapped␊
148␉␉␉set_PIT2(0);␊
149␉␉␉disable_PIT2();␊
150␉␉␉goto restart;␊
151␉␉}␊
152␉␉lastValue = timerValue;␊
153␉} while (timerValue > 5);␊
154␉printf("timerValue␉ %d\n",timerValue);␊
155␉printf("intermediate 0x%016llX\n",intermediate);␊
156␉printf("saveTime␉ 0x%016llX\n",saveTime);␊
157 ␊
158␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
159␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
160␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
161␉intermediate += latchTime;␉␉// add on our save fudge␊
162␊
163␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
164␉disable_PIT2();␉␉␉// turn off PIT 2␊
165␊
166␉//ml_set_interrupts_enabled(int_enabled);␊
167␉return intermediate;␊
168}␊
169␊
170/*␊
171 * Original comment/code:␊
172 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
173 *␊
174 * Measures the Actual Performance Frequency in Hz (64-bit)␊
175 * (just a naming change, mperf --> aperf )␊
176 */␊
177static uint64_t measure_aperf_frequency(void)␊
178{␊
179␉uint64_t aperfStart;␊
180␉uint64_t aperfEnd;␊
181␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
182␉unsigned long pollCount;␊
183␉uint64_t retval = 0;␊
184␉int i;␊
185␊
186␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
187␉ * counter 2. We run this loop 3 times to make sure the cache␊
188␉ * is hot and we take the minimum delta from all of the runs.␊
189␉ * That is to say that we're biased towards measuring the minimum␊
190␉ * number of APERF ticks that occur while waiting for the timer to␊
191␉ * expire.␊
192␉ */␊
193␉for(i = 0; i < 10; ++i)␊
194␉{␊
195␉␉enable_PIT2();␊
196␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
197␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
198␉␉pollCount = poll_PIT2_gate();␊
199␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
200␉␉/* The poll loop must have run at least a few times for accuracy */␊
201␉␉if (pollCount <= 1)␊
202␉␉{␊
203␉␉␉continue;␊
204␉␉}␊
205␉␉/* The TSC must increment at LEAST once every millisecond.␊
206␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
207␉␉ * be >= 30. Anything less and the processor is way too slow.␊
208␉␉ */␊
209␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
210␉␉{␊
211␉␉␉continue;␊
212␉␉}␊
213␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
214␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
215␉␉{␊
216␉␉␉aperfDelta = aperfEnd - aperfStart;␊
217␉␉}␊
218␉}␊
219␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
220␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
221␉ */␊
222␊
223␉if (aperfDelta > (1ULL<<32))␊
224␉{␊
225␉␉retval = 0;␊
226␉}␊
227␉else␊
228␉{␊
229␉␉retval = aperfDelta * 1000 / 30;␊
230␉}␊
231␉disable_PIT2();␊
232␉return retval;␊
233}␊
234␊
235/*␊
236 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
237 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
238 *␉ a max multi. (used to calculate the FSB freq.),␊
239 *␉ and a current multi. (used to calculate the CPU freq.)␊
240 * - fsbFrequency = tscFrequency / multi␊
241 * - cpuFrequency = fsbFrequency * multi␊
242 */␊
243void scan_cpu(PlatformInfo_t *p)␊
244{␊
245␉uint64_t␉tscFrequency␉= 0;␊
246␉uint64_t␉fsbFrequency␉= 0;␊
247␉uint64_t␉cpuFrequency␉= 0;␊
248␉uint64_t␉msr␉␉= 0;␊
249␉uint64_t␉flex_ratio␉= 0;␊
250␊
251␉uint32_t␉max_ratio␉= 0;␊
252␉uint32_t␉min_ratio␉= 0;␊
253␉uint8_t␉␉bus_ratio_max␉= 0;␊
254␉uint8_t␉␉bus_ratio_min␉= 0;␊
255␉uint8_t␉␉currdiv␉␉= 0;␊
256␉uint8_t␉␉currcoef␉= 0;␊
257␉uint8_t␉␉maxdiv␉␉= 0;␊
258␉uint8_t␉␉maxcoef␉␉= 0;␊
259␊
260␉const char␉*newratio;␊
261␉int␉␉len = 0;␊
262␉int␉␉myfsb = 0;␊
263␊
264␉/* get cpuid values */␊
265␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
266␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
267␊
268␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
269␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
270␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
271␊
272␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
273␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊
274␉{␊
275␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
276␉}␊
277␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊
278␉{␊
279␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
280␉}␊
281␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
282␉{␊
283␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
284␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
285␉}␊
286␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
287␉{␊
288␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
289␉}␊
290␊
291// #if DEBUG_CPU␊
292␉{␊
293␉␉int␉␉i;␊
294␉␉DBG("CPUID Raw Values:\n");␊
295␉␉for (i = 0; i < CPUID_MAX; i++) {␊
296␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊
297␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
298␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
299␉␉}␊
300␉}␊
301// #endif␊
302␊
303/* http://www.flounder.com/cpuid_explorer2.htm␊
304 EAX (Intel):␊
305 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
306 +--------+----------------+--------+----+----+--------+--------+--------+␊
307 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
308 +--------+----------------+--------+----+----+--------+--------+--------+␊
309␊
310 EAX (AMD):␊
311 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
312 +--------+----------------+--------+----+----+--------+--------+--------+␊
313 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
314 +--------+----------------+--------+----+----+--------+--------+--------+␊
315*/␊
316␉p->CPU.MCodeVersion␉= (uint32_t)(rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);␊
317␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
318␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
319␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
320␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
321␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
322␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
323␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
324␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
325␊
326␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
327␊
328␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
329␉␉p->CPU.Family == 0x06 &&␊
330␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊
331␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
332␉␉)␊
333␉{␊
334␉␉/*␊
335␉␉ * Find the number of enabled cores and threads␊
336␉␉ * (which determines whether SMT/Hyperthreading is active).␊
337␉␉ */␊
338␉␉switch (p->CPU.Model)␊
339␉␉{␊
340␉␉␉case CPUID_MODEL_NEHALEM:␊
341␉␉␉case CPUID_MODEL_FIELDS:␊
342␉␉␉case CPUID_MODEL_DALES:␊
343␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
344␉␉␉case CPUID_MODEL_JAKETOWN:␊
345␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
346␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
347␉␉␉case CPUID_MODEL_HASWELL:␊
348␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
349␉␉␉//case CPUID_MODEL_HASWELL_H:␊
350␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
351␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
352␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
353␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊
354␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
355␉␉␉␉break;␊
356␊
357␉␉␉case CPUID_MODEL_DALES_32NM:␊
358␉␉␉case CPUID_MODEL_WESTMERE:␊
359␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
360␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
361␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊
362␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
363␉␉␉␉break;␊
364␊
365␉␉␉default:␊
366␉␉␉␉p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
367␉␉␉␉p->CPU.NoThreads = (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊
368␉␉␉␉//workaround for N270. I don't know why it detected wrong␊
369␉␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (p->CPU.Stepping == 2))␊
370␉␉␉␉{␊
371␉␉␉␉␉p->CPU.NoCores = 1;␊
372␉␉␉␉}␊
373␉␉␉␉break;␊
374␊
375␉␉} // end switch␊
376␊
377␉}␊
378␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
379␉{␊
380␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
381␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
382␉}␊
383␉else␊
384␉{␊
385␉␉// Use previous method for Cores and Threads␊
386␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
387␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
388␉}␊
389␊
390␉/* get BrandString (if supported) */␊
391␉/* Copyright: from Apple's XNU cpuid.c */␊
392␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
393␉{␊
394␉␉uint32_t␉reg[4];␊
395␉␉char␉␉str[128], *s;␊
396␉␉/*␊
397␉␉ * The BrandString 48 bytes (max), guaranteed to␊
398␉␉ * be NULL terminated.␊
399␉␉ */␊
400␉␉do_cpuid(0x80000002, reg);␊
401␉␉bcopy((char *)reg, &str[0], 16);␊
402␉␉do_cpuid(0x80000003, reg);␊
403␉␉bcopy((char *)reg, &str[16], 16);␊
404␉␉do_cpuid(0x80000004, reg);␊
405␉␉bcopy((char *)reg, &str[32], 16);␊
406␉␉for (s = str; *s != '\0'; s++)␊
407␉␉{␊
408␉␉␉if (*s != ' ')␊
409␉␉␉{␊
410␉␉␉␉break;␊
411␉␉␉}␊
412␉␉}␊
413␊
414␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
415␉␉{␊
416␉␉␉/*␊
417␉␉␉ * This string means we have a firmware-programmable brand string,␊
418␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
419␉␉␉ */␊
420␉␉␉p->CPU.BrandString[0] = '\0';␊
421␉␉}␊
422␉}␊
423␊
424␉/* setup features */␊
425␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
426␉{␊
427␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
428␉}␊
429␊
430␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
431␉{␊
432␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
433␉}␊
434␊
435␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
436␉{␊
437␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
438␉}␊
439␊
440␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
441␉{␊
442␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
443␉}␊
444␊
445␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
446␉{␊
447␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
448␉}␊
449␊
450␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
451␉{␊
452␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
453␉}␊
454␊
455␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
456␉{␊
457␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
458␉}␊
459␊
460␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
461␉{␊
462␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
463␉}␊
464␊
465␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
466␊
467␉if (p->CPU.NoThreads > p->CPU.NoCores)␊
468␉{␊
469␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
470␉}␊
471␊
472␉tscFrequency = measure_tsc_frequency();␊
473␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊
474␉/* if usual method failed */␊
475␉if ( tscFrequency < 1000 )␉//TEST␊
476␉{␊
477␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊
478␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
479␉}␊
480␉else␊
481␉{␊
482␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊
483␉}␊
484␊
485␉fsbFrequency = 0;␊
486␉cpuFrequency = 0;␊
487␊
488␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
489␉{␊
490␉␉int intelCPU = p->CPU.Model;␊
491␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
492␉␉{␊
493␉␉␉/* Nehalem CPU model */␊
494␉␉␉switch (p->CPU.Model)␊
495␉␉␉{␊
496␉␉␉␉case CPUID_MODEL_NEHALEM:␊
497␉␉␉␉case CPUID_MODEL_FIELDS:␊
498␉␉␉␉case CPUID_MODEL_DALES:␊
499␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
500␉␉␉␉case CPUID_MODEL_WESTMERE:␊
501␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
502␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
503/* --------------------------------------------------------- */␊
504␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
505␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
506␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
507␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
508␉␉␉␉case CPUID_MODEL_HASWELL:␊
509␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
510␊
511␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
512␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
513/* --------------------------------------------------------- */␊
514␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
515␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
516␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
517␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
518␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
519␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
520␉␉␉␉␉if (bitfield(msr, 16, 16))␊
521␉␉␉␉␉{␊
522␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
523␉␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
524␉␉␉␉␉␉ where the cpu multipler can't be changed to␊
525␉␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
526␉␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊
527␉␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
528␉␉␉␉␉␉ causing the system to crash since tscGranularity␊
529␉␉␉␉␉␉ is inadvertently set to 0.␊
530␉␉␉␉␉␉ */␊
531␉␉␉␉␉␉if (flex_ratio == 0)␊
532␉␉␉␉␉␉{␊
533␉␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
534␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
535␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
536␉␉␉␉␉␉␉DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
537␉␉␉␉␉␉}␊
538␉␉␉␉␉␉else␊
539␉␉␉␉␉␉{␊
540␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
541␉␉␉␉␉␉␉{␊
542␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
543␉␉␉␉␉␉␉}␊
544␉␉␉␉␉␉}␊
545␉␉␉␉␉}␊
546␊
547␉␉␉␉␉if (bus_ratio_max)␊
548␉␉␉␉␉{␊
549␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
550␉␉␉␉␉}␊
551␊
552␉␉␉␉␉//valv: Turbo Ratio Limit␊
553␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
554␉␉␉␉␉{␊
555␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
556␊
557␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
558␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
559␉␉␉␉␉}␊
560␉␉␉␉␉else␊
561␉␉␉␉␉{␊
562␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
563␉␉␉␉␉}␊
564␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
565␉␉␉␉␉{␊
566␉␉␉␉␉␉max_ratio = atoi(newratio);␊
567␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
568␉␉␉␉␉␉if (len >= 3)␊
569␉␉␉␉␉␉{␊
570␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
571␉␉␉␉␉␉}␊
572␊
573␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
574␊
575␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
576␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
577␉␉␉␉␉␉{␊
578␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
579␉␉␉␉␉␉␉if (len >= 3)␊
580␉␉␉␉␉␉␉{␊
581␉␉␉␉␉␉␉␉maxdiv = 1;␊
582␉␉␉␉␉␉␉}␊
583␉␉␉␉␉␉␉else␊
584␉␉␉␉␉␉␉{␊
585␉␉␉␉␉␉␉␉maxdiv = 0;␊
586␉␉␉␉␉␉␉}␊
587␉␉␉␉␉␉}␊
588␉␉␉␉␉␉else␊
589␉␉␉␉␉␉{␊
590␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
591␉␉␉␉␉␉}␊
592␉␉␉␉␉}␊
593␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
594␉␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
595␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
596␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
597␊
598␉␉␉␉myfsb = fsbFrequency / 1000000;␊
599␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
600␉␉␉␉currcoef = bus_ratio_max;␊
601␊
602␉␉␉␉break;␊
603␊
604␉␉␉default:␊
605␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
606␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
607␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
608␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
609␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
610␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
611␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
612␊
613␉␉␉␉// This will always be model >= 3␊
614␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
615␉␉␉␉{␊
616␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
617␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
618␉␉␉␉}␊
619␉␉␉␉else␊
620␉␉␉␉{␊
621␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
622␉␉␉␉␉/* XXX */␊
623␉␉␉␉␉maxcoef = currcoef;␊
624␉␉␉␉}␊
625␊
626␉␉␉␉if (!currcoef)␊
627␉␉␉␉{␊
628␉␉␉␉␉currcoef = maxcoef;␊
629␉␉␉␉}␊
630␊
631␉␉␉␉if (maxcoef)␊
632␉␉␉␉{␊
633␉␉␉␉␉if (maxdiv)␊
634␉␉␉␉␉{␊
635␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
636␉␉␉␉␉}␊
637␉␉␉␉␉else␊
638␉␉␉␉␉{␊
639␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
640␉␉␉␉␉}␊
641␊
642␉␉␉␉␉if (currdiv)␊
643␉␉␉␉␉{␊
644␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
645␉␉␉␉␉}␊
646␉␉␉␉␉else␊
647␉␉␉␉␉{␊
648␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
649␉␉␉␉␉}␊
650␊
651␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
652␉␉␉␉}␊
653␉␉␉␉break;␊
654␉␉␉}␊
655␉␉}␊
656␉␉// Mobile CPU␊
657␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
658␉␉{␊
659␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
660␉␉}␊
661␉}␊
662␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
663␉{␊
664␉␉switch(p->CPU.ExtFamily)␊
665␉␉{␊
666␉␉␉case 0x00: //* K8 *//␊
667␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
668␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
669␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
670␉␉␉␉break;␊
671␊
672␉␉␉case 0x01: //* K10 *//␊
673␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
674␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
675␉␉␉␉// EffFreq: effective frequency interface␊
676␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
677␉␉␉␉{␊
678␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
679␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
680␉␉␉␉␉cpuFrequency = aperf;␊
681␉␉␉␉}␊
682␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
683␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
684␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
685␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
686␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
687␊
688␉␉␉␉break;␊
689␊
690␉␉␉case 0x05: //* K14 *//␊
691␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
692␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
693␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
694␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
695␊
696␉␉␉␉break;␊
697␊
698␉␉␉case 0x02: //* K11 *//␊
699␉␉␉␉// not implimented␊
700␉␉␉␉break;␊
701␉␉}␊
702␊
703␉␉if (maxcoef)␊
704␉␉{␊
705␉␉␉if (currdiv)␊
706␉␉␉{␊
707␉␉␉␉if (!currcoef)␊
708␉␉␉␉{␊
709␉␉␉␉␉currcoef = maxcoef;␊
710␉␉␉␉}␊
711␊
712␉␉␉␉if (!cpuFrequency)␊
713␉␉␉␉{␊
714␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
715␉␉␉␉}␊
716␉␉␉␉else␊
717␉␉␉␉{␊
718␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
719␉␉␉␉}␊
720␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
721␉␉␉}␊
722␉␉␉else␊
723␉␉␉{␊
724␉␉␉␉if (!cpuFrequency)␊
725␉␉␉␉{␊
726␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
727␉␉␉␉}␊
728␉␉␉␉else␊
729␉␉␉␉{␊
730␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
731␉␉␉␉}␊
732␉␉␉␉DBG("%d\n", currcoef);␊
733␉␉␉}␊
734␉␉}␊
735␉␉else if (currcoef)␊
736␉␉{␊
737␉␉␉if (currdiv)␊
738␉␉␉{␊
739␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
740␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
741␉␉␉}␊
742␉␉␉else␊
743␉␉␉{␊
744␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
745␉␉␉␉DBG("%d\n", currcoef);␊
746␉␉␉}␊
747␉␉}␊
748␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
749␉}␊
750␉␊
751#if 0␊
752␉if (!fsbFrequency)␊
753␉{␊
754␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
755␉␉cpuFrequency = tscFrequency;␊
756␉␉DBG("0 ! using the default value for FSB !\n");␊
757␉}␊
758␊
759␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
760␊
761#endif␊
762␊
763␉p->CPU.MaxCoef = maxcoef;␊
764␉p->CPU.MaxDiv = maxdiv;␊
765␉p->CPU.CurrCoef = currcoef;␊
766␉p->CPU.CurrDiv = currdiv;␊
767␉p->CPU.TSCFrequency = tscFrequency;␊
768␉p->CPU.FSBFrequency = fsbFrequency;␊
769␉p->CPU.CPUFrequency = cpuFrequency;␊
770␊
771␉// keep formatted with spaces instead of tabs␊
772␉DBG("\n---------------------------------------------\n");␊
773 ␉DBG("------------------ CPU INFO -----------------\n");␊
774␉DBG("---------------------------------------------\n");␊
775␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
776␉DBG("Vendor: 0x%x\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
777␉DBG("Family: 0x%x\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
778␉DBG("ExtFamily: 0x%x\n",␉␉p->CPU.ExtFamily);␊
779␉DBG("Signature: %x\n",␉␉p->CPU.Signature);␉␉// CPUID signature␊
780␉/*switch (p->CPU.Type) {␊
781␉␉case PT_OEM:␊
782␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
783␉␉␉break;␊
784␉␉case PT_OD:␊
785␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
786␉␉␉break;␊
787␉␉case PT_DUAL:␊
788␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
789␉␉␉break;␊
790␉␉case PT_RES:␊
791␉␉␉DBG("Processor type: Intel Reserved\n");␊
792␉␉␉break;␊
793␉␉default:␊
794␉␉␉break;␊
795␉}*/␊
796␉DBG("Model: 0x%x\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
797␉DBG("ExtModel: 0x%x\n",␉␉p->CPU.ExtModel);␊
798␉DBG("Stepping: 0x%x\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
799␉DBG("MaxCoef: 0x%x\n",␉␉p->CPU.MaxCoef);␊
800␉DBG("CurrCoef: 0x%x\n",␉␉p->CPU.CurrCoef);␊
801␉DBG("MaxDiv: 0x%x\n",␉␉p->CPU.MaxDiv);␊
802␉DBG("CurrDiv: 0x%x\n",␉␉p->CPU.CurrDiv);␊
803␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
804␉DBG("FSBFreq: %dMHz\n",␉␉(p->CPU.FSBFrequency + 500000) / 1000000);␊
805␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
806␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
807␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
808␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
809␉DBG("Microcode version: %d\n",␉␉p->CPU.MCodeVersion);␉␉// CPU microcode version␊
810␉DBG("\n---------------------------------------------\n");␊
811#if DEBUG_CPU␊
812␉pause();␊
813#endif␊
814}␊
815

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