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Root/branches/ErmaC/Enoch/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉/* 09h Undefined */␊
40␉"",␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72int spd_indexes[] = {␊
73␉SPD_MEMORY_TYPE,␊
74␉SPD_DDR3_MEMORY_BANK,␊
75␉SPD_DDR3_MEMORY_CODE,␊
76␉SPD_NUM_ROWS,␊
77␉SPD_NUM_COLUMNS,␊
78␉SPD_NUM_DIMM_BANKS,␊
79␉SPD_NUM_BANKS_PER_SDRAM,␊
80␉4,7,8,9,12,64, /* TODO: give names to these values */␊
81␉95,96,97,98, 122,123,124,125 /* UIS */␊
82};␊
83#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
84␊
85/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
86␊
87unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
88{␊
89␉int l1, h1, l2, h2;␊
90␉unsigned long long t;␊
91␊
92␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
93␉outb(base + SMBHSTDAT, 0xff);␊
94␊
95␉rdtsc(l1, h1);␊
96␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
97␉{␊
98␉␉rdtsc(l2, h2);␊
99␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
100␉␉if (t > 5)␊
101␉␉{␊
102␉␉␉return 0xFF;␉// break␊
103␉␉}␊
104␉}␊
105␊
106␉outb(base + SMBHSTCMD, cmd);␊
107␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
108␉outb(base + SMBHSTCNT, 0x48 );␊
109␊
110␉rdtsc(l1, h1);␊
111␊
112␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
113␉{␊
114␉␉rdtsc(l2, h2);␊
115␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
116␉␉if (t > 5)␊
117␉␉{␊
118␉␉␉break;␉// break after 5ms␊
119␉␉}␊
120␉}␊
121␉return inb(base + SMBHSTDAT);␊
122}␊
123␊
124/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
125#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
126␊
127/** Read from spd *used* values only*/␊
128static void init_spd(char * spd, uint32_t base, int slot)␊
129{␊
130␉int i;␊
131␉for (i = 0; i < SPD_INDEXES_SIZE; i++)␊
132␉{␊
133␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
134␉}␊
135}␊
136␊
137// Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,␊
138// have different formats, always return a valid ptr.␊
139const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
140{␊
141␉uint8_t bank = 0;␊
142␉uint8_t code = 0;␊
143␉int i = 0;␊
144␉uint8_t * spd = (uint8_t *) slot->spd;␊
145␊
146␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
147␉{␊
148␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
149␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
150␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
151␉␉{␊
152␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
153␉␉␉{␊
154␉␉␉␉return vendorMap[i].name;␊
155␉␉␉}␊
156␉␉}␊
157␉}␊
158␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
159␉{␊
160␉␉if(spd[64]==0x7f)␊
161␉␉{␊
162␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
163␉␉␉{␊
164␉␉␉␉bank++;␊
165␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
166␉␉␉}␊
167␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
168␉␉␉code = spd[i];␊
169␉␉}␊
170␉␉else␊
171␉␉{␊
172␉␉␉code = spd[64];␊
173␉␉␉bank = 0;␊
174␉␉}␊
175␊
176␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
177␉␉{␊
178␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
179␉␉␉{␊
180␉␉␉␉return vendorMap[i].name;␊
181␉␉␉}␊
182␉␉}␊
183␉}␊
184␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
185␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊
186␉␉return "Unifosa";␊
187␉}␊
188␉return "NoName";␊
189}␊
190␊
191/* Get Default Memory Module Speed (no overclocking handled) */␊
192int getDDRspeedMhz(const char * spd)␊
193{␊
194␊
195␉if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))␊
196␉{␊
197␉␉switch(spd[9])␊
198␉␉{␊
199␉␉␉case 0x50:␊
200␉␉␉␉return 400;␊
201␉␉␉case 0x3d:␊
202␉␉␉␉return 533;␊
203␉␉␉case 0x30:␊
204␉␉␉␉return 667;␊
205␉␉␉case 0x25:␊
206␉␉␉default:␊
207␉␉␉␉return 800;␊
208␉␉␉case 0x1E:␊
209␉␉␉␉return 1066;␊
210␉␉}␊
211␉}␊
212␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
213␉{␊
214␉␉switch(spd[12])␊
215␉␉{␊
216␉␉␉case 0x0f:␊
217␉␉␉␉return 1066;␊
218␉␉␉case 0x0c:␊
219␉␉␉␉return 1333;␊
220␉␉␉case 0x0a:␊
221␉␉␉␉return 1600;␊
222␉␉␉case 0x14:␊
223␉␉␉default:␊
224␉␉␉␉return 800;␊
225␉␉}␊
226␉}␊
227␉return 800; // default freq for unknown types␊
228}␊
229␊
230#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
231#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
232␊
233/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
234const char *getDDRSerial(const char* spd)␊
235{␊
236␉static char asciiSerial[17];␊
237␊
238␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
239␉{␊
240␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
241␉}␊
242␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
243␉{␊
244␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
245␉}␊
246␉else␊
247␉{␊
248␉␉sprintf(asciiSerial, "0000000000000000");␊
249␉}␊
250␊
251␉return strdup(asciiSerial);␊
252}␊
253␊
254/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
255const char *getDDRPartNum(char *spd, uint32_t base, int slot)␊
256{␊
257␉int i, start = 0, index = 0;␊
258␉char c;␊
259␉static char asciiPartNo[32];␊
260␊
261␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
262␉{␊
263␉␉start = 128;␊
264␉}␊
265␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR)␊
266␉{␊
267␉␉start = 73;␊
268␉}␊
269␉␊
270␉// Check that the spd part name is zero terminated and that it is ascii:␊
271␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
272␉for (i = start; i < start + sizeof(asciiPartNo); i++)␊
273␉{␊
274␉␉READ_SPD(spd, base, slot, (uint8_t)i); // only read once the corresponding model part (ddr3 or ddr2)␊
275␉␉c = spd[i];␊
276␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
277␉␉{␊
278␉␉␉// It seems that System Profiler likes only letters and digits...␊
279␉␉␉asciiPartNo[index++] = c;␊
280␉␉}␊
281␉␉else if (!isascii(c))␊
282␉␉{␊
283␉␉␉break;␊
284␉␉}␊
285␉}␊
286␊
287␉return strdup(asciiPartNo);␊
288}␊
289␊
290int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
291␊
292/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
293static void read_smb_intel(pci_dt_t *smbus_dev)␊
294{␊
295␉int␉␉i, speed;␊
296␉uint8_t␉␉spd_size, spd_type;␊
297␉uint32_t␉base, mmio, hostc;␊
298␉uint16_t␉cmd;␊
299//␉bool␉␉dump = false;␊
300␉RamSlotInfo_t␉*slot;␊
301␊
302␉cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
303␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
304␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
305␊
306␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
307␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
308␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
309␊
310␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",␊
311␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
312␊
313␉//Azi: no use for this!␊
314␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
315␉// needed at least for laptops␊
316␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
317␊
318␉char spdbuf[MAX_SPD_SIZE];␊
319␉// Search MAX_RAM_SLOTS slots␊
320␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊
321␉{␊
322␉␉slot = &Platform.RAM.DIMM[i];␊
323␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
324␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
325␉␉// Check spd is present␊
326␉␉if (spd_size && (spd_size != 0xff))␊
327␉␉{␊
328␉␉␉slot->spd = spdbuf;␊
329␉␉␉slot->InUse = true;␊
330␊
331␉␉␉bzero(slot->spd, spd_size);␊
332␊
333␉␉␉// Copy spd data into buffer␊
334␊
335␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
336␉␉␉init_spd(slot->spd, base, i);␊
337␊
338␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
339␉␉␉{␊
340␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
341␊
342␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
343␉␉␉␉␉+ (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
344␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
345␉␉␉␉␉slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
346␉␉␉␉break;␊
347␊
348␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
349␊
350␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
351␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
352␉␉␉␉break;␊
353␊
354␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
355␊
356␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
357␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
358␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
359␊
360␉␉␉␉break;␊
361␊
362␉␉␉␉default:␊
363␉␉␉␉␉slot->ModuleSize = 0;␊
364␉␉␉␉break;␊
365␊
366␉␉␉}␊
367␊
368␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
369␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
370␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE)␊
371␉␉␉{␊
372␉␉␉␉continue;␊
373␉␉␉}␊
374␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
375␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
376␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
377␊
378␉␉␉// determine spd speed␊
379␉␉␉speed = (uint16_t)getDDRspeedMhz(slot->spd);␊
380␉␉␉if (slot->Frequency < speed)␊
381␉␉␉{␊
382␉␉␉␉slot->Frequency = speed;␊
383␉␉␉}␊
384␊
385␉␉␉// pci memory controller if available, is more reliable␊
386␉␉␉if (Platform.RAM.Frequency > 0)␊
387␉␉␉{␊
388␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
389␉␉␉␉// now round off special cases␊
390␉␉␉␉uint32_t fmod100 = freq %100;␊
391␉␉␉␉switch(fmod100)␊
392␉␉␉␉{␊
393␉␉␉␉␉case 1:␉freq--;␉break;␊
394␉␉␉␉␉case 32:␉freq++;␉break;␊
395␉␉␉␉␉case 65:␉freq++; break;␊
396␉␉␉␉␉case 98:␉freq+=2;break;␊
397␉␉␉␉␉case 99:␉freq++; break;␊
398␉␉␉␉}␊
399␉␉␉␉slot->Frequency = freq;␊
400␉␉␉}␊
401␊
402␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n",␊
403␉␉␉␉i,␊
404␉␉␉␉(int)slot->Type,␊
405␉␉␉␉slot->ModuleSize, ␊
406␉␉␉␉spd_memory_types[spd_type],␊
407␉␉␉␉slot->Frequency,␊
408␉␉␉␉slot->Vendor,␊
409␉␉␉␉slot->PartNo,␊
410␉␉␉␉slot->SerialNo);␊
411␉␉␉␉slot->InUse = true;␊
412␉␉}␊
413␊
414␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
415␉␉Platform.DMI.DIMM[i]= ␊
416 ␉(uint32_t)((i > 0 && Platform.RAM.DIMM[1].InUse == false && fullBanks && Platform.DMI.CntMemorySlots == 2) ? mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
417␊
418␉␉slot->spd = NULL;␊
419␊
420␉} // for␊
421}␊
422␊
423static struct smbus_controllers_t smbus_controllers[] = {␊
424␊
425␉{0x8086, 0x1C22, "P67", read_smb_intel }, // Z68, Q67␊
426␉{0x8086, 0x1D22, "X79", read_smb_intel },␊
427␉{0x8086, 0x1D70, "X79", read_smb_intel },␊
428␉{0x8086, 0x1D71, "X79", read_smb_intel },␊
429␉{0x8086, 0x1D72, "C608", read_smb_intel },␊
430␉{0x8086, 0x1E22, "Z77", read_smb_intel }, // H77, Q77␊
431␉{0x8086, 0x2330, "DH89xxCC", read_smb_intel },␊
432␉{0x8086, 0x2413, "82801AA", read_smb_intel },␊
433␉{0x8086, 0x2423, "BAM", read_smb_intel },␊
434␉{0x8086, 0x2443, "BAM", read_smb_intel },␊
435␉{0x8086, 0x2483, "CAM", read_smb_intel },␊
436␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
437␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
438␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
439␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
440␉{0x8086, 0x269B, "ESB", read_smb_intel },␊
441␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
442␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
443␉{0x8086, 0x2930, "ICH9", read_smb_intel },␊
444␉{0x8086, 0x3A30, "ICH10", read_smb_intel },␊
445␉{0x8086, 0x3A60, "ICH10", read_smb_intel },␊
446␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
447␉{0x8086, 0x5032, "EP80579", read_smb_intel },␊
448␉{0x8086, 0x8119, "US15W", read_smb_intel },␊
449␉{0x8086, 0x8C22, "HSW", read_smb_intel }, // Z87, H87, Q87, H81␊
450␉{0x8086, 0x8CA2, "Z97/H97", read_smb_intel }, // new␊
451␉{0x8086, 0x8D22, "X99", read_smb_intel }, // new␊
452␉{0x8086, 0x9C22, "HSW-ULT", read_smb_intel }␊
453␊
454};␊
455␊
456// initial call : pci_dt = root_pci_dev;␊
457// find_and_read_smbus_controller(root_pci_dev);␊
458bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
459{␊
460␉pci_dt_t␉*current = pci_dt;␊
461␉int i;␊
462␊
463␉while (current)␊
464␉{␊
465#if 0␊
466␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
467␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
468␉␉current->class_id, current->vendor_id, current->device_id, ␊
469␉␉get_pci_dev_path(current));␊
470#endif␊
471␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
472␉␉{␊
473␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
474␉␉␉{␊
475␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
476␉␉␉␉return true;␊
477␉␉␉}␊
478␉␉}␊
479␉␉find_and_read_smbus_controller(current->children);␊
480␉␉current = current->next;␊
481␉}␊
482␉return false; // not found␊
483}␊
484␊
485void scan_spd(PlatformInfo_t *p)␊
486{␊
487␉find_and_read_smbus_controller(root_pci_dev);␊
488}␊
489␊
490

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