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Root/trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM",␉␉␉␉/* 00h Undefined */␊
31␉"STD FPM DRAM",␉␉␉/* 01h FPM */␊
32␉"EDO",␉␉␉␉/* 02h EDO */␊
33␉"PIPE NIBBLE",␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM",␉␉␉/* 04h SDRAM */␊
35␉"ROM",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM"␉␉␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉␉␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM",␉␉␉/* 08h SDRAM DDR 2 */␊
39␉"DDR2 SDRAM FB-DIMM",␉␉/* 09h Undefined */␊
40␉"DDR2 SDRAM FB-DIMM Probe",␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM",␉␉␉/* 0Bh SDRAM DDR 3 */␊
42␉"DDR4 SDRAM"␉␉␉/* 0Ch SDRAM DDR 4 */␊
43};␊
44␊
45#define UNKNOWN_MEM_TYPE 2␊
46static uint8_t spd_mem_to_smbios[] =␊
47{␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
51␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
52␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
53␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
54␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
55␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
56␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
58␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
59␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
60};␊
61#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
62␊
63#define rdtsc(low,high) \␊
64__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
65␊
66#define SMBHSTSTS 0␊
67#define SMBHSTCNT 2␊
68#define SMBHSTCMD 3␊
69#define SMBHSTADD 4␊
70#define SMBHSTDAT 5␊
71#define SBMBLKDAT 7␊
72␊
73int spd_indexes[] = {␊
74␉SPD_MEMORY_TYPE,␊
75␉SPD_DDR3_MEMORY_BANK,␊
76␉SPD_DDR3_MEMORY_CODE,␊
77␉SPD_NUM_ROWS,␊
78␉SPD_NUM_COLUMNS,␊
79␉SPD_NUM_DIMM_BANKS,␊
80␉SPD_NUM_BANKS_PER_SDRAM,␊
81␉4,7,8,9,12,64, /* TODO: give names to these values */␊
82␉95,96,97,98, 122,123,124,125 /* UIS */␊
83};␊
84#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
85␊
86/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
87␊
88unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
89{␊
90␉int l1, h1, l2, h2;␊
91␉unsigned long long t;␊
92␊
93␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
94␉outb(base + SMBHSTDAT, 0xff);␊
95␊
96␉rdtsc(l1, h1);␊
97␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
98␉{␊
99␉␉rdtsc(l2, h2);␊
100␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
101␉␉if (t > 5)␊
102␉␉{␊
103␉␉␉return 0xFF;␉// break␊
104␉␉}␊
105␉}␊
106␊
107␉outb(base + SMBHSTCMD, cmd);␊
108␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
109␉outb(base + SMBHSTCNT, 0x48 );␊
110␊
111␉rdtsc(l1, h1);␊
112␊
113␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait till command finished␊
114␉{␊
115␉␉rdtsc(l2, h2);␊
116␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
117␉␉if (t > 5)␊
118␉␉{␊
119␉␉␉break;␉// break after 5ms␊
120␉␉}␊
121␉}␊
122␉return inb(base + SMBHSTDAT);␊
123}␊
124␊
125/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
126#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
127␊
128/** Read from spd *used* values only*/␊
129static void init_spd(char * spd, uint32_t base, int slot)␊
130{␊
131␉int i;␊
132␉for (i = 0; i < SPD_INDEXES_SIZE; i++)␊
133␉{␊
134␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
135␉}␊
136}␊
137␊
138// Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,␊
139// have different formats, always return a valid ptr.␊
140const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
141{␊
142␉uint8_t bank = 0;␊
143␉uint8_t code = 0;␊
144␉int i = 0;␊
145␉uint8_t * spd = (uint8_t *) slot->spd;␊
146␊
147␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
148␉{␊
149␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
150␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
151␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
152␉␉{␊
153␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
154␉␉␉{␊
155␉␉␉␉return vendorMap[i].name;␊
156␉␉␉}␊
157␉␉}␊
158␉}␊
159␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
160␉{␊
161␉␉if(spd[64]==0x7f)␊
162␉␉{␊
163␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
164␉␉␉{␊
165␉␉␉␉bank++;␊
166␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
167␉␉␉}␊
168␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
169␉␉␉code = spd[i];␊
170␉␉}␊
171␉␉else␊
172␉␉{␊
173␉␉␉code = spd[64];␊
174␉␉␉bank = 0;␊
175␉␉}␊
176␊
177␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
178␉␉{␊
179␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
180␉␉␉{␊
181␉␉␉␉return vendorMap[i].name;␊
182␉␉␉}␊
183␉␉}␊
184␉}␊
185␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
186␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊
187␉␉return "Unifosa";␊
188␉}␊
189␉return "NoName";␊
190}␊
191␊
192/* Get Default Memory Module Speed (no overclocking handled) */␊
193int getDDRspeedMhz(const char * spd)␊
194{␊
195␊
196␉if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))␊
197␉{␊
198␉␉switch(spd[9])␊
199␉␉{␊
200␉␉␉case 0x50:␊
201␉␉␉␉return 400;␊
202␉␉␉case 0x3d:␊
203␉␉␉␉return 533;␊
204␉␉␉case 0x30:␊
205␉␉␉␉return 667;␊
206␉␉␉case 0x25:␊
207␉␉␉default:␊
208␉␉␉␉return 800;␊
209␉␉␉case 0x1E:␊
210␉␉␉␉return 1066;␊
211␉␉}␊
212␉}␊
213␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
214␉{␊
215␉␉switch(spd[12])␊
216␉␉{␊
217␉␉␉case 0x0f:␊
218␉␉␉␉return 1066;␊
219␉␉␉case 0x0c:␊
220␉␉␉␉return 1333;␊
221␉␉␉case 0x0a:␊
222␉␉␉␉return 1600;␊
223␉␉␉case 0x14:␊
224␉␉␉default:␊
225␉␉␉␉return 800;␊
226␉␉}␊
227␉}␊
228␉return 800; // default freq for unknown types␊
229}␊
230␊
231#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
232#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
233␊
234/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
235const char *getDDRSerial(const char* spd)␊
236{␊
237␉static char asciiSerial[17];␊
238␊
239␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
240␉{␊
241␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
242␉}␊
243␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
244␉{␊
245␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
246␉}␊
247␉else␊
248␉{␊
249␉␉sprintf(asciiSerial, "0000000000000000");␊
250␉}␊
251␊
252␉return strdup(asciiSerial);␊
253}␊
254␊
255/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
256const char *getDDRPartNum(char *spd, uint32_t base, int slot)␊
257{␊
258␉int i, start = 0, index = 0;␊
259␉char c;␊
260␉static char asciiPartNo[32];␊
261␊
262␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
263␉{␊
264␉␉start = 128;␊
265␉}␊
266␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR)␊
267␉{␊
268␉␉start = 73;␊
269␉}␊
270␉␊
271␉// Check that the spd part name is zero terminated and that it is ascii:␊
272␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
273␉for (i = start; i < start + sizeof(asciiPartNo); i++)␊
274␉{␊
275␉␉READ_SPD(spd, base, slot, (uint8_t)i); // only read once the corresponding model part (ddr3 or ddr2)␊
276␉␉c = spd[i];␊
277␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
278␉␉{␊
279␉␉␉// It seems that System Profiler likes only letters and digits...␊
280␉␉␉asciiPartNo[index++] = c;␊
281␉␉}␊
282␉␉else if (!isascii(c))␊
283␉␉{␊
284␉␉␉break;␊
285␉␉}␊
286␉}␊
287␊
288␉return strdup(asciiPartNo);␊
289}␊
290␊
291int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
292␊
293/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
294static void read_smb_intel(pci_dt_t *smbus_dev)␊
295{␊
296␉int␉␉i, speed;␊
297␉uint8_t␉␉spd_size, spd_type;␊
298␉uint32_t␉base, mmio, hostc;␊
299␉uint16_t␉cmd;␉␉// Command␊
300//␉bool␉␉dump = false;␊
301␉RamSlotInfo_t␉*slot;␊
302␊
303␉cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
304␊
305␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
306␊
307␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
308␊
309␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
310␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
311␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
312␊
313␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",␊
314␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
315␊
316␉//Azi: no use for this!␊
317␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
318␉// needed at least for laptops␊
319␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
320␊
321␉char spdbuf[MAX_SPD_SIZE];␊
322␉// Search MAX_RAM_SLOTS slots␊
323␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊
324␉{␊
325␉␉slot = &Platform.RAM.DIMM[i];␊
326␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
327␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
328␉␉// Check spd is present␊
329␉␉if (spd_size && (spd_size != 0xff))␊
330␉␉{␊
331␉␉␉slot->spd = spdbuf;␊
332␉␉␉slot->InUse = true;␊
333␊
334␉␉␉bzero(slot->spd, spd_size);␊
335␊
336␉␉␉// Copy spd data into buffer␊
337␊
338␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
339␉␉␉init_spd(slot->spd, base, i);␊
340␊
341␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
342␉␉␉{␊
343␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
344␊
345␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
346␉␉␉␉␉+ (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
347␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
348␉␉␉␉␉slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
349␉␉␉␉break;␊
350␊
351␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
352␊
353␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
354␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
355␉␉␉␉break;␊
356␊
357␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
358␊
359␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
360␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
361␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
362␊
363␉␉␉␉break;␊
364␊
365␉␉␉␉default:␊
366␉␉␉␉␉slot->ModuleSize = 0;␊
367␉␉␉␉break;␊
368␊
369␉␉␉}␊
370␊
371␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
372␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
373␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE)␊
374␉␉␉{␊
375␉␉␉␉continue;␊
376␉␉␉}␊
377␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
378␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
379␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
380␊
381␉␉␉// determine spd speed␊
382␉␉␉speed = (uint16_t)getDDRspeedMhz(slot->spd);␊
383␉␉␉if (slot->Frequency < speed)␊
384␉␉␉{␊
385␉␉␉␉slot->Frequency = speed;␊
386␉␉␉}␊
387␊
388␉␉␉// pci memory controller if available, is more reliable␊
389␉␉␉if (Platform.RAM.Frequency > 0)␊
390␉␉␉{␊
391␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
392␉␉␉␉// now round off special cases␊
393␉␉␉␉uint32_t fmod100 = freq %100;␊
394␉␉␉␉switch(fmod100)␊
395␉␉␉␉{␊
396␉␉␉␉␉case 1:␉freq--;␉break;␊
397␉␉␉␉␉case 32:␉freq++;␉break;␊
398␉␉␉␉␉case 65:␉freq++; break;␊
399␉␉␉␉␉case 98:␉freq+=2;break;␊
400␉␉␉␉␉case 99:␉freq++; break;␊
401␉␉␉␉}␊
402␉␉␉␉slot->Frequency = freq;␊
403␉␉␉}␊
404␊
405␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n",␊
406␉␉␉␉i,␊
407␉␉␉␉(int)slot->Type,␊
408␉␉␉␉slot->ModuleSize, ␊
409␉␉␉␉spd_memory_types[spd_type],␊
410␉␉␉␉slot->Frequency,␊
411␉␉␉␉slot->Vendor,␊
412␉␉␉␉slot->PartNo,␊
413␉␉␉␉slot->SerialNo);␊
414␉␉␉␉slot->InUse = true;␊
415␉␉}␊
416␊
417␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
418␉␉Platform.DMI.DIMM[i]= ␊
419 ␉(uint32_t)((i > 0 && Platform.RAM.DIMM[1].InUse == false && fullBanks && Platform.DMI.CntMemorySlots == 2) ? mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
420␊
421␉␉slot->spd = NULL;␊
422␊
423␉} // for␊
424}␊
425␊
426static struct smbus_controllers_t smbus_controllers[] = {␊
427␊
428␉{0x8086, 0x1C22, "P67", read_smb_intel }, // Z68, Q67␊
429␉{0x8086, 0x1D22, "X79", read_smb_intel },␊
430␉{0x8086, 0x1D70, "X79", read_smb_intel },␊
431␉{0x8086, 0x1D71, "X79", read_smb_intel },␊
432␉{0x8086, 0x1D72, "C608", read_smb_intel },␊
433␉{0x8086, 0x1E22, "Z77", read_smb_intel }, // H77, Q77␊
434␉{0x8086, 0x2330, "DH89xxCC", read_smb_intel },␊
435␉{0x8086, 0x2413, "82801AA", read_smb_intel },␊
436␉{0x8086, 0x2423, "BAM", read_smb_intel },␊
437␉{0x8086, 0x2443, "BAM", read_smb_intel },␊
438␉{0x8086, 0x2483, "CAM", read_smb_intel },␊
439␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
440␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
441␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
442␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
443␉{0x8086, 0x269B, "ESB", read_smb_intel },␊
444␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
445␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
446␉{0x8086, 0x2930, "ICH9", read_smb_intel },␊
447␉{0x8086, 0x3A30, "ICH10", read_smb_intel },␊
448␉{0x8086, 0x3A60, "ICH10", read_smb_intel },␊
449␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
450␉{0x8086, 0x5032, "EP80579", read_smb_intel },␊
451␉{0x8086, 0x8119, "US15W", read_smb_intel },␊
452␉{0x8086, 0x8C22, "HSW", read_smb_intel }, // Z87, H87, Q87, H81␊
453␉{0x8086, 0x8CA2, "Z97/H97", read_smb_intel }, // new␊
454␉{0x8086, 0x8D22, "X99", read_smb_intel }, // new␊
455␉{0x8086, 0x9C22, "HSW-ULT", read_smb_intel }␊
456␊
457};␊
458␊
459// initial call : pci_dt = root_pci_dev;␊
460// find_and_read_smbus_controller(root_pci_dev);␊
461bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
462{␊
463␉pci_dt_t␉*current = pci_dt;␊
464␉int i;␊
465␊
466␉while (current)␊
467␉{␊
468#if 0␊
469␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
470␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
471␉␉current->class_id, current->vendor_id, current->device_id, ␊
472␉␉get_pci_dev_path(current));␊
473#endif␊
474␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
475␉␉{␊
476␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
477␉␉␉{␊
478␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
479␉␉␉␉return true;␊
480␉␉␉}␊
481␉␉}␊
482␉␉find_and_read_smbus_controller(current->children);␊
483␉␉current = current->next;␊
484␉}␊
485␉return false; // not found␊
486}␊
487␊
488void scan_spd(PlatformInfo_t *p)␊
489{␊
490␉find_and_read_smbus_controller(root_pci_dev);␊
491}␊
492␊
493

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