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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28uint64_t timeRDTSC(void)␊
29{␊
30␉int␉␉attempts = 0;␊
31␉uint64_t latchTime;␊
32␉uint64_t␉saveTime,intermediate;␊
33␉unsigned int timerValue, lastValue;␊
34␉//boolean_t␉int_enabled;␊
35␉/*␊
36␉ * Table of correction factors to account for␊
37␉ *␉ - timer counter quantization errors, and␊
38␉ *␉ - undercounts 0..5␊
39␉ */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45␉uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52␉};␊
53␊
54␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊
55␊
56restart:␊
57␉if (attempts >= 9) // increase to up to 9 attempts.␊
58␉{␊
59␉ // This will flash-reboot. TODO: Use tscPanic instead.␊
60␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
61␉}␊
62␉attempts++;␊
63␉enable_PIT2();␉␉// turn on PIT2␊
64␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
65␉latchTime = rdtsc64();␉// get the time stamp to time ␊
66␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
67␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
68␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
69␉get_PIT2(&lastValue);␊
70␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
71␉do {␊
72␉␉intermediate = get_PIT2(&timerValue);␊
73␉␉if (timerValue > lastValue)␊
74␉␉{␊
75␉␉␉// Timer wrapped␊
76␉␉␉set_PIT2(0);␊
77␉␉␉disable_PIT2();␊
78␉␉␉goto restart;␊
79␉␉}␊
80␉␉lastValue = timerValue;␊
81␉} while (timerValue > 5);␊
82␉printf("timerValue␉ %d\n",timerValue);␊
83␉printf("intermediate 0x%016llX\n",intermediate);␊
84␉printf("saveTime␉ 0x%016llX\n",saveTime);␊
85 ␊
86␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
87␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
88␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
89␉intermediate += latchTime;␉␉// add on our save fudge␊
90␊
91␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
92␉disable_PIT2();␉␉␉// turn off PIT 2␊
93␊
94␉//ml_set_interrupts_enabled(int_enabled);␊
95␉return intermediate;␊
96}␊
97␊
98/*␊
99 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
100 */␊
101static uint64_t measure_tsc_frequency(void)␊
102{␊
103␉uint64_t tscStart;␊
104␉uint64_t tscEnd;␊
105␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
106␉unsigned long pollCount;␊
107␉uint64_t retval = 0;␊
108␉int i;␊
109␊
110␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
111␉ * counter 2. We run this loop 3 times to make sure the cache␊
112␉ * is hot and we take the minimum delta from all of the runs.␊
113␉ * That is to say that we're biased towards measuring the minimum␊
114␉ * number of TSC ticks that occur while waiting for the timer to␊
115␉ * expire. That theoretically helps avoid inconsistencies when␊
116␉ * running under a VM if the TSC is not virtualized and the host␊
117␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
118␉ */␊
119␉for(i = 0; i < 10; ++i)␊
120␉{␊
121␉␉enable_PIT2();␊
122␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
123␉␉tscStart = rdtsc64();␊
124␉␉pollCount = poll_PIT2_gate();␊
125␉␉tscEnd = rdtsc64();␊
126␉␉/* The poll loop must have run at least a few times for accuracy */␊
127␉␉if (pollCount <= 1)␊
128␉␉{␊
129␉␉␉continue;␊
130␉␉}␊
131␉␉/* The TSC must increment at LEAST once every millisecond.␊
132␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
133␉␉ * be >= 30. Anything less and the processor is way too slow.␊
134␉␉ */␊
135␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
136␉␉{␊
137␉␉␉continue;␊
138␉␉}␊
139␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
140␉␉if ( (tscEnd - tscStart) < tscDelta )␊
141␉␉{␊
142␉␉␉tscDelta = tscEnd - tscStart;␊
143␉␉}␊
144␉}␊
145␉/* tscDelta is now the least number of TSC ticks the processor made in␊
146␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
147␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
148␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
149␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
150␉ * dividing by the milliseconds, we simply multiply by 1000.␊
151␉ */␊
152␊
153␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
154␉ * that we're going to multiply by 1000 first so we do need at least some␊
155␉ * arithmetic headroom. For now, 32-bit should be enough.␊
156␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
157␉ */␊
158␉if (tscDelta > (1ULL<<32))␊
159␉{␊
160␉␉retval = 0;␊
161␉}␊
162␉else␊
163␉{␊
164␉␉retval = tscDelta * 1000 / 30;␊
165␉}␊
166␉disable_PIT2();␊
167␉return retval;␊
168}␊
169␊
170/*␊
171 * Original comment/code:␊
172 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
173 *␊
174 * Measures the Actual Performance Frequency in Hz (64-bit)␊
175 * (just a naming change, mperf --> aperf )␊
176 */␊
177static uint64_t measure_aperf_frequency(void)␊
178{␊
179␉uint64_t aperfStart;␊
180␉uint64_t aperfEnd;␊
181␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
182␉unsigned long pollCount;␊
183␉uint64_t retval = 0;␊
184␉int i;␊
185␊
186␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
187␉ * counter 2. We run this loop 3 times to make sure the cache␊
188␉ * is hot and we take the minimum delta from all of the runs.␊
189␉ * That is to say that we're biased towards measuring the minimum␊
190␉ * number of APERF ticks that occur while waiting for the timer to␊
191␉ * expire.␊
192␉ */␊
193␉for(i = 0; i < 10; ++i)␊
194␉{␊
195␉␉enable_PIT2();␊
196␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
197␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
198␉␉pollCount = poll_PIT2_gate();␊
199␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
200␉␉/* The poll loop must have run at least a few times for accuracy */␊
201␉␉if (pollCount <= 1)␊
202␉␉{␊
203␉␉␉continue;␊
204␉␉}␊
205␉␉/* The TSC must increment at LEAST once every millisecond.␊
206␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
207␉␉ * be >= 30. Anything less and the processor is way too slow.␊
208␉␉ */␊
209␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
210␉␉{␊
211␉␉␉continue;␊
212␉␉}␊
213␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
214␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
215␉␉{␊
216␉␉␉aperfDelta = aperfEnd - aperfStart;␊
217␉␉}␊
218␉}␊
219␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
220␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
221␉ */␊
222␊
223␉if (aperfDelta > (1ULL<<32))␊
224␉{␊
225␉␉retval = 0;␊
226␉}␊
227␉else␊
228␉{␊
229␉␉retval = aperfDelta * 1000 / 30;␊
230␉}␊
231␉disable_PIT2();␊
232␉return retval;␊
233}␊
234␊
235/*␊
236 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
237 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
238 *␉ a max multi. (used to calculate the FSB freq.),␊
239 *␉ and a current multi. (used to calculate the CPU freq.)␊
240 * - fsbFrequency = tscFrequency / multi␊
241 * - cpuFrequency = fsbFrequency * multi␊
242 */␊
243void scan_cpu(PlatformInfo_t *p)␊
244{␊
245␉uint64_t␉tscFrequency␉␉= 0;␊
246␉uint64_t␉fsbFrequency␉␉= 0;␊
247␉uint64_t␉cpuFrequency␉␉= 0;␊
248␉uint64_t␉msr␉␉␉= 0;␊
249␉uint64_t␉flex_ratio␉␉= 0;␊
250␊
251␉uint32_t␉max_ratio␉␉= 0;␊
252␉uint32_t␉min_ratio␉␉= 0;␊
253␉uint32_t␉reg[4];␊
254␊
255␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
256␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
257␉uint8_t␉␉currdiv␉␉␉= 0;␊
258␉uint8_t␉␉currcoef␉␉= 0;␊
259␉uint8_t␉␉maxdiv␉␉␉= 0;␊
260␉uint8_t␉␉maxcoef␉␉␉= 0;␊
261␊
262␉const char␉*newratio;␊
263␉char␉␉str[128];␊
264␊
265␉int␉␉len␉␉␉= 0;␊
266␉int␉␉myfsb␉␉␉= 0;␊
267␊
268␉/* get cpuid values */␊
269␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
270␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
271␊
272␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
273␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
274␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
275␊
276␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
277␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊
278␉{␊
279␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
280␉}␊
281␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊
282␉{␊
283␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
284␉}␊
285␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
286␉{␊
287␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
288␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
289␉}␊
290␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
291␉{␊
292␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
293␉}␊
294␊
295// #if DEBUG_CPU␊
296␉{␊
297␉␉int␉␉i;␊
298␉␉DBG("CPUID Raw Values:\n");␊
299␉␉for (i = 0; i < CPUID_MAX; i++) {␊
300␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊
301␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
302␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
303␉␉}␊
304␉}␊
305// #endif␊
306␊
307/*␊
308 EAX (Intel):␊
309 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
310 +--------+----------------+--------+----+----+--------+--------+--------+␊
311 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
312 +--------+----------------+--------+----+----+--------+--------+--------+␊
313␊
314 EAX (AMD):␊
315 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
316 +--------+----------------+--------+----+----+--------+--------+--------+␊
317 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
318 +--------+----------------+--------+----+----+--------+--------+--------+␊
319*/␊
320␊
321␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
322␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
323␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
324␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
325␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
326␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
327␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
328␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
329␊
330␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
331␊
332␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
333␉␉p->CPU.Family == 0x06 &&␊
334␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊
335␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
336␉␉)␊
337␉{␊
338␉␉/*␊
339␉␉ * Find the number of enabled cores and threads␊
340␉␉ * (which determines whether SMT/Hyperthreading is active).␊
341␉␉ */␊
342␉␉switch (p->CPU.Model)␊
343␉␉{␊
344␉␉␉case CPUID_MODEL_NEHALEM:␊
345␉␉␉case CPUID_MODEL_FIELDS:␊
346␉␉␉case CPUID_MODEL_DALES:␊
347␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
348␉␉␉case CPUID_MODEL_JAKETOWN:␊
349␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
350␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
351␉␉␉case CPUID_MODEL_HASWELL:␊
352␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
353␉␉␉//case CPUID_MODEL_HASWELL_H:␊
354␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
355␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
356␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
357␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊
358␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
359␉␉␉␉break;␊
360␊
361␉␉␉case CPUID_MODEL_DALES_32NM:␊
362␉␉␉case CPUID_MODEL_WESTMERE:␊
363␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
364␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
365␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊
366␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
367␉␉␉␉break;␊
368␊
369␉␉␉default:␊
370␉␉␉␉p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
371␉␉␉␉p->CPU.NoThreads = (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊
372␉␉␉␉//workaround for N270. I don't know why it detected wrong␊
373␉␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (p->CPU.Stepping == 2))␊
374␉␉␉␉{␊
375␉␉␉␉␉p->CPU.NoCores = 1;␊
376␉␉␉␉}␊
377␉␉␉␉break;␊
378␊
379␉␉} // end switch␊
380␊
381␉}␊
382␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
383␉{␊
384␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
385␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
386␉}␊
387␉else␊
388␉{␊
389␉␉// Use previous method for Cores and Threads␊
390␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
391␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
392␉}␊
393␊
394␉/* get BrandString (if supported) */␊
395␉/* Copyright: from Apple's XNU cpuid.c */␊
396␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
397␉{␊
398␉␉char␉ *s;␊
399␉␉bzero(str, 128);␊
400␉␉/*␊
401␉␉ * The BrandString 48 bytes (max), guaranteed to␊
402␉␉ * be NULL terminated.␊
403␉␉ */␊
404␉␉do_cpuid(0x80000002, reg);␊
405␉␉memcpy(&str[0], (char *)reg, 16);␊
406␉␉do_cpuid(0x80000003, reg);␊
407␉␉memcpy(&str[16], (char *)reg, 16);␊
408␉␉do_cpuid(0x80000004, reg);␊
409␉␉memcpy(&str[32], (char *)reg, 16);␊
410␉␉for (s = str; *s != '\0'; s++)␊
411␉␉{␊
412␉␉␉if (*s != ' ')␊
413␉␉␉{␊
414␉␉␉␉break;␊
415␉␉␉}␊
416␉␉}␊
417␉␉strlcpy(p->CPU.BrandString, s, 48);␊
418␊
419␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
420␉␉{␊
421␉␉␉/*␊
422␉␉␉ * This string means we have a firmware-programmable brand string,␊
423␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
424␉␉␉ */␊
425␉␉␉p->CPU.BrandString[0] = '\0';␊
426␉␉}␊
427␉␉p->CPU.BrandString[47] = '\0';␊
428//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
429␉}␊
430␊
431␉/* setup features */␊
432␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
433␉{␊
434␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
435␉}␊
436␊
437␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
438␉{␊
439␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
440␉}␊
441␊
442␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
443␉{␊
444␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
445␉}␊
446␊
447␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
448␉{␊
449␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
450␉}␊
451␊
452␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
453␉{␊
454␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
455␉}␊
456␊
457␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
458␉{␊
459␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
460␉}␊
461␊
462␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
463␉{␊
464␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
465␉}␊
466␊
467␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
468␉{␊
469␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
470␉}␊
471␊
472␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
473␊
474␉if (p->CPU.NoThreads > p->CPU.NoCores)␊
475␉{␊
476␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
477␉}␊
478␊
479␉tscFrequency = measure_tsc_frequency();␊
480␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊
481␉/* if usual method failed */␊
482␉if ( tscFrequency < 1000 )␉//TEST␊
483␉{␊
484␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊
485␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
486␉}␊
487␉else␊
488␉{␊
489␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊
490␉}␊
491␊
492␉fsbFrequency = 0;␊
493␉cpuFrequency = 0;␊
494␊
495␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
496␉{␊
497␉␉int intelCPU = p->CPU.Model;␊
498␉␉if (p->CPU.Family == 0x06)␊
499␉␉{␊
500␉␉␉/* Nehalem CPU model */␊
501␉␉␉switch (p->CPU.Model)␊
502␉␉␉{␊
503␉␉␉␉case CPUID_MODEL_NEHALEM:␊
504␉␉␉␉case CPUID_MODEL_FIELDS:␊
505␉␉␉␉case CPUID_MODEL_DALES:␊
506␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
507␉␉␉␉case CPUID_MODEL_WESTMERE:␊
508␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
509␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
510/* --------------------------------------------------------- */␊
511␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
512␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
513␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
514␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
515␉␉␉␉case CPUID_MODEL_HASWELL:␊
516␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
517␊
518␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
519␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
520/* --------------------------------------------------------- */␊
521␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
522␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
523␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
524␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
525␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
526␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
527␉␉␉␉␉if (bitfield(msr, 16, 16))␊
528␉␉␉␉␉{␊
529␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
530␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
531␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
532␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
533␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
534␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
535␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
536␉␉␉␉␉␉// is inadvertently set to 0.␊
537␊
538␉␉␉␉␉␉if (flex_ratio == 0)␊
539␉␉␉␉␉␉{␊
540␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
541␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
542␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
543␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
544␉␉␉␉␉␉}␊
545␉␉␉␉␉␉else␊
546␉␉␉␉␉␉{␊
547␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
548␉␉␉␉␉␉␉{␊
549␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
550␉␉␉␉␉␉␉}␊
551␉␉␉␉␉␉}␊
552␉␉␉␉␉}␊
553␊
554␉␉␉␉␉if (bus_ratio_max)␊
555␉␉␉␉␉{␊
556␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
557␉␉␉␉␉}␊
558␊
559␉␉␉␉␉//valv: Turbo Ratio Limit␊
560␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
561␉␉␉␉␉{␊
562␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
563␊
564␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
565␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
566␉␉␉␉␉}␊
567␉␉␉␉␉else␊
568␉␉␉␉␉{␊
569␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
570␉␉␉␉␉}␊
571␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
572␉␉␉␉␉{␊
573␉␉␉␉␉␉max_ratio = atoi(newratio);␊
574␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
575␉␉␉␉␉␉if (len >= 3)␊
576␉␉␉␉␉␉{␊
577␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
578␉␉␉␉␉␉}␊
579␊
580␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
581␊
582␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
583␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
584␉␉␉␉␉␉{␊
585␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
586␉␉␉␉␉␉␉if (len >= 3)␊
587␉␉␉␉␉␉␉{␊
588␉␉␉␉␉␉␉␉maxdiv = 1;␊
589␉␉␉␉␉␉␉}␊
590␉␉␉␉␉␉␉else␊
591␉␉␉␉␉␉␉{␊
592␉␉␉␉␉␉␉␉maxdiv = 0;␊
593␉␉␉␉␉␉␉}␊
594␉␉␉␉␉␉}␊
595␉␉␉␉␉␉else␊
596␉␉␉␉␉␉{␊
597␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
598␉␉␉␉␉␉}␊
599␉␉␉␉␉}␊
600␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
601␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
602␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
603␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
604␊
605␉␉␉␉myfsb = fsbFrequency / 1000000;␊
606␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
607␉␉␉␉currcoef = bus_ratio_max;␊
608␊
609␉␉␉␉break;␊
610␊
611␉␉␉default:␊
612␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
613␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
614␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
615␉␉␉␉// Non-integer bus ratio for the max-multi␊
616␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
617␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
618␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
619␊
620␉␉␉␉// This will always be model >= 3␊
621␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
622␉␉␉␉{␊
623␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
624␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
625␉␉␉␉}␊
626␉␉␉␉else␊
627␉␉␉␉{␊
628␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
629␉␉␉␉␉// XXX␊
630␉␉␉␉␉maxcoef = currcoef;␊
631␉␉␉␉}␊
632␊
633␉␉␉␉if (!currcoef)␊
634␉␉␉␉{␊
635␉␉␉␉␉currcoef = maxcoef;␊
636␉␉␉␉}␊
637␊
638␉␉␉␉if (maxcoef)␊
639␉␉␉␉{␊
640␉␉␉␉␉if (maxdiv)␊
641␉␉␉␉␉{␊
642␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
643␉␉␉␉␉}␊
644␉␉␉␉␉else␊
645␉␉␉␉␉{␊
646␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
647␉␉␉␉␉}␊
648␊
649␉␉␉␉␉if (currdiv)␊
650␉␉␉␉␉{␊
651␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
652␉␉␉␉␉}␊
653␉␉␉␉␉else␊
654␉␉␉␉␉{␊
655␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
656␉␉␉␉␉}␊
657␊
658␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
659␉␉␉␉}␊
660␉␉␉␉break;␊
661␉␉␉}␊
662␉␉}␊
663␉␉// Mobile CPU␊
664␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
665␉␉{␊
666␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
667␉␉}␊
668␉}␊
669␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
670␉{␊
671␉␉switch(p->CPU.ExtFamily)␊
672␉␉{␊
673␉␉␉case 0x00: //* K8 *//␊
674␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
675␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
676␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
677␉␉␉␉break;␊
678␊
679␉␉␉case 0x01: //* K10 *//␊
680␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
681␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
682␉␉␉␉// EffFreq: effective frequency interface␊
683␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
684␉␉␉␉{␊
685␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
686␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
687␉␉␉␉␉cpuFrequency = aperf;␊
688␉␉␉␉}␊
689␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
690␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
691␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
692␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
693␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
694␊
695␉␉␉␉break;␊
696␊
697␉␉␉case 0x05: //* K14 *//␊
698␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
699␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
700␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
701␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
702␊
703␉␉␉␉break;␊
704␊
705␉␉␉case 0x02: //* K11 *//␊
706␉␉␉␉// not implimented␊
707␉␉␉␉break;␊
708␉␉}␊
709␊
710␉␉if (maxcoef)␊
711␉␉{␊
712␉␉␉if (currdiv)␊
713␉␉␉{␊
714␉␉␉␉if (!currcoef)␊
715␉␉␉␉{␊
716␉␉␉␉␉currcoef = maxcoef;␊
717␉␉␉␉}␊
718␊
719␉␉␉␉if (!cpuFrequency)␊
720␉␉␉␉{␊
721␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
722␉␉␉␉}␊
723␉␉␉␉else␊
724␉␉␉␉{␊
725␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
726␉␉␉␉}␊
727␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
728␉␉␉}␊
729␉␉␉else␊
730␉␉␉{␊
731␉␉␉␉if (!cpuFrequency)␊
732␉␉␉␉{␊
733␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
734␉␉␉␉}␊
735␉␉␉␉else␊
736␉␉␉␉{␊
737␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
738␉␉␉␉}␊
739␉␉␉␉DBG("%d\n", currcoef);␊
740␉␉␉}␊
741␉␉}␊
742␉␉else if (currcoef)␊
743␉␉{␊
744␉␉␉if (currdiv)␊
745␉␉␉{␊
746␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
747␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
748␉␉␉}␊
749␉␉␉else␊
750␉␉␉{␊
751␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
752␉␉␉␉DBG("%d\n", currcoef);␊
753␉␉␉}␊
754␉␉}␊
755␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
756␉}␊
757␉␊
758#if 0␊
759␉if (!fsbFrequency)␊
760␉{␊
761␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
762␉␉DBG("CPU: fsbFrequency = 0! using the default value for FSB!\n");␊
763␉␉cpuFrequency = tscFrequency;␊
764␉}␊
765␊
766␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
767␊
768#endif␊
769␊
770␉p->CPU.MaxCoef = maxcoef;␊
771␉p->CPU.MaxDiv = maxdiv;␊
772␉p->CPU.CurrCoef = currcoef;␊
773␉p->CPU.CurrDiv = currdiv;␊
774␉p->CPU.TSCFrequency = tscFrequency;␊
775␉p->CPU.FSBFrequency = fsbFrequency;␊
776␉p->CPU.CPUFrequency = cpuFrequency;␊
777␊
778␉// keep formatted with spaces instead of tabs␊
779␉DBG("\n---------------------------------------------\n");␊
780 ␉DBG("------------------ CPU INFO -----------------\n");␊
781␉DBG("---------------------------------------------\n");␊
782␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
783␉DBG("Vendor: 0x%x\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
784␉DBG("Family: 0x%x\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
785␉DBG("ExtFamily: 0x%x\n",␉␉p->CPU.ExtFamily);␊
786␉DBG("Signature: %x\n",␉␉p->CPU.Signature);␉␉// CPUID signature␊
787␉DBG("Model: 0x%x\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
788␉DBG("ExtModel: 0x%x\n",␉␉p->CPU.ExtModel);␊
789␉DBG("Stepping: 0x%x\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
790␉DBG("MaxCoef: 0x%x\n",␉␉p->CPU.MaxCoef);␊
791␉DBG("CurrCoef: 0x%x\n",␉␉p->CPU.CurrCoef);␊
792␉DBG("MaxDiv: 0x%x\n",␉␉p->CPU.MaxDiv);␊
793␉DBG("CurrDiv: 0x%x\n",␉␉p->CPU.CurrDiv);␊
794␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
795␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
796␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
797␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
798␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
799␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
800␊
801␉DBG("\n---------------------------------------------\n");␊
802#if DEBUG_CPU␊
803␉pause();␊
804#endif␊
805}␊
806

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