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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28static uint64_t timeRDTSC(void)␊
29{␊
30␉int␉␉attempts = 0;␊
31␉uint64_t latchTime;␊
32␉uint64_t␉saveTime,intermediate;␊
33␉unsigned int timerValue, lastValue;␊
34␉//boolean_t␉int_enabled;␊
35␉/*␊
36␉ * Table of correction factors to account for␊
37␉ *␉ - timer counter quantization errors, and␊
38␉ *␉ - undercounts 0..5␊
39␉ */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45␉uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52␉};␊
53␊
54␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊
55␊
56restart:␊
57␉if (attempts >= 9) // increase to up to 9 attempts.␊
58␉{␊
59␉ // This will flash-reboot. TODO: Use tscPanic instead.␊
60␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
61␉}␊
62␉attempts++;␊
63␉enable_PIT2();␉␉// turn on PIT2␊
64␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
65␉latchTime = rdtsc64();␉// get the time stamp to time ␊
66␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
67␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
68␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
69␉get_PIT2(&lastValue);␊
70␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
71␉do {␊
72␉␉intermediate = get_PIT2(&timerValue);␊
73␉␉if (timerValue > lastValue)␊
74␉␉{␊
75␉␉␉// Timer wrapped␊
76␉␉␉set_PIT2(0);␊
77␉␉␉disable_PIT2();␊
78␉␉␉goto restart;␊
79␉␉}␊
80␉␉lastValue = timerValue;␊
81␉} while (timerValue > 5);␊
82␉printf("timerValue␉ %d\n",timerValue);␊
83␉printf("intermediate 0x%016llX\n",intermediate);␊
84␉printf("saveTime␉ 0x%016llX\n",saveTime);␊
85 ␊
86␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
87␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
88␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
89␉intermediate += latchTime;␉␉// add on our save fudge␊
90␊
91␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
92␉disable_PIT2();␉␉␉// turn off PIT 2␊
93␊
94␉//ml_set_interrupts_enabled(int_enabled);␊
95␉return intermediate;␊
96}␊
97␊
98/*␊
99 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
100 */␊
101static uint64_t measure_tsc_frequency(void)␊
102{␊
103␉uint64_t tscStart;␊
104␉uint64_t tscEnd;␊
105␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
106␉unsigned long pollCount;␊
107␉uint64_t retval = 0;␊
108␉int i;␊
109␊
110␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
111␉ * counter 2. We run this loop 3 times to make sure the cache␊
112␉ * is hot and we take the minimum delta from all of the runs.␊
113␉ * That is to say that we're biased towards measuring the minimum␊
114␉ * number of TSC ticks that occur while waiting for the timer to␊
115␉ * expire. That theoretically helps avoid inconsistencies when␊
116␉ * running under a VM if the TSC is not virtualized and the host␊
117␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
118␉ */␊
119␉for(i = 0; i < 10; ++i)␊
120␉{␊
121␉␉enable_PIT2();␊
122␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
123␉␉tscStart = rdtsc64();␊
124␉␉pollCount = poll_PIT2_gate();␊
125␉␉tscEnd = rdtsc64();␊
126␉␉/* The poll loop must have run at least a few times for accuracy */␊
127␉␉if (pollCount <= 1)␊
128␉␉{␊
129␉␉␉continue;␊
130␉␉}␊
131␉␉/* The TSC must increment at LEAST once every millisecond.␊
132␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
133␉␉ * be >= 30. Anything less and the processor is way too slow.␊
134␉␉ */␊
135␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
136␉␉{␊
137␉␉␉continue;␊
138␉␉}␊
139␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
140␉␉if ( (tscEnd - tscStart) < tscDelta )␊
141␉␉{␊
142␉␉␉tscDelta = tscEnd - tscStart;␊
143␉␉}␊
144␉}␊
145␉/* tscDelta is now the least number of TSC ticks the processor made in␊
146␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
147␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
148␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
149␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
150␉ * dividing by the milliseconds, we simply multiply by 1000.␊
151␉ */␊
152␊
153␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
154␉ * that we're going to multiply by 1000 first so we do need at least some␊
155␉ * arithmetic headroom. For now, 32-bit should be enough.␊
156␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
157␉ */␊
158␉if (tscDelta > (1ULL<<32))␊
159␉{␊
160␉␉retval = 0;␊
161␉}␊
162␉else␊
163␉{␊
164␉␉retval = tscDelta * 1000 / 30;␊
165␉}␊
166␉disable_PIT2();␊
167␉return retval;␊
168}␊
169␊
170/*␊
171 * Original comment/code:␊
172 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
173 *␊
174 * Measures the Actual Performance Frequency in Hz (64-bit)␊
175 * (just a naming change, mperf --> aperf )␊
176 */␊
177static uint64_t measure_aperf_frequency(void)␊
178{␊
179␉uint64_t aperfStart;␊
180␉uint64_t aperfEnd;␊
181␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
182␉unsigned long pollCount;␊
183␉uint64_t retval = 0;␊
184␉int i;␊
185␊
186␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
187␉ * counter 2. We run this loop 3 times to make sure the cache␊
188␉ * is hot and we take the minimum delta from all of the runs.␊
189␉ * That is to say that we're biased towards measuring the minimum␊
190␉ * number of APERF ticks that occur while waiting for the timer to␊
191␉ * expire.␊
192␉ */␊
193␉for(i = 0; i < 10; ++i)␊
194␉{␊
195␉␉enable_PIT2();␊
196␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
197␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
198␉␉pollCount = poll_PIT2_gate();␊
199␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
200␉␉/* The poll loop must have run at least a few times for accuracy */␊
201␉␉if (pollCount <= 1)␊
202␉␉{␊
203␉␉␉continue;␊
204␉␉}␊
205␉␉/* The TSC must increment at LEAST once every millisecond.␊
206␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
207␉␉ * be >= 30. Anything less and the processor is way too slow.␊
208␉␉ */␊
209␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
210␉␉{␊
211␉␉␉continue;␊
212␉␉}␊
213␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
214␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
215␉␉{␊
216␉␉␉aperfDelta = aperfEnd - aperfStart;␊
217␉␉}␊
218␉}␊
219␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
220␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
221␉ */␊
222␊
223␉if (aperfDelta > (1ULL<<32))␊
224␉{␊
225␉␉retval = 0;␊
226␉}␊
227␉else␊
228␉{␊
229␉␉retval = aperfDelta * 1000 / 30;␊
230␉}␊
231␉disable_PIT2();␊
232␉return retval;␊
233}␊
234␊
235/*␊
236 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
237 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
238 *␉ a max multi. (used to calculate the FSB freq.),␊
239 *␉ and a current multi. (used to calculate the CPU freq.)␊
240 * - fsbFrequency = tscFrequency / multi␊
241 * - cpuFrequency = fsbFrequency * multi␊
242 */␊
243void scan_cpu(PlatformInfo_t *p)␊
244{␊
245␉uint64_t␉tscFrequency␉␉= 0;␊
246␉uint64_t␉fsbFrequency␉␉= 0;␊
247␉uint64_t␉cpuFrequency␉␉= 0;␊
248␉uint64_t␉msr␉␉␉= 0;␊
249␉uint64_t␉flex_ratio␉␉= 0;␊
250␊
251␉uint32_t␉max_ratio␉␉= 0;␊
252␉uint32_t␉min_ratio␉␉= 0;␊
253␉uint32_t␉reg[4]; //␉␉= {0, 0, 0, 0};␊
254␉uint32_t␉cores_per_package␉= 0;␊
255␉uint32_t␉logical_per_package␉= 1;␊
256␉uint32_t␉threads_per_core␉= 1;␊
257␊
258␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
259␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
260␉uint8_t␉␉currdiv␉␉␉= 0;␊
261␉uint8_t␉␉currcoef␉␉= 0;␊
262␉uint8_t␉␉maxdiv␉␉␉= 0;␊
263␉uint8_t␉␉maxcoef␉␉␉= 0;␊
264␊
265␉const char␉*newratio;␊
266␉char␉␉str[128];␊
267␉char␉␉*s␉␉␉= 0;␊
268␊
269␉int␉␉len␉␉␉= 0;␊
270␉int␉␉myfsb␉␉␉= 0;␊
271␉int␉␉i␉␉␉= 0;␊
272␊
273␉/* get cpuid values */␊
274␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
275␉p->CPU.Vendor = p->CPU.CPUID[CPUID_0][ebx];␊
276␊
277␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
278␊
279␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((bit(28) & p->CPU.CPUID[CPUID_1][edx]) != 0)) // Intel && HTT/Multicore␊
280␉{␊
281␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
282␉}␊
283␊
284␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
285␊
286␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
287␊
288␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
289␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
290␉{␊
291␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
292␉␉{␊
293␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
294␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
295␉␉␉{␊
296␉␉␉␉break;␊
297␉␉␉}␊
298␉␉␉//cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
299␉␉}␊
300␉}␊
301␊
302␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
303␊
304␉if (i > 0)␊
305␉{␊
306␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
307␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
308␉}␊
309␊
310␉if (cores_per_package == 0)␊
311␉{␊
312␉␉cores_per_package = 1;␊
313␉}␊
314␊
315␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5) // Monitor/Mwait␊
316␉{␊
317␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
318␉}␊
319␉if (p->CPU.CPUID[CPUID_0][0] >= 6) // Thermal/Power␊
320␉{␊
321␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
322␉}␊
323␊
324␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
325␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
326␉{␊
327␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
328␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
329␉}␊
330␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
331␉{␊
332␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
333␉}␊
334␊
335/* http://www.flounder.com/cpuid_explorer2.htm␊
336 EAX (Intel):␊
337 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
338 +--------+----------------+--------+----+----+--------+--------+--------+␊
339 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
340 +--------+----------------+--------+----+----+--------+--------+--------+␊
341␊
342 EAX (AMD):␊
343 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
344 +--------+----------------+--------+----+----+--------+--------+--------+␊
345 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
346 +--------+----------------+--------+----+----+--------+--------+--------+␊
347*/␊
348␊
349␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
350␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
351␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
352␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
353␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
354␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
355␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
356␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
357␊
358␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
359␊
360␉/* get BrandString (if supported) */␊
361␉/* Copyright: from Apple's XNU cpuid.c */␊
362␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
363␉{␊
364␉␉bzero(str, 128);␊
365␉␉/*␊
366␉␉ * The BrandString 48 bytes (max), guaranteed to␊
367␉␉ * be NULL terminated.␊
368␉␉ */␊
369␉␉do_cpuid(0x80000002, reg);␊
370␉␉memcpy(&str[0], (char *)reg, 16);␊
371␉␉do_cpuid(0x80000003, reg);␊
372␉␉memcpy(&str[16], (char *)reg, 16);␊
373␉␉do_cpuid(0x80000004, reg);␊
374␉␉memcpy(&str[32], (char *)reg, 16);␊
375␉␉for (s = str; *s != '\0'; s++)␊
376␉␉{␊
377␉␉␉if (*s != ' ')␊
378␉␉␉{␊
379␉␉␉␉break;␊
380␉␉␉}␊
381␉␉}␊
382␉␉strlcpy(p->CPU.BrandString, s, 48);␊
383␊
384␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
385␉␉{␊
386␉␉␉/*␊
387␉␉␉ * This string means we have a firmware-programmable brand string,␊
388␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
389␉␉␉ */␊
390␉␉␉p->CPU.BrandString[0] = '\0';␊
391␉␉}␊
392␉␉p->CPU.BrandString[47] = '\0';␊
393//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
394␉}␊
395␊
396␉/*␊
397␉ * Find the number of enabled cores and threads␊
398␉ * (which determines whether SMT/Hyperthreading is active).␊
399␉ */␊
400␉switch (p->CPU.Vendor)␊
401␉{␊
402␉␉case CPUID_VENDOR_INTEL:␊
403␉␉␉switch (p->CPU.Model)␊
404␉␉␉{␊
405␉␉␉␉case CPUID_MODEL_NEHALEM:␊
406␉␉␉␉case CPUID_MODEL_FIELDS:␊
407␉␉␉␉case CPUID_MODEL_DALES:␊
408␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
409␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
410␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
411␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
412␊
413␉␉␉␉case CPUID_MODEL_HASWELL:␊
414␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
415␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊
416␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
417␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
418␉␉␉␉//case CPUID_MODEL_:␊
419␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
420␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
421␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
422␉␉␉␉␉break;␊
423␊
424␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
425␉␉␉␉case CPUID_MODEL_WESTMERE:␊
426␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
427␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
428␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
429␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
430␉␉␉␉␉break;␊
431␉␉␉}␊
432␊
433␉␉␉if (p->CPU.NoCores == 0)␊
434␉␉␉{␊
435␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
436␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
437␉␉␉}␊
438␉␉␉break;␊
439␊
440␉␉case CPUID_VENDOR_AMD:␊
441␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
442␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
443␉␉␉if (p->CPU.NoCores == 0)␊
444␉␉␉{␊
445␉␉␉␉p->CPU.NoCores = 1;␊
446␉␉␉}␊
447␊
448␉␉␉if (p->CPU.NoThreads < p->CPU.NoCores)␊
449␉␉␉{␊
450␉␉␉␉p->CPU.NoThreads = p->CPU.NoCores;␊
451␉␉␉}␊
452␊
453␉␉␉break;␊
454␊
455␉␉default:␊
456␉␉␉stop("Unsupported CPU detected! System halted.");␊
457␉}␊
458␊
459␉//workaround for N270. I don't know why it detected wrong␊
460␉// MSR is *NOT* available on the Intel Atom CPU␊
461␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
462␉{␊
463␉␉␉p->CPU.NoCores␉␉= 1;␊
464␉␉␉p->CPU.NoThreads␉= 2;␊
465␉}␊
466␊
467␉/* setup features */␊
468␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
469␉{␊
470␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
471␉}␊
472␊
473␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
474␉{␊
475␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
476␉}␊
477␊
478␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
479␉{␊
480␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
481␉}␊
482␊
483␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
484␉{␊
485␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
486␉}␊
487␊
488␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
489␉{␊
490␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
491␉}␊
492␊
493␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
494␉{␊
495␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
496␉}␊
497␊
498␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
499␉{␊
500␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
501␉}␊
502␊
503␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
504␉{␊
505␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
506␉}␊
507␊
508␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && (p->CPU.NoThreads > p->CPU.NoCores))␊
509␉{␊
510␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
511␉}␊
512␊
513␉tscFrequency = measure_tsc_frequency();␊
514␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊
515␉/* if usual method failed */␊
516␉if ( tscFrequency < 1000 )␉//TEST␊
517␉{␊
518␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊
519␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
520␉}␊
521␉else␊
522␉{␊
523␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊
524␉}␊
525␊
526␉fsbFrequency = 0;␊
527␉cpuFrequency = 0;␊
528␊
529␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
530␉{␊
531␉␉int intelCPU = p->CPU.Model;␊
532␉␉if (p->CPU.Family == 0x06)␊
533␉␉{␊
534␉␉␉/* Nehalem CPU model */␊
535␉␉␉switch (p->CPU.Model)␊
536␉␉␉{␊
537␉␉␉␉case CPUID_MODEL_NEHALEM:␊
538␉␉␉␉case CPUID_MODEL_FIELDS:␊
539␉␉␉␉case CPUID_MODEL_DALES:␊
540␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
541␉␉␉␉case CPUID_MODEL_WESTMERE:␊
542␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
543␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
544/* --------------------------------------------------------- */␊
545␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
546␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
547␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
548␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
549␉␉␉␉case CPUID_MODEL_HASWELL:␊
550␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
551␊
552␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
553␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
554/* --------------------------------------------------------- */␊
555␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
556␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
557␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
558␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
559␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
560␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
561␉␉␉␉␉if (bitfield(msr, 16, 16))␊
562␉␉␉␉␉{␊
563␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
564␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
565␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
566␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
567␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
568␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
569␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
570␉␉␉␉␉␉// is inadvertently set to 0.␊
571␊
572␉␉␉␉␉␉if (flex_ratio == 0)␊
573␉␉␉␉␉␉{␊
574␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
575␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
576␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
577␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
578␉␉␉␉␉␉}␊
579␉␉␉␉␉␉else␊
580␉␉␉␉␉␉{␊
581␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
582␉␉␉␉␉␉␉{␊
583␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
584␉␉␉␉␉␉␉}␊
585␉␉␉␉␉␉}␊
586␉␉␉␉␉}␊
587␊
588␉␉␉␉␉if (bus_ratio_max)␊
589␉␉␉␉␉{␊
590␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
591␉␉␉␉␉}␊
592␊
593␉␉␉␉␉//valv: Turbo Ratio Limit␊
594␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
595␉␉␉␉␉{␊
596␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
597␊
598␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
599␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
600␉␉␉␉␉}␊
601␉␉␉␉␉else␊
602␉␉␉␉␉{␊
603␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
604␉␉␉␉␉}␊
605␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
606␉␉␉␉␉{␊
607␉␉␉␉␉␉max_ratio = atoi(newratio);␊
608␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
609␉␉␉␉␉␉if (len >= 3)␊
610␉␉␉␉␉␉{␊
611␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
612␉␉␉␉␉␉}␊
613␊
614␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
615␊
616␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
617␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
618␉␉␉␉␉␉{␊
619␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
620␉␉␉␉␉␉␉if (len >= 3)␊
621␉␉␉␉␉␉␉{␊
622␉␉␉␉␉␉␉␉maxdiv = 1;␊
623␉␉␉␉␉␉␉}␊
624␉␉␉␉␉␉␉else␊
625␉␉␉␉␉␉␉{␊
626␉␉␉␉␉␉␉␉maxdiv = 0;␊
627␉␉␉␉␉␉␉}␊
628␉␉␉␉␉␉}␊
629␉␉␉␉␉␉else␊
630␉␉␉␉␉␉{␊
631␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
632␉␉␉␉␉␉}␊
633␉␉␉␉␉}␊
634␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
635␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
636␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
637␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
638␊
639␉␉␉␉myfsb = fsbFrequency / 1000000;␊
640␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
641␉␉␉␉currcoef = bus_ratio_max;␊
642␊
643␉␉␉␉break;␊
644␊
645␉␉␉default:␊
646␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
647␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
648␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
649␉␉␉␉// Non-integer bus ratio for the max-multi␊
650␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
651␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
652␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
653␊
654␉␉␉␉// This will always be model >= 3␊
655␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
656␉␉␉␉{␊
657␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
658␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
659␉␉␉␉}␊
660␉␉␉␉else␊
661␉␉␉␉{␊
662␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
663␉␉␉␉␉// XXX␊
664␉␉␉␉␉maxcoef = currcoef;␊
665␉␉␉␉}␊
666␊
667␉␉␉␉if (!currcoef)␊
668␉␉␉␉{␊
669␉␉␉␉␉currcoef = maxcoef;␊
670␉␉␉␉}␊
671␊
672␉␉␉␉if (maxcoef)␊
673␉␉␉␉{␊
674␉␉␉␉␉if (maxdiv)␊
675␉␉␉␉␉{␊
676␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
677␉␉␉␉␉}␊
678␉␉␉␉␉else␊
679␉␉␉␉␉{␊
680␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
681␉␉␉␉␉}␊
682␊
683␉␉␉␉␉if (currdiv)␊
684␉␉␉␉␉{␊
685␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
686␉␉␉␉␉}␊
687␉␉␉␉␉else␊
688␉␉␉␉␉{␊
689␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
690␉␉␉␉␉}␊
691␊
692␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
693␉␉␉␉}␊
694␉␉␉␉break;␊
695␉␉␉}␊
696␉␉}␊
697␉␉// Mobile CPU␊
698␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
699␉␉{␊
700␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
701␉␉}␊
702␉}␊
703␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
704␉{␊
705␉␉switch(p->CPU.ExtFamily)␊
706␉␉{␊
707␉␉␉case 0x00: //* K8 *//␊
708␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
709␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
710␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
711␉␉␉␉break;␊
712␊
713␉␉␉case 0x01: //* K10 *//␊
714␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
715␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
716␉␉␉␉// EffFreq: effective frequency interface␊
717␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
718␉␉␉␉{␊
719␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
720␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
721␉␉␉␉␉cpuFrequency = aperf;␊
722␉␉␉␉}␊
723␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
724␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
725␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
726␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
727␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
728␊
729␉␉␉␉break;␊
730␊
731␉␉␉case 0x05: //* K14 *//␊
732␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
733␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
734␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
735␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
736␊
737␉␉␉␉break;␊
738␊
739␉␉␉case 0x02: //* K11 *//␊
740␉␉␉␉// not implimented␊
741␉␉␉␉break;␊
742␉␉}␊
743␊
744␉␉if (maxcoef)␊
745␉␉{␊
746␉␉␉if (currdiv)␊
747␉␉␉{␊
748␉␉␉␉if (!currcoef)␊
749␉␉␉␉{␊
750␉␉␉␉␉currcoef = maxcoef;␊
751␉␉␉␉}␊
752␊
753␉␉␉␉if (!cpuFrequency)␊
754␉␉␉␉{␊
755␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
756␉␉␉␉}␊
757␉␉␉␉else␊
758␉␉␉␉{␊
759␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
760␉␉␉␉}␊
761␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
762␉␉␉}␊
763␉␉␉else␊
764␉␉␉{␊
765␉␉␉␉if (!cpuFrequency)␊
766␉␉␉␉{␊
767␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
768␉␉␉␉}␊
769␉␉␉␉else␊
770␉␉␉␉{␊
771␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
772␉␉␉␉}␊
773␉␉␉␉DBG("%d\n", currcoef);␊
774␉␉␉}␊
775␉␉}␊
776␉␉else if (currcoef)␊
777␉␉{␊
778␉␉␉if (currdiv)␊
779␉␉␉{␊
780␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
781␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
782␉␉␉}␊
783␉␉␉else␊
784␉␉␉{␊
785␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
786␉␉␉␉DBG("%d\n", currcoef);␊
787␉␉␉}␊
788␉␉}␊
789␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
790␉}␊
791␉␊
792#if 0␊
793␉if (!fsbFrequency)␊
794␉{␊
795␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
796␉␉DBG("CPU: fsbFrequency = 0! using the default value for FSB!\n");␊
797␉␉cpuFrequency = tscFrequency;␊
798␉}␊
799␊
800␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
801␊
802#endif␊
803␊
804␉p->CPU.MaxCoef = maxcoef;␊
805␉p->CPU.MaxDiv = maxdiv;␊
806␉p->CPU.CurrCoef = currcoef;␊
807␉p->CPU.CurrDiv = currdiv;␊
808␉p->CPU.TSCFrequency = tscFrequency;␊
809␉p->CPU.FSBFrequency = fsbFrequency;␊
810␉p->CPU.CPUFrequency = cpuFrequency;␊
811␊
812␉// keep formatted with spaces instead of tabs␊
813␉DBG("\n------------------------------\n");␊
814 ␉DBG("\tCPU INFO\n");␊
815␉DBG("------------------------------\n");␊
816␊
817␉DBG("CPUID Raw Values:\n");␊
818␉for (i = 0; i < CPUID_MAX; i++)␊
819␉{␊
820␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
821␉}␊
822␉DBG("\n");␊
823␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
824␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
825␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
826␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊
827␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
828␉/*switch (p->CPU.Type) {␊
829␉␉case PT_OEM:␊
830␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
831␉␉␉break;␊
832␉␉case PT_OD:␊
833␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
834␉␉␉break;␊
835␉␉case PT_DUAL:␊
836␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
837␉␉␉break;␊
838␉␉case PT_RES:␊
839␉␉␉DBG("Processor type: Intel Reserved\n");␊
840␉␉␉break;␊
841␉␉default:␊
842␉␉␉break;␊
843␉}*/␊
844␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
845␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊
846␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
847␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
848␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
849␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
850␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
851␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
852␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
853␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
854␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
855␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
856␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
857␊
858␉DBG("\n---------------------------------------------\n");␊
859#if DEBUG_CPU␊
860␉pause();␊
861#endif␊
862}␊
863

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