1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * timeRDTSC()␊ |
24 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
25 | * It pauses until the value is latched in the counter␊ |
26 | * and then reads the time stamp counter to return to the caller.␊ |
27 | */␊ |
28 | static uint64_t timeRDTSC(void)␊ |
29 | {␊ |
30 | ␉int␉␉attempts = 0;␊ |
31 | ␉uint64_t ␉latchTime;␊ |
32 | ␉uint64_t␉saveTime,intermediate;␊ |
33 | ␉unsigned int␉timerValue, lastValue;␊ |
34 | ␉//boolean_t␉int_enabled;␊ |
35 | ␉/*␊ |
36 | ␉ * Table of correction factors to account for␊ |
37 | ␉ *␉ - timer counter quantization errors, and␊ |
38 | ␉ *␉ - undercounts 0..5␊ |
39 | ␉ */␊ |
40 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
41 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
42 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
43 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
44 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
45 | ␉uint64_t␉scale[6] = {␊ |
46 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
47 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
48 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
49 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
50 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
51 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
52 | ␉};␊ |
53 | ␊ |
54 | ␉//int_enabled = ml_set_interrupts_enabled(false);␊ |
55 | ␊ |
56 | restart:␊ |
57 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
58 | ␉{␊ |
59 | ␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊ |
60 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
61 | ␉}␊ |
62 | ␉attempts++;␊ |
63 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
64 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
65 | ␉latchTime = rdtsc64();␉// get the time stamp to time␊ |
66 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
67 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
68 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
69 | ␉get_PIT2(&lastValue);␊ |
70 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
71 | ␉do {␊ |
72 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
73 | ␉␉if (timerValue > lastValue)␊ |
74 | ␉␉{␊ |
75 | ␉␉␉// Timer wrapped␊ |
76 | ␉␉␉set_PIT2(0);␊ |
77 | ␉␉␉disable_PIT2();␊ |
78 | ␉␉␉goto restart;␊ |
79 | ␉␉}␊ |
80 | ␉␉lastValue = timerValue;␊ |
81 | ␉} while (timerValue > 5);␊ |
82 | ␉printf("timerValue␉ %d\n",timerValue);␊ |
83 | ␉printf("intermediate 0x%016llX\n",intermediate);␊ |
84 | ␉printf("saveTime␉ 0x%016llX\n",saveTime);␊ |
85 | ␊ |
86 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
87 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
88 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
89 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
90 | ␊ |
91 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
92 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
93 | ␊ |
94 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
95 | ␉return intermediate;␊ |
96 | }␊ |
97 | ␊ |
98 | /*␊ |
99 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
100 | */␊ |
101 | static uint64_t measure_tsc_frequency(void)␊ |
102 | {␊ |
103 | ␉uint64_t tscStart;␊ |
104 | ␉uint64_t tscEnd;␊ |
105 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
106 | ␉unsigned long pollCount;␊ |
107 | ␉uint64_t retval = 0;␊ |
108 | ␉int i;␊ |
109 | ␊ |
110 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
111 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
112 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
113 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
114 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
115 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
116 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
117 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
118 | ␉ */␊ |
119 | ␉for(i = 0; i < 10; ++i)␊ |
120 | ␉{␊ |
121 | ␉␉enable_PIT2();␊ |
122 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
123 | ␉␉tscStart = rdtsc64();␊ |
124 | ␉␉pollCount = poll_PIT2_gate();␊ |
125 | ␉␉tscEnd = rdtsc64();␊ |
126 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
127 | ␉␉if (pollCount <= 1)␊ |
128 | ␉␉{␊ |
129 | ␉␉␉continue;␊ |
130 | ␉␉}␊ |
131 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
132 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
133 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
134 | ␉␉ */␊ |
135 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
136 | ␉␉{␊ |
137 | ␉␉␉continue;␊ |
138 | ␉␉}␊ |
139 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
140 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
141 | ␉␉{␊ |
142 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
143 | ␉␉}␊ |
144 | ␉}␊ |
145 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
146 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
147 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
148 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
149 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
150 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
151 | ␉ */␊ |
152 | ␊ |
153 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
154 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
155 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
156 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
157 | ␉ */␊ |
158 | ␉if (tscDelta > (1ULL<<32))␊ |
159 | ␉{␊ |
160 | ␉␉retval = 0;␊ |
161 | ␉}␊ |
162 | ␉else␊ |
163 | ␉{␊ |
164 | ␉␉retval = tscDelta * 1000 / 30;␊ |
165 | ␉}␊ |
166 | ␉disable_PIT2();␊ |
167 | ␉return retval;␊ |
168 | }␊ |
169 | ␊ |
170 | /*␊ |
171 | * Original comment/code:␊ |
172 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
173 | *␊ |
174 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
175 | * (just a naming change, mperf --> aperf )␊ |
176 | */␊ |
177 | static uint64_t measure_aperf_frequency(void)␊ |
178 | {␊ |
179 | ␉uint64_t aperfStart;␊ |
180 | ␉uint64_t aperfEnd;␊ |
181 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
182 | ␉unsigned long pollCount;␊ |
183 | ␉uint64_t retval = 0;␊ |
184 | ␉int i;␊ |
185 | ␊ |
186 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
187 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
188 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
189 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
190 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
191 | ␉ * expire.␊ |
192 | ␉ */␊ |
193 | ␉for(i = 0; i < 10; ++i)␊ |
194 | ␉{␊ |
195 | ␉␉enable_PIT2();␊ |
196 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
197 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
198 | ␉␉pollCount = poll_PIT2_gate();␊ |
199 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
200 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
201 | ␉␉if (pollCount <= 1)␊ |
202 | ␉␉{␊ |
203 | ␉␉␉continue;␊ |
204 | ␉␉}␊ |
205 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
206 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
207 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
208 | ␉␉ */␊ |
209 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
210 | ␉␉{␊ |
211 | ␉␉␉continue;␊ |
212 | ␉␉}␊ |
213 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
214 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
215 | ␉␉{␊ |
216 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
217 | ␉␉}␊ |
218 | ␉}␊ |
219 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
220 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
221 | ␉ */␊ |
222 | ␊ |
223 | ␉if (aperfDelta > (1ULL<<32))␊ |
224 | ␉{␊ |
225 | ␉␉retval = 0;␊ |
226 | ␉}␊ |
227 | ␉else␊ |
228 | ␉{␊ |
229 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
230 | ␉}␊ |
231 | ␉disable_PIT2();␊ |
232 | ␉return retval;␊ |
233 | }␊ |
234 | ␊ |
235 | /*␊ |
236 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
237 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
238 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
239 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
240 | * - fsbFrequency = tscFrequency / multi␊ |
241 | * - cpuFrequency = fsbFrequency * multi␊ |
242 | */␊ |
243 | void scan_cpu(PlatformInfo_t *p)␊ |
244 | {␊ |
245 | ␉uint64_t␉tscFrequency␉␉= 0;␊ |
246 | ␉uint64_t␉fsbFrequency␉␉= 0;␊ |
247 | ␉uint64_t␉cpuFrequency␉␉= 0;␊ |
248 | ␉uint64_t␉msr␉␉␉= 0;␊ |
249 | ␉uint64_t␉flex_ratio␉␉= 0;␊ |
250 | ␊ |
251 | ␉uint32_t␉max_ratio␉␉= 0;␊ |
252 | ␉uint32_t␉min_ratio␉␉= 0;␊ |
253 | ␉uint32_t␉reg[4]; //␉␉= {0, 0, 0, 0};␊ |
254 | ␉uint32_t␉cores_per_package␉= 0;␊ |
255 | ␉uint32_t␉logical_per_package␉= 1;␊ |
256 | ␉uint32_t␉threads_per_core␉= 1;␊ |
257 | ␊ |
258 | ␉uint8_t␉␉bus_ratio_max␉␉= 0;␊ |
259 | ␉uint8_t␉␉bus_ratio_min␉␉= 0;␊ |
260 | ␉uint8_t␉␉currdiv␉␉␉= 0;␊ |
261 | ␉uint8_t␉␉currcoef␉␉= 0;␊ |
262 | ␉uint8_t␉␉maxdiv␉␉␉= 0;␊ |
263 | ␉uint8_t␉␉maxcoef␉␉␉= 0;␊ |
264 | ␊ |
265 | ␉const char␉*newratio;␊ |
266 | ␉char␉␉str[128];␊ |
267 | ␉char␉␉*s␉␉␉= 0;␊ |
268 | ␊ |
269 | ␉int␉␉len␉␉␉= 0;␊ |
270 | ␉int␉␉myfsb␉␉␉= 0;␊ |
271 | ␉int␉␉i␉␉␉= 0;␊ |
272 | ␊ |
273 | ␉/* get cpuid values */␊ |
274 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊ |
275 | ␉p->CPU.Vendor = p->CPU.CPUID[CPUID_0][ebx];␊ |
276 | ␊ |
277 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊ |
278 | ␊ |
279 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((bit(28) & p->CPU.CPUID[CPUID_1][edx]) != 0)) // Intel && HTT/Multicore␊ |
280 | ␉{␊ |
281 | ␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊ |
282 | ␉}␊ |
283 | ␊ |
284 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊ |
285 | ␊ |
286 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊ |
287 | ␊ |
288 | ␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊ |
289 | ␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊ |
290 | ␉{␊ |
291 | ␉␉for (i = 0; i < 0xFF; i++) // safe loop␊ |
292 | ␉␉{␊ |
293 | ␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊ |
294 | ␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊ |
295 | ␉␉␉{␊ |
296 | ␉␉␉␉break;␊ |
297 | ␉␉␉}␊ |
298 | ␉␉␉//cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊ |
299 | ␉␉}␊ |
300 | ␉}␊ |
301 | ␊ |
302 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
303 | ␊ |
304 | ␉if (i > 0)␊ |
305 | ␉{␊ |
306 | ␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊ |
307 | ␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊ |
308 | ␉}␊ |
309 | ␊ |
310 | ␉if (cores_per_package == 0)␊ |
311 | ␉{␊ |
312 | ␉␉cores_per_package = 1;␊ |
313 | ␉}␊ |
314 | ␊ |
315 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊ |
316 | ␉{␊ |
317 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
318 | ␉}␊ |
319 | ␊ |
320 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊ |
321 | ␉{␊ |
322 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
323 | ␉}␊ |
324 | ␊ |
325 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
326 | ␊ |
327 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
328 | ␉{␊ |
329 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
330 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
331 | ␉}␊ |
332 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
333 | ␉{␊ |
334 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
335 | ␉}␊ |
336 | ␊ |
337 | /* http://www.flounder.com/cpuid_explorer2.htm␊ |
338 | EAX (Intel):␊ |
339 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
340 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
341 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
342 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
343 | ␊ |
344 | EAX (AMD):␊ |
345 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
346 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
347 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
348 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
349 | */␊ |
350 | ␊ |
351 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
352 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
353 | ␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊ |
354 | ␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊ |
355 | ␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊ |
356 | ␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
357 | ␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
358 | ␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
359 | ␊ |
360 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
361 | ␊ |
362 | ␉/* get BrandString (if supported) */␊ |
363 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
364 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
365 | ␉{␊ |
366 | ␉␉bzero(str, 128);␊ |
367 | ␉␉/*␊ |
368 | ␉␉ * The BrandString 48 bytes (max), guaranteed to␊ |
369 | ␉␉ * be NULL terminated.␊ |
370 | ␉␉ */␊ |
371 | ␉␉do_cpuid(0x80000002, reg);␊ |
372 | ␉␉memcpy(&str[0], (char *)reg, 16);␊ |
373 | ␉␉do_cpuid(0x80000003, reg);␊ |
374 | ␉␉memcpy(&str[16], (char *)reg, 16);␊ |
375 | ␉␉do_cpuid(0x80000004, reg);␊ |
376 | ␉␉memcpy(&str[32], (char *)reg, 16);␊ |
377 | ␉␉for (s = str; *s != '\0'; s++)␊ |
378 | ␉␉{␊ |
379 | ␉␉␉if (*s != ' ')␊ |
380 | ␉␉␉{␊ |
381 | ␉␉␉␉break;␊ |
382 | ␉␉␉}␊ |
383 | ␉␉}␊ |
384 | ␉␉strlcpy(p->CPU.BrandString, s, 48);␊ |
385 | ␊ |
386 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
387 | ␉␉{␊ |
388 | ␉␉␉/*␊ |
389 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
390 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
391 | ␉␉␉ */␊ |
392 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
393 | ␉␉}␊ |
394 | ␉␉p->CPU.BrandString[47] = '\0';␊ |
395 | //␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊ |
396 | ␉}␊ |
397 | ␊ |
398 | ␉/*␊ |
399 | ␉ * Find the number of enabled cores and threads␊ |
400 | ␉ * (which determines whether SMT/Hyperthreading is active).␊ |
401 | ␉ */␊ |
402 | ␉switch (p->CPU.Vendor)␊ |
403 | ␉{␊ |
404 | ␉␉case CPUID_VENDOR_INTEL:␊ |
405 | ␉␉␉switch (p->CPU.Model)␊ |
406 | ␉␉␉{␊ |
407 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
408 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
409 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
410 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
411 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
412 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
413 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
414 | ␊ |
415 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
416 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
417 | ␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊ |
418 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
419 | ␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
420 | ␉␉␉␉//case CPUID_MODEL_:␊ |
421 | ␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
422 | ␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊ |
423 | ␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
424 | ␉␉␉␉␉break;␊ |
425 | ␊ |
426 | ␉␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
427 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
428 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
429 | ␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
430 | ␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊ |
431 | ␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
432 | ␉␉␉␉␉break;␊ |
433 | ␉␉␉}␊ |
434 | ␊ |
435 | ␉␉␉if (p->CPU.NoCores == 0)␊ |
436 | ␉␉␉{␊ |
437 | ␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊ |
438 | ␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊ |
439 | ␉␉␉}␊ |
440 | ␉␉␉break;␊ |
441 | ␊ |
442 | ␉␉case CPUID_VENDOR_AMD:␊ |
443 | ␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
444 | ␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
445 | ␉␉␉if (p->CPU.NoCores == 0)␊ |
446 | ␉␉␉{␊ |
447 | ␉␉␉␉p->CPU.NoCores = 1;␊ |
448 | ␉␉␉}␊ |
449 | ␊ |
450 | ␉␉␉if (p->CPU.NoThreads < p->CPU.NoCores)␊ |
451 | ␉␉␉{␊ |
452 | ␉␉␉␉p->CPU.NoThreads = p->CPU.NoCores;␊ |
453 | ␉␉␉}␊ |
454 | ␊ |
455 | ␉␉␉break;␊ |
456 | ␊ |
457 | ␉␉default:␊ |
458 | ␉␉␉stop("Unsupported CPU detected! System halted.");␊ |
459 | ␉}␊ |
460 | ␊ |
461 | ␉//workaround for N270. I don't know why it detected wrong␊ |
462 | ␉// MSR is *NOT* available on the Intel Atom CPU␊ |
463 | ␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊ |
464 | ␉{␊ |
465 | ␉␉p->CPU.NoCores␉␉= 1;␊ |
466 | ␉␉p->CPU.NoThreads␉= 2;␊ |
467 | ␉}␊ |
468 | ␊ |
469 | ␉/* setup features */␊ |
470 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
471 | ␉{␊ |
472 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
473 | ␉}␊ |
474 | ␊ |
475 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
476 | ␉{␊ |
477 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
478 | ␉}␊ |
479 | ␊ |
480 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
481 | ␉{␊ |
482 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
483 | ␉}␊ |
484 | ␊ |
485 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
486 | ␉{␊ |
487 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
488 | ␉}␊ |
489 | ␊ |
490 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
491 | ␉{␊ |
492 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
493 | ␉}␊ |
494 | ␊ |
495 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
496 | ␉{␊ |
497 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
498 | ␉}␊ |
499 | ␊ |
500 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
501 | ␉{␊ |
502 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
503 | ␉}␊ |
504 | ␊ |
505 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
506 | ␉{␊ |
507 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
508 | ␉}␊ |
509 | ␊ |
510 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && (p->CPU.NoThreads > p->CPU.NoCores))␊ |
511 | ␉{␊ |
512 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
513 | ␉}␊ |
514 | ␊ |
515 | ␉tscFrequency = measure_tsc_frequency();␊ |
516 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
517 | ␉// if usual method failed␊ |
518 | ␉if ( tscFrequency < 1000 )␉//TEST␊ |
519 | ␉{␊ |
520 | ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
521 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
522 | ␉}␊ |
523 | ␉else␊ |
524 | ␉{␊ |
525 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
526 | ␉}␊ |
527 | ␊ |
528 | ␉fsbFrequency = 0;␊ |
529 | ␉cpuFrequency = 0;␊ |
530 | ␊ |
531 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊ |
532 | ␉{␊ |
533 | ␉␉int intelCPU = p->CPU.Model;␊ |
534 | ␉␉if (p->CPU.Family == 0x06)␊ |
535 | ␉␉{␊ |
536 | ␉␉␉/* Nehalem CPU model */␊ |
537 | ␉␉␉switch (p->CPU.Model)␊ |
538 | ␉␉␉{␊ |
539 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
540 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
541 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
542 | ␉␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
543 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
544 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
545 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
546 | /* --------------------------------------------------------- */␊ |
547 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
548 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
549 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
550 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
551 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
552 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
553 | ␊ |
554 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
555 | ␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
556 | /* --------------------------------------------------------- */␊ |
557 | ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
558 | ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
559 | ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
560 | ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
561 | ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
562 | ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
563 | ␉␉␉␉␉if (bitfield(msr, 16, 16))␊ |
564 | ␉␉␉␉␉{␊ |
565 | ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
566 | ␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊ |
567 | ␉␉␉␉␉␉// where the cpu multipler can't be changed to␊ |
568 | ␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
569 | ␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊ |
570 | ␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊ |
571 | ␉␉␉␉␉␉// causing the system to crash since tscGranularity␊ |
572 | ␉␉␉␉␉␉// is inadvertently set to 0.␊ |
573 | ␊ |
574 | ␉␉␉␉␉␉if (flex_ratio == 0)␊ |
575 | ␉␉␉␉␉␉{␊ |
576 | ␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊ |
577 | ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
578 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
579 | ␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
580 | ␉␉␉␉␉␉}␊ |
581 | ␉␉␉␉␉␉else␊ |
582 | ␉␉␉␉␉␉{␊ |
583 | ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
584 | ␉␉␉␉␉␉␉{␊ |
585 | ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
586 | ␉␉␉␉␉␉␉}␊ |
587 | ␉␉␉␉␉␉}␊ |
588 | ␉␉␉␉␉}␊ |
589 | ␊ |
590 | ␉␉␉␉␉if (bus_ratio_max)␊ |
591 | ␉␉␉␉␉{␊ |
592 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
593 | ␉␉␉␉␉}␊ |
594 | ␊ |
595 | ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
596 | ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
597 | ␉␉␉␉␉{␊ |
598 | ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
599 | ␊ |
600 | ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
601 | ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
602 | ␉␉␉␉␉}␊ |
603 | ␉␉␉␉␉else␊ |
604 | ␉␉␉␉␉{␊ |
605 | ␉␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
606 | ␉␉␉␉␉}␊ |
607 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
608 | ␉␉␉␉␉{␊ |
609 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
610 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
611 | ␉␉␉␉␉␉if (len >= 3)␊ |
612 | ␉␉␉␉␉␉{␊ |
613 | ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
614 | ␉␉␉␉␉␉}␊ |
615 | ␊ |
616 | ␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
617 | ␊ |
618 | ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
619 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
620 | ␉␉␉␉␉␉{␊ |
621 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
622 | ␉␉␉␉␉␉␉if (len >= 3)␊ |
623 | ␉␉␉␉␉␉␉{␊ |
624 | ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
625 | ␉␉␉␉␉␉␉}␊ |
626 | ␉␉␉␉␉␉␉else␊ |
627 | ␉␉␉␉␉␉␉{␊ |
628 | ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
629 | ␉␉␉␉␉␉␉}␊ |
630 | ␉␉␉␉␉␉}␊ |
631 | ␉␉␉␉␉␉else␊ |
632 | ␉␉␉␉␉␉{␊ |
633 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
634 | ␉␉␉␉␉␉}␊ |
635 | ␉␉␉␉␉}␊ |
636 | ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
637 | ␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊ |
638 | ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
639 | ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
640 | ␊ |
641 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
642 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
643 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
644 | ␊ |
645 | ␉␉␉␉break;␊ |
646 | ␊ |
647 | ␉␉␉default:␊ |
648 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
649 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
650 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
651 | ␉␉␉␉// Non-integer bus ratio for the max-multi␊ |
652 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
653 | ␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊ |
654 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
655 | ␊ |
656 | ␉␉␉␉// This will always be model >= 3␊ |
657 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
658 | ␉␉␉␉{␊ |
659 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
660 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
661 | ␉␉␉␉}␊ |
662 | ␉␉␉␉else␊ |
663 | ␉␉␉␉{␊ |
664 | ␉␉␉␉␉// On lower models, currcoef defines TSC freq␊ |
665 | ␉␉␉␉␉// XXX␊ |
666 | ␉␉␉␉␉maxcoef = currcoef;␊ |
667 | ␉␉␉␉}␊ |
668 | ␊ |
669 | ␉␉␉␉if (!currcoef)␊ |
670 | ␉␉␉␉{␊ |
671 | ␉␉␉␉␉currcoef = maxcoef;␊ |
672 | ␉␉␉␉}␊ |
673 | ␊ |
674 | ␉␉␉␉if (maxcoef)␊ |
675 | ␉␉␉␉{␊ |
676 | ␉␉␉␉␉if (maxdiv)␊ |
677 | ␉␉␉␉␉{␊ |
678 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
679 | ␉␉␉␉␉}␊ |
680 | ␉␉␉␉␉else␊ |
681 | ␉␉␉␉␉{␊ |
682 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
683 | ␉␉␉␉␉}␊ |
684 | ␊ |
685 | ␉␉␉␉␉if (currdiv)␊ |
686 | ␉␉␉␉␉{␊ |
687 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
688 | ␉␉␉␉␉}␊ |
689 | ␉␉␉␉␉else␊ |
690 | ␉␉␉␉␉{␊ |
691 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
692 | ␉␉␉␉␉}␊ |
693 | ␊ |
694 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
695 | ␉␉␉␉}␊ |
696 | ␉␉␉␉break;␊ |
697 | ␉␉␉}␊ |
698 | ␉␉}␊ |
699 | ␉␉// Mobile CPU␊ |
700 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
701 | ␉␉{␊ |
702 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
703 | ␉␉}␊ |
704 | ␉}␊ |
705 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
706 | ␉{␊ |
707 | ␉␉switch(p->CPU.ExtFamily)␊ |
708 | ␉␉{␊ |
709 | ␉␉␉case 0x00: //* K8 *//␊ |
710 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
711 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
712 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
713 | ␉␉␉␉break;␊ |
714 | ␊ |
715 | ␉␉␉case 0x01: //* K10 *//␊ |
716 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
717 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
718 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
719 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
720 | ␉␉␉␉{␊ |
721 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
722 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
723 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
724 | ␉␉␉␉}␊ |
725 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
726 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
727 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
728 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
729 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
730 | ␊ |
731 | ␉␉␉␉break;␊ |
732 | ␊ |
733 | ␉␉␉case 0x05: //* K14 *//␊ |
734 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
735 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
736 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
737 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
738 | ␊ |
739 | ␉␉␉␉break;␊ |
740 | ␊ |
741 | ␉␉␉case 0x02: //* K11 *//␊ |
742 | ␉␉␉␉// not implimented␊ |
743 | ␉␉␉␉break;␊ |
744 | ␉␉}␊ |
745 | ␊ |
746 | ␉␉if (maxcoef)␊ |
747 | ␉␉{␊ |
748 | ␉␉␉if (currdiv)␊ |
749 | ␉␉␉{␊ |
750 | ␉␉␉␉if (!currcoef)␊ |
751 | ␉␉␉␉{␊ |
752 | ␉␉␉␉␉currcoef = maxcoef;␊ |
753 | ␉␉␉␉}␊ |
754 | ␊ |
755 | ␉␉␉␉if (!cpuFrequency)␊ |
756 | ␉␉␉␉{␊ |
757 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
758 | ␉␉␉␉}␊ |
759 | ␉␉␉␉else␊ |
760 | ␉␉␉␉{␊ |
761 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
762 | ␉␉␉␉}␊ |
763 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
764 | ␉␉␉}␊ |
765 | ␉␉␉else␊ |
766 | ␉␉␉{␊ |
767 | ␉␉␉␉if (!cpuFrequency)␊ |
768 | ␉␉␉␉{␊ |
769 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
770 | ␉␉␉␉}␊ |
771 | ␉␉␉␉else␊ |
772 | ␉␉␉␉{␊ |
773 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
774 | ␉␉␉␉}␊ |
775 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
776 | ␉␉␉}␊ |
777 | ␉␉}␊ |
778 | ␉␉else if (currcoef)␊ |
779 | ␉␉{␊ |
780 | ␉␉␉if (currdiv)␊ |
781 | ␉␉␉{␊ |
782 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
783 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
784 | ␉␉␉}␊ |
785 | ␉␉␉else␊ |
786 | ␉␉␉{␊ |
787 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
788 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
789 | ␉␉␉}␊ |
790 | ␉␉}␊ |
791 | ␉␉if (!cpuFrequency)␊ |
792 | ␉␉{␊ |
793 | ␉␉␉cpuFrequency = tscFrequency;␊ |
794 | ␉␉}␊ |
795 | ␉}␊ |
796 | ␊ |
797 | #if 0␊ |
798 | ␉if (!fsbFrequency)␊ |
799 | ␉{␊ |
800 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
801 | ␉␉DBG("CPU: fsbFrequency = 0! using the default value for FSB!\n");␊ |
802 | ␉␉cpuFrequency = tscFrequency;␊ |
803 | ␉}␊ |
804 | ␊ |
805 | ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
806 | ␊ |
807 | #endif␊ |
808 | ␊ |
809 | ␉p->CPU.MaxCoef = maxcoef;␊ |
810 | ␉p->CPU.MaxDiv = maxdiv;␊ |
811 | ␉p->CPU.CurrCoef = currcoef;␊ |
812 | ␉p->CPU.CurrDiv = currdiv;␊ |
813 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
814 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
815 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
816 | ␊ |
817 | ␉// keep formatted with spaces instead of tabs␊ |
818 | ␉DBG("\n------------------------------\n");␊ |
819 | ␉DBG("\tCPU INFO\n");␊ |
820 | ␉DBG("------------------------------\n");␊ |
821 | ␊ |
822 | ␉DBG("CPUID Raw Values:\n");␊ |
823 | ␉for (i = 0; i < CPUID_MAX; i++)␊ |
824 | ␉{␊ |
825 | ␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊ |
826 | ␉}␊ |
827 | ␉DBG("\n");␊ |
828 | ␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊ |
829 | ␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊ |
830 | ␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊ |
831 | ␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊ |
832 | ␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊ |
833 | ␉/*switch (p->CPU.Type) {␊ |
834 | ␉␉case PT_OEM:␊ |
835 | ␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊ |
836 | ␉␉␉break;␊ |
837 | ␉␉case PT_OD:␊ |
838 | ␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊ |
839 | ␉␉␉break;␊ |
840 | ␉␉case PT_DUAL:␊ |
841 | ␉␉␉DBG("Processor type: Intel Dual Processor\n");␊ |
842 | ␉␉␉break;␊ |
843 | ␉␉case PT_RES:␊ |
844 | ␉␉␉DBG("Processor type: Intel Reserved\n");␊ |
845 | ␉␉␉break;␊ |
846 | ␉␉default:␊ |
847 | ␉␉␉break;␊ |
848 | ␉}*/␊ |
849 | ␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊ |
850 | ␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊ |
851 | ␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊ |
852 | ␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊ |
853 | ␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊ |
854 | ␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊ |
855 | ␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊ |
856 | ␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊ |
857 | ␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊ |
858 | ␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊ |
859 | ␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊ |
860 | ␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊ |
861 | ␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊ |
862 | ␊ |
863 | ␉DBG("\n---------------------------------------------\n");␊ |
864 | #if DEBUG_CPU␊ |
865 | ␉pause();␊ |
866 | #endif␊ |
867 | }␊ |
868 | |