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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28static uint64_t timeRDTSC(void)␊
29{␊
30␉int␉␉attempts = 0;␊
31␉uint64_t ␉latchTime;␊
32␉uint64_t␉saveTime,intermediate;␊
33␉unsigned int␉timerValue, lastValue;␊
34␉//boolean_t␉int_enabled;␊
35␉/*␊
36␉ * Table of correction factors to account for␊
37␉ *␉ - timer counter quantization errors, and␊
38␉ *␉ - undercounts 0..5␊
39␉ */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45␉uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52␉};␊
53␊
54␉//int_enabled = ml_set_interrupts_enabled(false);␊
55␊
56restart:␊
57␉if (attempts >= 9) // increase to up to 9 attempts.␊
58␉{␊
59␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
60␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
61␉}␊
62␉attempts++;␊
63␉enable_PIT2();␉␉// turn on PIT2␊
64␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
65␉latchTime = rdtsc64();␉// get the time stamp to time␊
66␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
67␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
68␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
69␉get_PIT2(&lastValue);␊
70␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
71␉do {␊
72␉␉intermediate = get_PIT2(&timerValue);␊
73␉␉if (timerValue > lastValue)␊
74␉␉{␊
75␉␉␉// Timer wrapped␊
76␉␉␉set_PIT2(0);␊
77␉␉␉disable_PIT2();␊
78␉␉␉goto restart;␊
79␉␉}␊
80␉␉lastValue = timerValue;␊
81␉} while (timerValue > 5);␊
82␉printf("timerValue␉ %d\n",timerValue);␊
83␉printf("intermediate 0x%016llX\n",intermediate);␊
84␉printf("saveTime␉ 0x%016llX\n",saveTime);␊
85 ␊
86␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
87␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
88␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
89␉intermediate += latchTime;␉␉// add on our save fudge␊
90␊
91␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
92␉disable_PIT2();␉␉␉// turn off PIT 2␊
93␊
94␉//ml_set_interrupts_enabled(int_enabled);␊
95␉return intermediate;␊
96}␊
97␊
98/*␊
99 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
100 */␊
101static uint64_t measure_tsc_frequency(void)␊
102{␊
103␉uint64_t tscStart;␊
104␉uint64_t tscEnd;␊
105␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
106␉unsigned long pollCount;␊
107␉uint64_t retval = 0;␊
108␉int i;␊
109␊
110␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
111␉ * counter 2. We run this loop 3 times to make sure the cache␊
112␉ * is hot and we take the minimum delta from all of the runs.␊
113␉ * That is to say that we're biased towards measuring the minimum␊
114␉ * number of TSC ticks that occur while waiting for the timer to␊
115␉ * expire. That theoretically helps avoid inconsistencies when␊
116␉ * running under a VM if the TSC is not virtualized and the host␊
117␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
118␉ */␊
119␉for(i = 0; i < 10; ++i)␊
120␉{␊
121␉␉enable_PIT2();␊
122␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
123␉␉tscStart = rdtsc64();␊
124␉␉pollCount = poll_PIT2_gate();␊
125␉␉tscEnd = rdtsc64();␊
126␉␉/* The poll loop must have run at least a few times for accuracy */␊
127␉␉if (pollCount <= 1)␊
128␉␉{␊
129␉␉␉continue;␊
130␉␉}␊
131␉␉/* The TSC must increment at LEAST once every millisecond.␊
132␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
133␉␉ * be >= 30. Anything less and the processor is way too slow.␊
134␉␉ */␊
135␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
136␉␉{␊
137␉␉␉continue;␊
138␉␉}␊
139␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
140␉␉if ( (tscEnd - tscStart) < tscDelta )␊
141␉␉{␊
142␉␉␉tscDelta = tscEnd - tscStart;␊
143␉␉}␊
144␉}␊
145␉/* tscDelta is now the least number of TSC ticks the processor made in␊
146␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
147␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
148␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
149␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
150␉ * dividing by the milliseconds, we simply multiply by 1000.␊
151␉ */␊
152␊
153␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
154␉ * that we're going to multiply by 1000 first so we do need at least some␊
155␉ * arithmetic headroom. For now, 32-bit should be enough.␊
156␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
157␉ */␊
158␉if (tscDelta > (1ULL<<32))␊
159␉{␊
160␉␉retval = 0;␊
161␉}␊
162␉else␊
163␉{␊
164␉␉retval = tscDelta * 1000 / 30;␊
165␉}␊
166␉disable_PIT2();␊
167␉return retval;␊
168}␊
169␊
170/*␊
171 * Original comment/code:␊
172 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
173 *␊
174 * Measures the Actual Performance Frequency in Hz (64-bit)␊
175 * (just a naming change, mperf --> aperf )␊
176 */␊
177static uint64_t measure_aperf_frequency(void)␊
178{␊
179␉uint64_t aperfStart;␊
180␉uint64_t aperfEnd;␊
181␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
182␉unsigned long pollCount;␊
183␉uint64_t retval = 0;␊
184␉int i;␊
185␊
186␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
187␉ * counter 2. We run this loop 3 times to make sure the cache␊
188␉ * is hot and we take the minimum delta from all of the runs.␊
189␉ * That is to say that we're biased towards measuring the minimum␊
190␉ * number of APERF ticks that occur while waiting for the timer to␊
191␉ * expire.␊
192␉ */␊
193␉for(i = 0; i < 10; ++i)␊
194␉{␊
195␉␉enable_PIT2();␊
196␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
197␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
198␉␉pollCount = poll_PIT2_gate();␊
199␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
200␉␉/* The poll loop must have run at least a few times for accuracy */␊
201␉␉if (pollCount <= 1)␊
202␉␉{␊
203␉␉␉continue;␊
204␉␉}␊
205␉␉/* The TSC must increment at LEAST once every millisecond.␊
206␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
207␉␉ * be >= 30. Anything less and the processor is way too slow.␊
208␉␉ */␊
209␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
210␉␉{␊
211␉␉␉continue;␊
212␉␉}␊
213␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
214␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
215␉␉{␊
216␉␉␉aperfDelta = aperfEnd - aperfStart;␊
217␉␉}␊
218␉}␊
219␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
220␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
221␉ */␊
222␊
223␉if (aperfDelta > (1ULL<<32))␊
224␉{␊
225␉␉retval = 0;␊
226␉}␊
227␉else␊
228␉{␊
229␉␉retval = aperfDelta * 1000 / 30;␊
230␉}␊
231␉disable_PIT2();␊
232␉return retval;␊
233}␊
234␊
235/*␊
236 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
237 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
238 *␉ a max multi. (used to calculate the FSB freq.),␊
239 *␉ and a current multi. (used to calculate the CPU freq.)␊
240 * - fsbFrequency = tscFrequency / multi␊
241 * - cpuFrequency = fsbFrequency * multi␊
242 */␊
243void scan_cpu(PlatformInfo_t *p)␊
244{␊
245␉uint64_t␉tscFrequency␉␉= 0;␊
246␉uint64_t␉fsbFrequency␉␉= 0;␊
247␉uint64_t␉cpuFrequency␉␉= 0;␊
248␉uint64_t␉msr␉␉␉= 0;␊
249␉uint64_t␉flex_ratio␉␉= 0;␊
250␊
251␉uint32_t␉max_ratio␉␉= 0;␊
252␉uint32_t␉min_ratio␉␉= 0;␊
253␉uint32_t␉reg[4]; //␉␉= {0, 0, 0, 0};␊
254␉uint32_t␉cores_per_package␉= 0;␊
255␉uint32_t␉logical_per_package␉= 1;␊
256␉uint32_t␉threads_per_core␉= 1;␊
257␊
258␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
259␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
260␉uint8_t␉␉currdiv␉␉␉= 0;␊
261␉uint8_t␉␉currcoef␉␉= 0;␊
262␉uint8_t␉␉maxdiv␉␉␉= 0;␊
263␉uint8_t␉␉maxcoef␉␉␉= 0;␊
264␉uint8_t␉␉pic0_mask;␊
265␊
266␉const char␉*newratio;␊
267␉char␉␉str[128];␊
268␉char␉␉*s␉␉␉= 0;␊
269␊
270␉int␉␉len␉␉␉= 0;␊
271␉int␉␉myfsb␉␉␉= 0;␊
272␉int␉␉i␉␉␉= 0;␊
273␊
274␉/* get cpuid values */␊
275␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
276␉p->CPU.Vendor = p->CPU.CPUID[CPUID_0][ebx];␊
277␊
278␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
279␊
280␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((bit(28) & p->CPU.CPUID[CPUID_1][edx]) != 0)) // Intel && HTT/Multicore␊
281␉{␊
282␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
283␉}␊
284␊
285␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
286␊
287␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
288␊
289␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
290␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
291␉{␊
292␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
293␉␉{␊
294␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
295␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
296␉␉␉{␊
297␉␉␉␉break;␊
298␉␉␉}␊
299␉␉␉//cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
300␉␉}␊
301␉}␊
302␊
303␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
304␊
305␉if (i > 0)␊
306␉{␊
307␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
308␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
309␉}␊
310␊
311␉if (cores_per_package == 0)␊
312␉{␊
313␉␉cores_per_package = 1;␊
314␉}␊
315␊
316␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
317␉{␊
318␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
319␉}␊
320␊
321␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
322␉{␊
323␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
324␉}␊
325␊
326␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
327␊
328␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
329␉{␊
330␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
331␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
332␉}␊
333␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
334␉{␊
335␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
336␉}␊
337␊
338/* http://www.flounder.com/cpuid_explorer2.htm␊
339 EAX (Intel):␊
340 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
341 +--------+----------------+--------+----+----+--------+--------+--------+␊
342 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
343 +--------+----------------+--------+----+----+--------+--------+--------+␊
344␊
345 EAX (AMD):␊
346 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
347 +--------+----------------+--------+----+----+--------+--------+--------+␊
348 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
349 +--------+----------------+--------+----+----+--------+--------+--------+␊
350*/␊
351␊
352␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
353␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
354␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
355␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
356␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
357␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
358␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
359␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
360␊
361␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
362␊
363␉/* get BrandString (if supported) */␊
364␉/* Copyright: from Apple's XNU cpuid.c */␊
365␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
366␉{␊
367␉␉bzero(str, 128);␊
368␉␉/*␊
369␉␉ * The BrandString 48 bytes (max), guaranteed to␊
370␉␉ * be NULL terminated.␊
371␉␉ */␊
372␉␉do_cpuid(0x80000002, reg);␊
373␉␉memcpy(&str[0], (char *)reg, 16);␊
374␉␉do_cpuid(0x80000003, reg);␊
375␉␉memcpy(&str[16], (char *)reg, 16);␊
376␉␉do_cpuid(0x80000004, reg);␊
377␉␉memcpy(&str[32], (char *)reg, 16);␊
378␉␉for (s = str; *s != '\0'; s++)␊
379␉␉{␊
380␉␉␉if (*s != ' ')␊
381␉␉␉{␊
382␉␉␉␉break;␊
383␉␉␉}␊
384␉␉}␊
385␉␉strlcpy(p->CPU.BrandString, s, 48);␊
386␊
387␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
388␉␉{␊
389␉␉␉/*␊
390␉␉␉ * This string means we have a firmware-programmable brand string,␊
391␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
392␉␉␉ */␊
393␉␉␉p->CPU.BrandString[0] = '\0';␊
394␉␉}␊
395␉␉p->CPU.BrandString[47] = '\0';␊
396//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
397␉}␊
398␊
399␉/*␊
400␉ * Find the number of enabled cores and threads␊
401␉ * (which determines whether SMT/Hyperthreading is active).␊
402␉ */␊
403␉switch (p->CPU.Vendor)␊
404␉{␊
405␉␉case CPUID_VENDOR_INTEL:␊
406␉␉␉switch (p->CPU.Model)␊
407␉␉␉{␊
408␉␉␉␉case CPUID_MODEL_NEHALEM:␊
409␉␉␉␉case CPUID_MODEL_FIELDS:␊
410␉␉␉␉case CPUID_MODEL_DALES:␊
411␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
412␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
413␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
414␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
415␊
416␉␉␉␉case CPUID_MODEL_HASWELL:␊
417␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
418␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊
419␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
420␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
421␉␉␉␉//case CPUID_MODEL_:␊
422␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
423␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
424␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
425␉␉␉␉␉break;␊
426␊
427␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
428␉␉␉␉case CPUID_MODEL_WESTMERE:␊
429␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
430␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
431␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
432␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
433␉␉␉␉␉break;␊
434␉␉␉}␊
435␊
436␉␉␉if (p->CPU.NoCores == 0)␊
437␉␉␉{␊
438␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
439␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
440␉␉␉}␊
441␉␉␉break;␊
442␊
443␉␉case CPUID_VENDOR_AMD:␊
444␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
445␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
446␉␉␉if (p->CPU.NoCores == 0)␊
447␉␉␉{␊
448␉␉␉␉p->CPU.NoCores = 1;␊
449␉␉␉}␊
450␊
451␉␉␉if (p->CPU.NoThreads < p->CPU.NoCores)␊
452␉␉␉{␊
453␉␉␉␉p->CPU.NoThreads = p->CPU.NoCores;␊
454␉␉␉}␊
455␊
456␉␉␉break;␊
457␊
458␉␉default:␊
459␉␉␉stop("Unsupported CPU detected! System halted.");␊
460␉}␊
461␊
462␉//workaround for N270. I don't know why it detected wrong␊
463␉// MSR is *NOT* available on the Intel Atom CPU␊
464␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
465␉{␊
466␉␉p->CPU.NoCores␉␉= 1;␊
467␉␉p->CPU.NoThreads␉= 2;␊
468␉}␊
469␊
470␉/* setup features */␊
471␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
472␉{␊
473␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
474␉}␊
475␊
476␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
477␉{␊
478␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
479␉}␊
480␊
481␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
482␉{␊
483␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
484␉}␊
485␊
486␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
487␉{␊
488␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
489␉}␊
490␊
491␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
492␉{␊
493␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
494␉}␊
495␊
496␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
497␉{␊
498␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
499␉}␊
500␊
501␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
502␉{␊
503␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
504␉}␊
505␊
506␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
507␉{␊
508␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
509␉}␊
510␊
511␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && (p->CPU.NoThreads > p->CPU.NoCores))␊
512␉{␊
513␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
514␉}␊
515␊
516␉pic0_mask = inb(0x21U);␊
517␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
518␊
519␉tscFrequency = measure_tsc_frequency();␊
520␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊
521␉// if usual method failed␊
522␉if ( tscFrequency < 1000 )␉//TEST␊
523␉{␊
524␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊
525␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
526␉}␊
527␉else␊
528␉{␊
529␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊
530␉}␊
531␊
532␉fsbFrequency = 0;␊
533␉cpuFrequency = 0;␊
534␊
535␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
536␉{␊
537␉␉int intelCPU = p->CPU.Model;␊
538␉␉if (p->CPU.Family == 0x06)␊
539␉␉{␊
540␉␉␉/* Nehalem CPU model */␊
541␉␉␉switch (p->CPU.Model)␊
542␉␉␉{␊
543␉␉␉␉case CPUID_MODEL_NEHALEM:␊
544␉␉␉␉case CPUID_MODEL_FIELDS:␊
545␉␉␉␉case CPUID_MODEL_DALES:␊
546␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
547␉␉␉␉case CPUID_MODEL_WESTMERE:␊
548␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
549␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
550/* --------------------------------------------------------- */␊
551␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
552␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
553␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
554␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
555␉␉␉␉case CPUID_MODEL_HASWELL:␊
556␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
557␊
558␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
559␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
560/* --------------------------------------------------------- */␊
561␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
562␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
563␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
564␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
565␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
566␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
567␉␉␉␉␉if (bitfield(msr, 16, 16))␊
568␉␉␉␉␉{␊
569␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
570␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
571␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
572␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
573␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
574␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
575␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
576␉␉␉␉␉␉// is inadvertently set to 0.␊
577␊
578␉␉␉␉␉␉if (flex_ratio == 0)␊
579␉␉␉␉␉␉{␊
580␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
581␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
582␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
583␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
584␉␉␉␉␉␉}␊
585␉␉␉␉␉␉else␊
586␉␉␉␉␉␉{␊
587␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
588␉␉␉␉␉␉␉{␊
589␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
590␉␉␉␉␉␉␉}␊
591␉␉␉␉␉␉}␊
592␉␉␉␉␉}␊
593␊
594␉␉␉␉␉if (bus_ratio_max)␊
595␉␉␉␉␉{␊
596␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
597␉␉␉␉␉}␊
598␊
599␉␉␉␉␉//valv: Turbo Ratio Limit␊
600␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
601␉␉␉␉␉{␊
602␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
603␊
604␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
605␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
606␉␉␉␉␉}␊
607␉␉␉␉␉else␊
608␉␉␉␉␉{␊
609␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
610␉␉␉␉␉}␊
611␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
612␉␉␉␉␉{␊
613␉␉␉␉␉␉max_ratio = atoi(newratio);␊
614␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
615␉␉␉␉␉␉if (len >= 3)␊
616␉␉␉␉␉␉{␊
617␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
618␉␉␉␉␉␉}␊
619␊
620␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
621␊
622␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
623␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
624␉␉␉␉␉␉{␊
625␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
626␉␉␉␉␉␉␉if (len >= 3)␊
627␉␉␉␉␉␉␉{␊
628␉␉␉␉␉␉␉␉maxdiv = 1;␊
629␉␉␉␉␉␉␉}␊
630␉␉␉␉␉␉␉else␊
631␉␉␉␉␉␉␉{␊
632␉␉␉␉␉␉␉␉maxdiv = 0;␊
633␉␉␉␉␉␉␉}␊
634␉␉␉␉␉␉}␊
635␉␉␉␉␉␉else␊
636␉␉␉␉␉␉{␊
637␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
638␉␉␉␉␉␉}␊
639␉␉␉␉␉}␊
640␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
641␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
642␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
643␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
644␊
645␉␉␉␉myfsb = fsbFrequency / 1000000;␊
646␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
647␉␉␉␉currcoef = bus_ratio_max;␊
648␊
649␉␉␉␉break;␊
650␊
651␉␉␉default:␊
652␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
653␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
654␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
655␉␉␉␉// Non-integer bus ratio for the max-multi␊
656␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
657␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
658␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
659␊
660␉␉␉␉// This will always be model >= 3␊
661␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
662␉␉␉␉{␊
663␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
664␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
665␉␉␉␉}␊
666␉␉␉␉else␊
667␉␉␉␉{␊
668␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
669␉␉␉␉␉// XXX␊
670␉␉␉␉␉maxcoef = currcoef;␊
671␉␉␉␉}␊
672␊
673␉␉␉␉if (!currcoef)␊
674␉␉␉␉{␊
675␉␉␉␉␉currcoef = maxcoef;␊
676␉␉␉␉}␊
677␊
678␉␉␉␉if (maxcoef)␊
679␉␉␉␉{␊
680␉␉␉␉␉if (maxdiv)␊
681␉␉␉␉␉{␊
682␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
683␉␉␉␉␉}␊
684␉␉␉␉␉else␊
685␉␉␉␉␉{␊
686␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
687␉␉␉␉␉}␊
688␊
689␉␉␉␉␉if (currdiv)␊
690␉␉␉␉␉{␊
691␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
692␉␉␉␉␉}␊
693␉␉␉␉␉else␊
694␉␉␉␉␉{␊
695␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
696␉␉␉␉␉}␊
697␊
698␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
699␉␉␉␉}␊
700␉␉␉␉break;␊
701␉␉␉}␊
702␉␉}␊
703␉␉// Mobile CPU␊
704␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
705␉␉{␊
706␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
707␉␉}␊
708␉}␊
709␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
710␉{␊
711␉␉switch(p->CPU.ExtFamily)␊
712␉␉{␊
713␉␉␉case 0x00: //* K8 *//␊
714␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
715␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
716␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
717␉␉␉␉break;␊
718␊
719␉␉␉case 0x01: //* K10 *//␊
720␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
721␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
722␉␉␉␉// EffFreq: effective frequency interface␊
723␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
724␉␉␉␉{␊
725␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
726␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
727␉␉␉␉␉cpuFrequency = aperf;␊
728␉␉␉␉}␊
729␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
730␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
731␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
732␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
733␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
734␊
735␉␉␉␉break;␊
736␊
737␉␉␉case 0x05: //* K14 *//␊
738␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
739␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
740␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
741␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
742␊
743␉␉␉␉break;␊
744␊
745␉␉␉case 0x02: //* K11 *//␊
746␉␉␉␉// not implimented␊
747␉␉␉␉break;␊
748␉␉}␊
749␊
750␉␉if (maxcoef)␊
751␉␉{␊
752␉␉␉if (currdiv)␊
753␉␉␉{␊
754␉␉␉␉if (!currcoef)␊
755␉␉␉␉{␊
756␉␉␉␉␉currcoef = maxcoef;␊
757␉␉␉␉}␊
758␊
759␉␉␉␉if (!cpuFrequency)␊
760␉␉␉␉{␊
761␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
762␉␉␉␉}␊
763␉␉␉␉else␊
764␉␉␉␉{␊
765␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
766␉␉␉␉}␊
767␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
768␉␉␉}␊
769␉␉␉else␊
770␉␉␉{␊
771␉␉␉␉if (!cpuFrequency)␊
772␉␉␉␉{␊
773␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
774␉␉␉␉}␊
775␉␉␉␉else␊
776␉␉␉␉{␊
777␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
778␉␉␉␉}␊
779␉␉␉␉DBG("%d\n", currcoef);␊
780␉␉␉}␊
781␉␉}␊
782␉␉else if (currcoef)␊
783␉␉{␊
784␉␉␉if (currdiv)␊
785␉␉␉{␊
786␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
787␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
788␉␉␉}␊
789␉␉␉else␊
790␉␉␉{␊
791␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
792␉␉␉␉DBG("%d\n", currcoef);␊
793␉␉␉}␊
794␉␉}␊
795␉␉if (!cpuFrequency)␊
796␉␉{␊
797␉␉␉cpuFrequency = tscFrequency;␊
798␉␉}␊
799␉}␊
800␊
801#if 0␊
802␉if (!fsbFrequency)␊
803␉{␊
804␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
805␉␉DBG("CPU: fsbFrequency = 0! using the default value for FSB!\n");␊
806␉␉cpuFrequency = tscFrequency;␊
807␉}␊
808␊
809␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
810␊
811#endif␊
812␊
813␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
814␊
815␉p->CPU.MaxCoef = maxcoef;␊
816␉p->CPU.MaxDiv = maxdiv;␊
817␉p->CPU.CurrCoef = currcoef;␊
818␉p->CPU.CurrDiv = currdiv;␊
819␉p->CPU.TSCFrequency = tscFrequency;␊
820␉p->CPU.FSBFrequency = fsbFrequency;␊
821␉p->CPU.CPUFrequency = cpuFrequency;␊
822␊
823␉// keep formatted with spaces instead of tabs␊
824␉DBG("\n------------------------------\n");␊
825 ␉DBG("\tCPU INFO\n");␊
826␉DBG("------------------------------\n");␊
827␊
828␉DBG("CPUID Raw Values:\n");␊
829␉for (i = 0; i < CPUID_MAX; i++)␊
830␉{␊
831␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
832␉}␊
833␉DBG("\n");␊
834␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
835␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
836␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
837␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊
838␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
839␉/*switch (p->CPU.Type) {␊
840␉␉case PT_OEM:␊
841␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
842␉␉␉break;␊
843␉␉case PT_OD:␊
844␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
845␉␉␉break;␊
846␉␉case PT_DUAL:␊
847␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
848␉␉␉break;␊
849␉␉case PT_RES:␊
850␉␉␉DBG("Processor type: Intel Reserved\n");␊
851␉␉␉break;␊
852␉␉default:␊
853␉␉␉break;␊
854␉}*/␊
855␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
856␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊
857␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
858␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
859␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
860␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
861␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
862␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
863␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
864␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
865␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
866␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
867␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
868␊
869␉DBG("\n---------------------------------------------\n");␊
870#if DEBUG_CPU␊
871␉pause();␊
872#endif␊
873}␊
874

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