1 | /*␊ |
2 | * resolution.h␊ |
3 | * ␊ |
4 | *␉NOTE: I don't beleive this code is production ready / should be in trunk␊ |
5 | * Atleast, not in it's current state. ␊ |
6 | *␊ |
7 | * Created by Evan Lojewski on 3/4/10.␊ |
8 | * Copyright 2009. All rights reserved.␊ |
9 | *␊ |
10 | */␊ |
11 | #ifndef _RESOLUTION_H_␊ |
12 | #define _RESOLUTION_H_␊ |
13 | ␊ |
14 | //#include "libsaio.h"␊ |
15 | //#include "edid.h" //included␊ |
16 | #include "915resolution.h"␊ |
17 | ␊ |
18 | ␊ |
19 | void patchVideoBios()␊ |
20 | {␊ |
21 | ␉UInt32 x = 0, y = 0, bp = 0;␊ |
22 | ␉␊ |
23 | ␉verbose("Resolution:\n");␊ |
24 | ␉getResolution(&x, &y, &bp);␊ |
25 | ␉␊ |
26 | ␉if (x != 0 && y != 0 && bp != 0)␊ |
27 | ␉{␊ |
28 | ␉␉vbios_map * map;␊ |
29 | ␉␉␊ |
30 | ␉␉map = open_vbios(CT_UNKNOWN);␊ |
31 | ␉␉if(map)␊ |
32 | ␉␉{␊ |
33 | ␉␉␉unlock_vbios(map);␊ |
34 | ␊ |
35 | ␉␉␉set_mode(map, x, y, bp, 0, 0);␊ |
36 | ␊ |
37 | ␉␉␉relock_vbios(map);␊ |
38 | ␊ |
39 | ␉␉␉close_vbios(map);␊ |
40 | ␉␉}␊ |
41 | ␉}␊ |
42 | }␊ |
43 | ␊ |
44 | ␊ |
45 | /* Copied from 915 resolution created by steve tomljenovic␊ |
46 | *␊ |
47 | * This code is based on the techniques used in :␊ |
48 | *␊ |
49 | * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊ |
50 | * for demonstrating how to shadow the VBIOS into system RAM␊ |
51 | * and then modify it.␊ |
52 | *␊ |
53 | * - 1280patch by Andrew Tipton (andrewtipton null li).␊ |
54 | *␊ |
55 | * - 855resolution by Alain Poirier␊ |
56 | *␊ |
57 | * This source code is into the public domain.␊ |
58 | */␊ |
59 | ␊ |
60 | /**␊ |
61 | **␊ |
62 | **/␊ |
63 | ␊ |
64 | #define CONFIG_MECH_ONE_ADDR␉0xCF8␊ |
65 | #define CONFIG_MECH_ONE_DATA␉0xCFC␊ |
66 | ␊ |
67 | int freqs[] = { 60, 75, 85 };␊ |
68 | ␊ |
69 | UInt32 get_chipset_id(void)␊ |
70 | {␊ |
71 | ␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊ |
72 | ␉return inl(CONFIG_MECH_ONE_DATA);␊ |
73 | }␊ |
74 | ␊ |
75 | chipset_type get_chipset(UInt32 id)␊ |
76 | {␊ |
77 | ␉chipset_type type;␊ |
78 | ␉␉␊ |
79 | ␉switch (id) {␊ |
80 | ␉␉case 0x35758086:␊ |
81 | ␉␉␉type = CT_830;␊ |
82 | ␉␉␉break;␊ |
83 | ␉␉␉␊ |
84 | ␉␉case 0x25608086:␊ |
85 | ␉␉␉type = CT_845G;␊ |
86 | ␉␉␉break;␊ |
87 | ␉␉␉␊ |
88 | ␉␉case 0x35808086:␊ |
89 | ␉␉␉type = CT_855GM;␊ |
90 | ␉␉␉break;␊ |
91 | ␉␉␉␊ |
92 | ␉␉case 0x25708086:␊ |
93 | ␉␉␉type = CT_865G;␊ |
94 | ␉␉␉break;␊ |
95 | ␉␉␉␊ |
96 | ␉␉case 0x25808086:␊ |
97 | ␉␉␉type = CT_915G;␊ |
98 | ␉␉␉break;␊ |
99 | ␉␉␉␊ |
100 | ␉␉case 0x25908086:␊ |
101 | ␉␉␉type = CT_915GM;␊ |
102 | ␉␉␉break;␊ |
103 | ␉␉␉␊ |
104 | ␉␉case 0x27708086:␊ |
105 | ␉␉␉type = CT_945G;␊ |
106 | ␉␉␉break;␊ |
107 | ␉␉␉␊ |
108 | ␉␉case 0x27a08086:␊ |
109 | ␉␉␉type = CT_945GM;␊ |
110 | ␉␉␉break;␊ |
111 | ␉␉␉␊ |
112 | ␉␉case 0x27ac8086:␊ |
113 | ␉␉␉type = CT_945GME;␊ |
114 | ␉␉␉break;␊ |
115 | ␉␉␉␊ |
116 | ␉␉case 0x29708086:␊ |
117 | ␉␉␉type = CT_946GZ;␊ |
118 | ␉␉␉break;␊ |
119 | ␉␉␉␊ |
120 | ␉␉case 0x27748086:␊ |
121 | ␉␉␉type = CT_955X;␊ |
122 | ␉␉␉break;␊ |
123 | ␉␉␉␊ |
124 | ␉␉case 0x277c8086:␊ |
125 | ␉␉␉type = CT_975X;␊ |
126 | ␉␉␉break;␊ |
127 | ␊ |
128 | ␉␉case 0x29a08086:␊ |
129 | ␉␉␉type = CT_G965;␊ |
130 | ␉␉␉break;␊ |
131 | ␉␉␉␊ |
132 | ␉␉case 0x29908086:␊ |
133 | ␉␉␉type = CT_Q965;␊ |
134 | ␉␉␉break;␊ |
135 | ␉␉␉␊ |
136 | ␉␉case 0x81008086:␊ |
137 | ␉␉␉type = CT_500;␊ |
138 | ␉␉␉break;␊ |
139 | ␉␉␉␊ |
140 | ␉␉case 0x2e108086:␊ |
141 | ␉␉case 0X2e908086:␊ |
142 | ␉␉␉type = CT_B43;␊ |
143 | ␉␉␉break;␊ |
144 | ␊ |
145 | ␉␉case 0x2e208086:␊ |
146 | ␉␉␉type = CT_P45;␊ |
147 | ␉␉␉break;␊ |
148 | ␊ |
149 | ␉␉case 0x2e308086:␊ |
150 | ␉␉␉type = CT_G41;␊ |
151 | ␉␉␉break;␊ |
152 | ␉␉␉␉␉␊ |
153 | ␉␉case 0x29c08086:␊ |
154 | ␉␉␉type = CT_G31;␊ |
155 | ␉␉␉break;␊ |
156 | ␉␉␉␊ |
157 | ␉␉case 0x29208086:␊ |
158 | ␉␉␉type = CT_G45;␊ |
159 | ␉␉␉break;␊ |
160 | ␉␉␉␊ |
161 | ␉␉case 0xA0108086:␉// mobile␊ |
162 | ␉␉case 0xA0008086:␉// desktop␊ |
163 | ␉␉␉type = CT_3150;␊ |
164 | ␉␉␉break;␊ |
165 | ␉␉␉␊ |
166 | ␉␉case 0x2a008086:␊ |
167 | ␉␉␉type = CT_965GM;␊ |
168 | ␉␉␉break;␊ |
169 | ␉␉␉␊ |
170 | ␉␉case 0x29e08086:␊ |
171 | ␉␉␉type = CT_X48;␊ |
172 | ␉␉␉break;␉␉␉␊ |
173 | ␉␉␉␉␊ |
174 | ␉␉case 0x2a408086:␊ |
175 | ␉␉␉type = CT_GM45;␊ |
176 | ␉␉␉break;␊ |
177 | ␉␉␉␊ |
178 | ␉␉␉//␊ |
179 | ␉␉␉// Core processors␊ |
180 | ␉␉␉// http://pci-ids.ucw.cz/read/PC/8086␊ |
181 | ␉␉␉//␊ |
182 | ␉␉case 0x00408086: // Core Processor DRAM Controller␊ |
183 | ␉␉case 0x00448086: // Core Processor DRAM Controller␊ |
184 | ␉␉case 0x00488086: // Core Processor DRAM Controller␊ |
185 | ␉␉case 0x00698086: // Core Processor DRAM Controller␊ |
186 | ␉␉␉␊ |
187 | ␉␉case 0x01008086: // 2nd Generation Core Processor Family DRAM Controller␊ |
188 | ␉␉case 0x01048086: // 2nd Generation Core Processor Family DRAM Controller␊ |
189 | ␉␉case 0x01088086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊ |
190 | ␉␉case 0x010c8086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊ |
191 | ␊ |
192 | ␉␉case 0x01508086: // 3rd Generation Core Processor Family DRAM Controller␊ |
193 | ␉␉case 0x01548086: // 3rd Generation Core Processor Family DRAM Controller␊ |
194 | ␉␉case 0x01588086: // 3rd Generation Core Processor Family DRAM Controller␊ |
195 | ␉␉case 0x015c8086: // 3rd Generation Core Processor Family DRAM Controller␊ |
196 | ␉␉␉verbose(" core proc identified\n");␊ |
197 | ␉␉␉type = CT_CORE_PROC;␊ |
198 | ␉␉␉break;␊ |
199 | ␉␉␉␊ |
200 | ␉␉default:␊ |
201 | ␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊ |
202 | ␉␉␉{␊ |
203 | ␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊ |
204 | ␉␉␉␉//getc();␊ |
205 | ␉␉␉␉type = CT_UNKNOWN_INTEL;␊ |
206 | ␉␉␉␉//type = CT_UNKNOWN;␊ |
207 | ␊ |
208 | ␉␉␉}␊ |
209 | ␉␉␉else␊ |
210 | ␉␉␉{␊ |
211 | ␉␉␉␉type = CT_UNKNOWN;␊ |
212 | ␉␉␉}␊ |
213 | ␉␉␉break;␊ |
214 | ␉}␊ |
215 | ␊ |
216 | ␉return type;␊ |
217 | }␊ |
218 | ␊ |
219 | vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊ |
220 | {␊ |
221 | ␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊ |
222 | ␉return ptr;␊ |
223 | }␊ |
224 | ␊ |
225 | vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊ |
226 | {␊ |
227 | ␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊ |
228 | ␉return ptr;␊ |
229 | }␊ |
230 | ␊ |
231 | vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊ |
232 | {␊ |
233 | ␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊ |
234 | ␉return ptr;␊ |
235 | }␊ |
236 | ␊ |
237 | char detect_bios_type(vbios_map * map, char modeline, int entry_size);␊ |
238 | char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊ |
239 | {␊ |
240 | ␉UInt32 i;␊ |
241 | ␉UInt16 r1, r2;␊ |
242 | ␉␊ |
243 | ␉r1 = r2 = 32000;␊ |
244 | ␉␊ |
245 | ␉for (i=0; i < map->mode_table_size; i++)␊ |
246 | ␉{␊ |
247 | ␉␉if (map->mode_table[i].resolution <= r1)␊ |
248 | ␉␉{␊ |
249 | ␉␉␉r1 = map->mode_table[i].resolution;␊ |
250 | ␉␉}␊ |
251 | ␉␉else␊ |
252 | ␉␉{␊ |
253 | ␉␉␉if (map->mode_table[i].resolution <= r2)␊ |
254 | ␉␉␉{␊ |
255 | ␉␉␉␉r2 = map->mode_table[i].resolution;␊ |
256 | ␉␉␉}␊ |
257 | ␉␉}␊ |
258 | ␊ |
259 | ␉␉//printf("r1 = %d r2 = %d\n", r1, r2);␊ |
260 | ␉}␊ |
261 | ␉␊ |
262 | ␉return (r2-r1-6) % entry_size == 0;␊ |
263 | }␊ |
264 | ␊ |
265 | void close_vbios(vbios_map * map);␊ |
266 | ␊ |
267 | char detect_ati_bios_type(vbios_map * map)␊ |
268 | {␉␊ |
269 | ␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊ |
270 | }␊ |
271 | ␊ |
272 | ␊ |
273 | vbios_map * open_vbios(chipset_type forced_chipset)␊ |
274 | {␊ |
275 | ␉UInt32 z;␊ |
276 | ␉vbios_map * map = malloc(sizeof(vbios_map));␊ |
277 | ␉if (!map)␊ |
278 | ␉{␊ |
279 | ␉␉return 0;␊ |
280 | ␉}␊ |
281 | ␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊ |
282 | ␉/*␊ |
283 | ␉ * Determine chipset␊ |
284 | ␉ */␊ |
285 | ␉␊ |
286 | ␉if (forced_chipset == CT_UNKNOWN)␊ |
287 | ␉{␊ |
288 | ␉␉map->chipset_id = get_chipset_id();␊ |
289 | ␉␉map->chipset = get_chipset(map->chipset_id);␊ |
290 | ␉}␊ |
291 | ␉else if (forced_chipset != CT_UNKNOWN)␊ |
292 | ␉{␊ |
293 | ␉␉map->chipset = forced_chipset;␊ |
294 | ␉}␊ |
295 | ␉␊ |
296 | ␉␊ |
297 | ␉if (map->chipset == CT_UNKNOWN)␊ |
298 | ␉{␊ |
299 | ␉␉verbose(" Unknown chipset type: %08x.\n", (unsigned) map->chipset_id);␊ |
300 | ␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊ |
301 | ␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊ |
302 | ␉␉close_vbios(map);␊ |
303 | ␉␉return 0;␊ |
304 | ␉} else {␊ |
305 | ␉␉verbose(" Detected chipset/proc id (DRAM controller): %08x\n", (unsigned) map->chipset_id);␊ |
306 | ␉}␊ |
307 | ␉␊ |
308 | ␉␊ |
309 | ␉verbose(" VBios: ");␊ |
310 | ␉/*␊ |
311 | ␉ * Map the video bios to memory␊ |
312 | ␉ */␊ |
313 | ␉map->bios_ptr=(char*)VBIOS_START;␊ |
314 | ␉␊ |
315 | ␉/*␊ |
316 | ␉ * check if we have ATI Radeon␊ |
317 | ␉ */␊ |
318 | ␉map->ati_tables.base = map->bios_ptr;␊ |
319 | ␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊ |
320 | ␉if (strncmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM", sizeof("ATOM")) == 0)␊ |
321 | ␉{␊ |
322 | ␉␉verbose("ATI");␊ |
323 | ␉␉// ATI Radeon Card␊ |
324 | ␉␉map->bios = BT_ATI_1;␊ |
325 | ␉␉␊ |
326 | ␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊ |
327 | ␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊ |
328 | ␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊ |
329 | ␉␉␊ |
330 | ␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊ |
331 | ␉␉if (map->ati_mode_table == 0)␊ |
332 | ␉␉{␊ |
333 | ␉␉␉printf("Unable to locate the mode table.\n");␊ |
334 | ␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
335 | ␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
336 | ␉␉␉printf("Chipset: %d\n", map->chipset);␊ |
337 | ␉␉␉close_vbios(map);␊ |
338 | ␉␉␉return 0;␊ |
339 | ␉␉}␊ |
340 | ␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊ |
341 | ␉␉␊ |
342 | ␉␉if (!detect_ati_bios_type(map))␊ |
343 | ␉␉{␊ |
344 | ␉␉␉map->bios = BT_ATI_2;␊ |
345 | ␉␉}␊ |
346 | ␊ |
347 | ␉␉if (map->bios == BT_ATI_1)␊ |
348 | ␉␉{␊ |
349 | ␉␉␉verbose(", BT_ATI_1\n");␊ |
350 | ␉␉} else {␊ |
351 | ␉␉␉verbose(", BT_ATI_2\n");␊ |
352 | ␉␉}␊ |
353 | ␉}␊ |
354 | ␉else␊ |
355 | ␉{␊ |
356 | ␉␉␊ |
357 | ␉␉/*␊ |
358 | ␉␉ * check if we have NVIDIA␊ |
359 | ␉␉ */␊ |
360 | ␊ |
361 | ␉␉int i = 0;␊ |
362 | ␉␉while (i < 512)␊ |
363 | ␉␉{ // we don't need to look through the whole bios, just the first 512 bytes␊ |
364 | ␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊ |
365 | ␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊ |
366 | ␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊ |
367 | ␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊ |
368 | ␉␉␉{␊ |
369 | ␉␉␉␉verbose("nVidia\n");␊ |
370 | ␉␉␉␉map->bios = BT_NVDA;␊ |
371 | ␉␉␉␉unsigned short nv_data_table_offset = 0;␊ |
372 | ␉␉␉␉unsigned short * nv_data_table;␊ |
373 | ␉␉␉␉NV_VESA_TABLE * std_vesa;␊ |
374 | ␉␉␉␉␊ |
375 | ␉␉␉␉int i = 0;␊ |
376 | ␊ |
377 | ␉␉␉␉while (i < 0x300)␊ |
378 | ␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊ |
379 | ␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊ |
380 | ␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊ |
381 | ␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊ |
382 | ␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊ |
383 | ␉␉␉␉␉{␊ |
384 | ␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊ |
385 | ␉␉␉␉␉␉break;␊ |
386 | ␉␉␉␉␉}␊ |
387 | ␉␉␉␉␉i++;␊ |
388 | ␉␉␉␉}␊ |
389 | ␉␉␉␉␊ |
390 | ␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊ |
391 | ␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊ |
392 | ␉␉␉␉␊ |
393 | ␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊ |
394 | ␉␉␉␉if (map->nv_mode_table == 0)␊ |
395 | ␉␉␉␉{␊ |
396 | ␉␉␉␉␉printf("Unable to locate the mode table.\n");␊ |
397 | ␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
398 | ␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
399 | ␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊ |
400 | ␉␉␉␉␉close_vbios(map);␊ |
401 | ␉␉␉␉␉return 0;␊ |
402 | ␉␉␉␉}␊ |
403 | ␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊ |
404 | ␉␉␉␉␊ |
405 | ␉␉␉␉break;␊ |
406 | ␉␉␉}␊ |
407 | ␉␉␉i++;␊ |
408 | ␉␉}␊ |
409 | ␉}␊ |
410 | ␉␊ |
411 | ␊ |
412 | ␉/*␊ |
413 | ␉ * check if we have Intel␊ |
414 | ␉ */␊ |
415 | ␊ |
416 | ␉/*if (map->chipset == CT_UNKNOWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊ |
417 | ␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊ |
418 | ␊ |
419 | ␉ printf("Chipset Id: %x\n", map->chipset_id);␊ |
420 | ␊ |
421 | ␉ printf("Please report this problem to stomljen@yahoo.com\n");␊ |
422 | ␊ |
423 | ␉ close_vbios(map);␊ |
424 | ␉ return 0;␊ |
425 | ␉ }*/␊ |
426 | ␊ |
427 | ␉/*␊ |
428 | ␉ * check for others␊ |
429 | ␉ */␊ |
430 | ␉␊ |
431 | ␉/*␊ |
432 | ␉ * Figure out where the mode table is ␊ |
433 | ␉ */␊ |
434 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA)) ␊ |
435 | ␉{␊ |
436 | ␉␉char* p = map->bios_ptr + 16;␊ |
437 | ␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊ |
438 | ␉␉␊ |
439 | ␉␉verbose("Other");␊ |
440 | ␉␉while (p < limit && map->mode_table == 0)␊ |
441 | ␉␉{␊ |
442 | ␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊ |
443 | ␉␉␉␊ |
444 | ␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊ |
445 | ␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊ |
446 | ␉␉␉{␊ |
447 | ␉␉␉␉map->mode_table = mode_ptr;␊ |
448 | ␉␉␉}␊ |
449 | ␉␉␉␊ |
450 | ␉␉␉p++;␊ |
451 | ␉␉}␊ |
452 | ␊ |
453 | ␉␉if (map->mode_table == 0)␊ |
454 | ␉␉{␊ |
455 | ␉␉␉close_vbios(map);␊ |
456 | ␉␉␉return 0;␊ |
457 | ␉␉}␊ |
458 | ␉}␊ |
459 | ␉␊ |
460 | ␉␊ |
461 | ␉/*␊ |
462 | ␉ * Determine size of mode table␊ |
463 | ␉ */␊ |
464 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
465 | ␉{␊ |
466 | ␉␉vbios_mode * mode_ptr = map->mode_table;␊ |
467 | ␉␉␊ |
468 | ␉␉while (mode_ptr->mode != 0xff)␊ |
469 | ␉␉{␊ |
470 | ␉␉␉map->mode_table_size++;␊ |
471 | ␉␉␉mode_ptr++;␊ |
472 | ␉␉}␊ |
473 | ␉}␊ |
474 | ␉␊ |
475 | ␉/*␊ |
476 | ␉ * Figure out what type of bios we have␊ |
477 | ␉ * order of detection is important␊ |
478 | ␉ */␊ |
479 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
480 | ␉{␊ |
481 | ␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊ |
482 | ␉␉{␊ |
483 | ␉␉␉map->bios = BT_3;␊ |
484 | ␉␉␉verbose(", BT_3\n");␊ |
485 | ␉␉}␊ |
486 | ␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊ |
487 | ␉␉{␊ |
488 | ␉␉␉map->bios = BT_2;␊ |
489 | ␉␉␉verbose(", BT_2\n");␊ |
490 | ␉␉}␊ |
491 | ␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊ |
492 | ␉␉{␊ |
493 | ␉␉␉map->bios = BT_1;␊ |
494 | ␉␉␉verbose(", BT_1\n");␊ |
495 | ␉␉}␊ |
496 | ␉␉else {␊ |
497 | ␉␉␉verbose(" - unknown\n");␊ |
498 | ␉␉␉return 0;␊ |
499 | ␉␉}␊ |
500 | ␉}␊ |
501 | ␉␊ |
502 | ␉return map;␊ |
503 | }␊ |
504 | ␊ |
505 | void close_vbios(vbios_map * map)␊ |
506 | {␊ |
507 | ␉free(map);␊ |
508 | }␊ |
509 | ␊ |
510 | void unlock_vbios(vbios_map * map)␊ |
511 | {␊ |
512 | ␊ |
513 | ␉map->unlocked = TRUE;␊ |
514 | ␊ |
515 | ␉switch (map->chipset) {␊ |
516 | ␉␉case CT_UNKNOWN:␊ |
517 | ␉␉␉break;␊ |
518 | ␉␉case CT_830:␊ |
519 | ␉␉case CT_855GM:␊ |
520 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
521 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
522 | ␉␉␉␊ |
523 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
524 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
525 | ␉␉␉break;␊ |
526 | ␉␉case CT_845G:␊ |
527 | ␉␉case CT_865G:␊ |
528 | ␉␉case CT_915G:␊ |
529 | ␉␉case CT_915GM:␊ |
530 | ␉␉case CT_945G:␊ |
531 | ␉␉case CT_945GM:␊ |
532 | ␉␉case CT_945GME:␊ |
533 | ␉␉case CT_946GZ:␊ |
534 | ␉␉case CT_G965:␊ |
535 | ␉␉case CT_Q965:␊ |
536 | ␉␉case CT_965GM:␊ |
537 | ␉␉case CT_975X:␊ |
538 | ␉␉case CT_P35:␊ |
539 | ␉␉case CT_955X:␊ |
540 | ␉␉case CT_X48:␊ |
541 | ␉␉case CT_B43:␊ |
542 | ␉␉case CT_Q45:␊ |
543 | ␉␉case CT_P45:␊ |
544 | ␉␉case CT_GM45:␊ |
545 | ␉␉case CT_G45:␊ |
546 | ␉␉case CT_G41:␊ |
547 | ␉␉case CT_G31:␊ |
548 | ␉␉case CT_500:␊ |
549 | ␉␉case CT_3150:␊ |
550 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
551 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
552 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
553 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
554 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
555 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
556 | ␉␉␉break;␊ |
557 | ␉␉case CT_CORE_PROC:␉ // Core procs - PAM regs are 80h - 86h␊ |
558 | ␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊ |
559 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
560 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
561 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
562 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
563 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
564 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
565 | ␉␉␉break;␊ |
566 | ␉␉default:␊ |
567 | ␉␉␉break;␊ |
568 | ␉}␊ |
569 | ␉␊ |
570 | #if DEBUG␊ |
571 | ␉{␊ |
572 | ␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
573 | ␉␉verbose("unlock PAM: (0x%08x)\n", t);␊ |
574 | ␉}␊ |
575 | #endif␊ |
576 | }␊ |
577 | ␊ |
578 | void relock_vbios(vbios_map * map)␊ |
579 | {␊ |
580 | ␉␊ |
581 | ␉map->unlocked = FALSE;␊ |
582 | ␉␊ |
583 | ␉switch (map->chipset)␊ |
584 | ␉{␊ |
585 | ␉␉case CT_UNKNOWN:␊ |
586 | ␉␉␉break;␊ |
587 | ␉␉case CT_830:␊ |
588 | ␉␉case CT_855GM:␊ |
589 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
590 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊ |
591 | ␉␉␉break;␊ |
592 | ␉␉case CT_845G:␊ |
593 | ␉␉case CT_865G:␊ |
594 | ␉␉case CT_915G:␊ |
595 | ␉␉case CT_915GM:␊ |
596 | ␉␉case CT_945G:␊ |
597 | ␉␉case CT_945GM:␊ |
598 | ␉␉case CT_945GME:␊ |
599 | ␉␉case CT_946GZ:␊ |
600 | ␉␉case CT_G965:␊ |
601 | ␉␉case CT_955X:␊ |
602 | ␉␉case CT_G45:␊ |
603 | ␉␉case CT_Q965:␊ |
604 | ␉␉case CT_965GM:␊ |
605 | ␉␉case CT_975X:␊ |
606 | ␉␉case CT_P35:␊ |
607 | ␉␉case CT_X48:␊ |
608 | ␉␉case CT_B43:␊ |
609 | ␉␉case CT_Q45:␊ |
610 | ␉␉case CT_P45:␊ |
611 | ␉␉case CT_GM45:␊ |
612 | ␉␉case CT_G41:␊ |
613 | ␉␉case CT_G31:␊ |
614 | ␉␉case CT_500:␊ |
615 | ␉␉case CT_3150:␊ |
616 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
617 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
618 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
619 | ␉␉␉break;␊ |
620 | ␉␉case CT_CORE_PROC:␊ |
621 | ␉␉case CT_UNKNOWN_INTEL:␊ |
622 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
623 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
624 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
625 | ␉␉default:␊ |
626 | ␉␉␉break;␊ |
627 | ␉}␊ |
628 | ␉␊ |
629 | #if DEBUG␊ |
630 | ␉{␊ |
631 | UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
632 | ␉␉verbose("relock PAM: (0x%08x)\n", t);␊ |
633 | ␉}␊ |
634 | #endif␊ |
635 | }␊ |
636 | ␊ |
637 | ␊ |
638 | int getMode(edid_mode *mode)␊ |
639 | {␊ |
640 | ␉char* edidInfo = readEDID();␊ |
641 | ␉␉␉␊ |
642 | ␉if(!edidInfo) return 1;␊ |
643 | //Slice␊ |
644 | ␉if(!fb_parse_edid((struct EDID *)edidInfo, mode) || !mode->h_active) ␊ |
645 | ␉{␊ |
646 | ␉␉free( edidInfo );␊ |
647 | ␉␉return 1;␊ |
648 | ␉}␊ |
649 | /*␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊ |
650 | ␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊ |
651 | ␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊ |
652 | ␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊ |
653 | ␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊ |
654 | ␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊ |
655 | ␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊ |
656 | ␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊ |
657 | ␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊ |
658 | */␉␉␊ |
659 | ␊ |
660 | ␉free( edidInfo );␊ |
661 | ␉␉␊ |
662 | ␉if(!mode->h_active) return 1;␊ |
663 | ␊ |
664 | ␉return 0;␊ |
665 | ␉␉␊ |
666 | }␊ |
667 | ␊ |
668 | ␊ |
669 | static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊ |
670 | ␉␉␉␉␉␉unsigned long *clock,␊ |
671 | ␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊ |
672 | ␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊ |
673 | {␊ |
674 | ␉UInt32 hbl, vbl, vfreq;␊ |
675 | ␉␊ |
676 | ␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊ |
677 | ␉vfreq = vbl * freq;␊ |
678 | ␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊ |
679 | ␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊ |
680 | ␊ |
681 | ␉*vsyncstart = y;␊ |
682 | ␉*vsyncend = y + 3;␊ |
683 | ␉*vblank = vbl - 1;␊ |
684 | ␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊ |
685 | ␉*hsyncend = x + hbl / 2 - 1;␊ |
686 | ␉*hblank = x + hbl - 1;␊ |
687 | ␉*clock = (x + hbl) * vfreq / 1000;␊ |
688 | }␊ |
689 | ␊ |
690 | void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊ |
691 | ␉UInt32 xprev, yprev;␊ |
692 | ␉UInt32 i = 0, j;␊ |
693 | ␉// patch first available mode␊ |
694 | ␉␊ |
695 | ␉//␉for (i=0; i < map->mode_table_size; i++) {␊ |
696 | ␉//␉␉if (map->mode_table[0].mode == mode) {␊ |
697 | ␉verbose(" Patching: ");␊ |
698 | ␉switch(map->bios) {␊ |
699 | ␉␉case BT_INTEL:␊ |
700 | ␉␉␉verbose("BT_INTEL - not supported\n");␊ |
701 | ␉␉␉return;␊ |
702 | ␊ |
703 | ␉␉case BT_1:␊ |
704 | ␉␉{␊ |
705 | ␉␉␉verbose("BT_1 patched.\n");␊ |
706 | ␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊ |
707 | ␉␉␉␊ |
708 | ␉␉␉if (bp)␊ |
709 | ␉␉␉{␊ |
710 | ␉␉␉␉map->mode_table[i].bits_per_pixel = (uint8_t)bp;␊ |
711 | ␉␉␉}␊ |
712 | ␉␉␉␊ |
713 | ␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊ |
714 | ␉␉␉res->x1 = (x & 0xff);␊ |
715 | ␉␉␉␊ |
716 | ␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊ |
717 | ␉␉␉res->y1 = (y & 0xff);␊ |
718 | ␉␉␉if (htotal)␊ |
719 | ␉␉␉{␊ |
720 | ␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊ |
721 | ␉␉␉}␊ |
722 | ␉␉␉if (vtotal)␊ |
723 | ␉␉␉{␊ |
724 | ␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊ |
725 | ␉␉␉}␊ |
726 | ␉␉␉break;␊ |
727 | ␉␉}␊ |
728 | ␉␉case BT_2:␊ |
729 | ␉␉{␊ |
730 | ␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊ |
731 | ␉␉␉␊ |
732 | ␉␉␉res->xchars = (uint8_t)(x / 8);␊ |
733 | ␉␉␉res->ychars = (uint8_t)(y / 16 - 1);␊ |
734 | ␉␉␉xprev = res->modelines[0].x1;␊ |
735 | ␉␉␉yprev = res->modelines[0].y1;␊ |
736 | ␉␉␉␊ |
737 | ␉␉␉for(j=0; j < 3; j++) {␊ |
738 | ␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊ |
739 | ␉␉␉␉␊ |
740 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev)␊ |
741 | ␉␉␉␉{␊ |
742 | ␉␉␉␉␉modeline->x1 = modeline->x2 = (uint16_t)(x-1);␊ |
743 | ␉␉␉␉␉modeline->y1 = modeline->y2 = (uint16_t)(y-1);␊ |
744 | ␉␉␉␉␉␊ |
745 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
746 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
747 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
748 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
749 | ␉␉␉␉␉␊ |
750 | ␉␉␉␉␉if (htotal)␊ |
751 | ␉␉␉␉␉{␊ |
752 | ␉␉␉␉␉␉modeline->htotal = (uint16_t)htotal;␊ |
753 | ␉␉␉␉␉}␊ |
754 | ␉␉␉␉␉else␊ |
755 | ␉␉␉␉␉{␊ |
756 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
757 | ␉␉␉␉␉}␊ |
758 | ␉␉␉␉␉if (vtotal)␊ |
759 | ␉␉␉␉␉{␊ |
760 | ␉␉␉␉␉␉modeline->vtotal = (uint16_t)vtotal;␊ |
761 | ␉␉␉␉␉}␊ |
762 | ␉␉␉␉␉else␊ |
763 | ␉␉␉␉␉{␊ |
764 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
765 | ␉␉␉␉␉}␊ |
766 | ␉␉␉␉}␊ |
767 | ␉␉␉}␊ |
768 | ␉␉␉verbose("BT_1 patched.\n");␊ |
769 | ␉␉␉break;␊ |
770 | ␉␉}␊ |
771 | ␉␉case BT_3:␊ |
772 | ␉␉{␊ |
773 | ␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊ |
774 | ␉␉␉␊ |
775 | ␉␉␉xprev = res->modelines[0].x1;␊ |
776 | ␉␉␉yprev = res->modelines[0].y1;␊ |
777 | ␉␉␉␊ |
778 | ␉␉␉for (j=0; j < 3; j++)␊ |
779 | ␉␉␉{␊ |
780 | ␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊ |
781 | ␉␉␉␉␊ |
782 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev)␊ |
783 | ␉␉␉␉{␊ |
784 | ␉␉␉␉␉modeline->x1 = modeline->x2 = (uint16_t)(x-1);␊ |
785 | ␉␉␉␉␉modeline->y1 = modeline->y2 = (uint16_t)(y-1);␊ |
786 | ␉␉␉␉␉␊ |
787 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
788 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
789 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
790 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
791 | ␉␉␉␉␉if (htotal)␊ |
792 | ␉␉␉␉␉{␊ |
793 | ␉␉␉␉␉␉modeline->htotal = (uint16_t)htotal;␊ |
794 | ␉␉␉␉␉}␊ |
795 | ␉␉␉␉␉else␊ |
796 | ␉␉␉␉␉{␊ |
797 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
798 | ␉␉␉␉␉}␊ |
799 | ␉␉␉␉␉if (vtotal)␊ |
800 | ␉␉␉␉␉{␊ |
801 | ␉␉␉␉␉␉modeline->vtotal = (uint16_t)vtotal;␊ |
802 | ␉␉␉␉␉}␊ |
803 | ␉␉␉␉␉else␊ |
804 | ␉␉␉␉␉{␊ |
805 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
806 | ␉␉␉␉␉}␊ |
807 | ␉␉␉␉␉modeline->timing_h = (uint16_t)(y-1);␊ |
808 | ␉␉␉␉␉modeline->timing_v = (uint16_t)(x-1);␊ |
809 | ␉␉␉␉}␊ |
810 | ␉␉␉}␊ |
811 | ␉␉␉verbose("BT_3 patched.\n");␊ |
812 | ␉␉␉break;␊ |
813 | ␉␉}␊ |
814 | ␉␉case BT_ATI_1:␊ |
815 | ␉␉{␊ |
816 | ␉␉␉verbose("BT_ATI_1");␊ |
817 | ␉␉␉edid_mode mode;␊ |
818 | ␉␉␉␉␊ |
819 | ␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊ |
820 | ␊ |
821 | ␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force){␊ |
822 | ␉␉␉if (!getMode(&mode))␊ |
823 | ␉␉␉{␊ |
824 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊ |
825 | ␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊ |
826 | ␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊ |
827 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
828 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊ |
829 | ␉␉␉␉␉␊ |
830 | ␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊ |
831 | ␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊ |
832 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
833 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊ |
834 | ␊ |
835 | ␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊ |
836 | ␉␉␉}␊ |
837 | ␉␉␉else␊ |
838 | ␉␉␉{␊ |
839 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
840 | ␉␉␉}␊ |
841 | ␉␉␉/*else␊ |
842 | ␉␉␉{␊ |
843 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
844 | ␊ |
845 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
846 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
847 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
848 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
849 | ␊ |
850 | ␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊ |
851 | ␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊ |
852 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊ |
853 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
854 | ␊ |
855 | ␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊ |
856 | ␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊ |
857 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊ |
858 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊ |
859 | ␉␉␉␉␉␉␉␉␉␉␉␉␊ |
860 | ␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊ |
861 | ␉␉␉ }*/␊ |
862 | ␊ |
863 | ␉␉␉break;␊ |
864 | ␉␉}␊ |
865 | ␉␉case BT_ATI_2:␊ |
866 | ␉␉{␊ |
867 | ␉␉␉verbose("BT_ATI_2");␊ |
868 | ␉␉␉edid_mode mode;␊ |
869 | ␉␉␉␉␉␉␊ |
870 | ␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊ |
871 | ␉␉␉␊ |
872 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
873 | ␉␉␉if (!getMode(&mode))␊ |
874 | ␉␉␉{␊ |
875 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊ |
876 | ␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊ |
877 | ␉␉␉␉mode_timing->usHActive = mode.h_active;␊ |
878 | ␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊ |
879 | ␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊ |
880 | ␉␉␉␉␉␉␉␉␉␉␊ |
881 | ␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊ |
882 | ␉␉␉␉mode_timing->usVActive = mode.v_active;␊ |
883 | ␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊ |
884 | ␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊ |
885 | ␉␉␉␉␉␉␉␉␉␉␊ |
886 | ␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊ |
887 | ␉␉␉}␊ |
888 | ␉␉␉else␊ |
889 | ␉␉␉{␊ |
890 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
891 | ␉␉␉}␊ |
892 | ␉␉␉/*else␊ |
893 | ␉␉␉{␊ |
894 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
895 | ␉␉␉␊ |
896 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
897 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
898 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
899 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
900 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
901 | ␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊ |
902 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usHActive = x;␊ |
903 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊ |
904 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
905 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
906 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊ |
907 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVActive = y;␊ |
908 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊ |
909 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
910 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
911 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊ |
912 | ␉␉␉␉␉␉␉␉␉␉}*/␊ |
913 | ␊ |
914 | ␉␉␉break;␊ |
915 | ␉␉}␊ |
916 | ␉␉case BT_NVDA:␊ |
917 | ␉␉{␊ |
918 | ␉␉␉verbose("BT_NVDA");␊ |
919 | ␉␉␉edid_mode mode;␊ |
920 | ␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊ |
921 | ␉␉␉␊ |
922 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
923 | ␉␉␉if (!getMode(&mode))␊ |
924 | ␉␉␉{␊ |
925 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode %d patched!\n", mode.h_active, mode.v_active, (int) i);␊ |
926 | ␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊ |
927 | ␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊ |
928 | ␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
929 | ␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊ |
930 | ␉␉␉␉␊ |
931 | ␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊ |
932 | ␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊ |
933 | ␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
934 | ␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊ |
935 | ␉␉␉␉␊ |
936 | ␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊ |
937 | ␉␉␉}␊ |
938 | ␉␉␉ else␊ |
939 | ␉␉␉{␊ |
940 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
941 | ␉␉␉}␊ |
942 | ␉␉␉/*else␊ |
943 | ␉␉␉ {␊ |
944 | ␉␉␉ vbios_modeline_type2 modeline;␊ |
945 | ␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
946 | ␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊ |
947 | ␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊ |
948 | ␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊ |
949 | ␊ |
950 | ␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊ |
951 | ␉␉␉ mode_timing[i].usH_Active = x;␊ |
952 | ␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊ |
953 | ␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊ |
954 | ␊ |
955 | ␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊ |
956 | ␉␉␉ mode_timing[i].usV_Active = y;␊ |
957 | ␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊ |
958 | ␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊ |
959 | ␊ |
960 | ␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊ |
961 | ␉␉␉ }*/␊ |
962 | ␉␉␉break;␊ |
963 | ␉␉}␊ |
964 | ␉␉case BT_UNKNOWN:␊ |
965 | ␉␉{␊ |
966 | ␉␉␉verbose(" Unknown - vbios not patched\n");␊ |
967 | ␉␉␉break;␊ |
968 | ␉␉}␊ |
969 | ␉␉default:␊ |
970 | ␉␉␉break;␊ |
971 | ␉}␊ |
972 | ␉//␉␉}␊ |
973 | ␉//␉}␊ |
974 | }␊ |
975 | ␊ |
976 | #endif // _RESOLUTION_H_␊ |
977 | |