Chameleon

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Root/trunk/i386/libsaio/dram_controllers.c

1/*␊
2 * dram controller access and scan from the pci host controller␊
3 * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊
4 * original source comes from:␊
5 *␊
6 * memtest86␊
7 *␊
8 * Released under version 2 of the Gnu Public License.␊
9 * By Chris Brady, cbrady@sgi.com␊
10 * ----------------------------------------------------␊
11 * MemTest86+ V4.00 Specific code (GPL V2.0)␊
12 * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
13 * http://www.canardpc.com - http://www.memtest.org␊
14 */␊
15␊
16#include "libsaio.h"␊
17#include "bootstruct.h"␊
18#include "pci.h"␊
19#include "platform.h"␊
20#include "dram_controllers.h"␊
21␊
22#ifndef DEBUG_DRAM␊
23#define DEBUG_DRAM 0␊
24#endif␊
25␊
26#if DEBUG_DRAM␊
27#define DBG(x...) printf(x)␊
28#else␊
29#define DBG(x...)␊
30#endif␊
31␊
32/*␊
33 * Initialise memory controller functions␊
34 */␊
35␊
36// Setup P35 Memory Controller␊
37static void setup_p35(pci_dt_t *dram_dev)␊
38{␊
39␉uint32_t dev0;␊
40␊
41␉// Activate MMR I/O␊
42␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
43␉if (!(dev0 & 0x1)) {␊
44␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
45␉}␊
46}␊
47␊
48int nhm_bus = 0x3F;␊
49␊
50// Setup Nehalem Integrated Memory Controller␊
51static void setup_nhm(pci_dt_t *dram_dev)␊
52{␊
53␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
54␉unsigned long did, vid;␊
55␉int i;␊
56␊
57␉// Nehalem supports Scrubbing␊
58␉// First, locate the PCI bus where the MCH is located␊
59␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
60␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊
61␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊
62␉␉vid &= 0xFFFF;␊
63␉␉did &= 0xFF00;␊
64␊
65␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
66␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
67␉␉}␊
68␉}␊
69}␊
70␊
71/*␊
72 * Retrieve memory controller fsb functions␊
73 */␊
74␊
75␊
76// Get i965 Memory Speed␊
77static void get_fsb_i965(pci_dt_t *dram_dev)␊
78{␊
79␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
80␊
81␉long *ptr;␊
82␊
83␉// Find Ratio␊
84␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
85␉dev0 &= 0xFFFFC000;␊
86␉ptr = (long*)(dev0 + 0xC00);␊
87␉mch_cfg = *ptr & 0xFFFF;␊
88␊
89␉mch_ratio = 100000;␊
90␊
91␉switch (mch_cfg & 7) {␊
92␉␉case 0: mch_fsb = 1066; break;␊
93␉␉case 1: mch_fsb = 533; break;␊
94␉␉default:␊
95␉␉case 2: mch_fsb = 800; break;␊
96␉␉case 3: mch_fsb = 667; break;␊
97␉␉case 4: mch_fsb = 1333; break;␊
98␉␉case 6: mch_fsb = 1600; break;␊
99␉}␊
100␊
101␉DBG("mch_fsb %d\n", mch_fsb);␊
102␊
103␉switch (mch_fsb) {␊
104␉␉case 533:␊
105␉␉switch ((mch_cfg >> 4) & 7) {␊
106␉␉␉case 1:␉mch_ratio = 200000; break;␊
107␉␉␉case 2:␉mch_ratio = 250000; break;␊
108␉␉␉case 3:␉mch_ratio = 300000; break;␊
109␉␉}␊
110␉␉break;␊
111␊
112␉␉default:␊
113␉␉case 800:␊
114␉␉switch ((mch_cfg >> 4) & 7) {␊
115␉␉␉case 0:␉mch_ratio = 100000; break;␊
116␉␉␉case 1:␉mch_ratio = 125000; break;␊
117␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊
118␉␉␉case 3:␉mch_ratio = 200000; break;␊
119␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
120␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊
121␉␉}␊
122␉␉break;␊
123␊
124␉␉case 1066:␊
125␉␉switch ((mch_cfg >> 4) & 7) {␊
126␉␉␉case 1:␉mch_ratio = 100000; break;␊
127␉␉␉case 2:␉mch_ratio = 125000; break;␊
128␉␉␉case 3:␉mch_ratio = 150000; break;␊
129␉␉␉case 4:␉mch_ratio = 200000; break;␊
130␉␉␉case 5:␉mch_ratio = 250000; break;␊
131␉␉}␊
132␉␉break;␊
133␊
134␉␉case 1333:␊
135␉␉switch ((mch_cfg >> 4) & 7) {␊
136␉␉␉case 2:␉mch_ratio = 100000; break;␊
137␉␉␉case 3:␉mch_ratio = 120000; break;␊
138␉␉␉case 4:␉mch_ratio = 160000; break;␊
139␉␉␉case 5:␉mch_ratio = 200000; break;␊
140␉␉}␊
141␉␉break;␊
142␊
143␉␉case 1600:␊
144␉␉switch ((mch_cfg >> 4) & 7)␊
145␉␉{␊
146␉␉␉case 3:␉mch_ratio = 100000; break;␊
147␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
148␉␉␉case 5:␉mch_ratio = 150000; break;␊
149␉␉␉case 6:␉mch_ratio = 200000; break;␊
150␉␉}␊
151␉␉break;␊
152␉}␊
153␊
154␉DBG("mch_ratio %d\n", mch_ratio);␊
155␊
156␉// Compute RAM Frequency␊
157␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
158␊
159␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊
160␊
161}␊
162␊
163// Get i965m Memory Speed␊
164static void get_fsb_im965(pci_dt_t *dram_dev)␊
165{␊
166␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
167␊
168␉long *ptr;␊
169␊
170␉// Find Ratio␊
171␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
172␉dev0 &= 0xFFFFC000;␊
173␉ptr = (long*)(dev0 + 0xC00);␊
174␉mch_cfg = *ptr & 0xFFFF;␊
175␊
176␉mch_ratio = 100000;␊
177␊
178␉switch (mch_cfg & 7) {␊
179␉␉case 1: mch_fsb = 533; break;␊
180␉␉default: ␊
181␉␉case 2:␉mch_fsb = 800; break;␊
182␉␉case 3:␉mch_fsb = 667; break;␊
183␉␉case 6:␉mch_fsb = 1066; break;␊
184␉}␊
185␊
186␉switch (mch_fsb) {␊
187␉␉case 533:␊
188␉␉␉switch ((mch_cfg >> 4) & 7) {␊
189␉␉␉␉case 1:␉mch_ratio = 125000; break;␊
190␉␉␉␉case 2:␉mch_ratio = 150000; break;␊
191␉␉␉␉case 3:␉mch_ratio = 200000; break;␊
192␉␉␉}␊
193␉␉␉break;␊
194␊
195␉␉case 667:␊
196␉␉␉switch ((mch_cfg >> 4)& 7) {␊
197␉␉␉␉case 1:␉mch_ratio = 100000; break;␊
198␉␉␉␉case 2:␉mch_ratio = 120000; break;␊
199␉␉␉␉case 3:␉mch_ratio = 160000; break;␊
200␉␉␉␉case 4:␉mch_ratio = 200000; break;␊
201␉␉␉␉case 5:␉mch_ratio = 240000; break;␊
202␉␉␉}␊
203␉␉␉break;␊
204␊
205␉␉default:␊
206␉␉case 800:␊
207␉␉␉switch ((mch_cfg >> 4) & 7) {␊
208␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊
209␉␉␉␉case 2:␉mch_ratio = 100000; break;␊
210␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊
211␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊
212␉␉␉␉case 5:␉mch_ratio = 200000; break;␊
213␉␉␉}␊
214␉␉␉break;␊
215␉␉case 1066:␊
216␉␉␉switch ((mch_cfg >> 4)&7) {␊
217␉␉␉␉case 5:␉mch_ratio = 150000; break;␊
218␉␉␉␉case 6:␉mch_ratio = 200000; break;␊
219␉␉␉}␊
220␊
221␉}␊
222␊
223␉// Compute RAM Frequency␊
224␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
225␉// DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊
226}␊
227␊
228␊
229// Get iCore7 Memory Speed␊
230static void get_fsb_nhm(pci_dt_t *dram_dev)␊
231{␊
232␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
233␊
234␉// Get the clock ratio␊
235␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
236␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
237␊
238␉// Compute RAM Frequency␊
239␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊
240␉// DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊
241}␊
242␊
243/*␊
244 * Retrieve memory controller info functions␊
245 */␊
246␊
247// Get i965 Memory Timings␊
248static void get_timings_i965(pci_dt_t *dram_dev)␊
249{␊
250␉// Thanks for CDH optis␊
251␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊
252␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
253␊
254␉long *ptr;␊
255␊
256␉// Read MMR Base Address␊
257␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
258␉dev0 &= 0xFFFFC000;␊
259␊
260␉ptr = (long*)(dev0 + 0x260);␊
261␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
262␊
263␉ptr = (long*)(dev0 + 0x660);␊
264␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
265␊
266␉// If DIMM 0 not populated, check DIMM 1␊
267␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
268␊
269␉ptr = (long*)(dev0 + offset + 0x29C);␊
270␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
271␊
272␉ptr = (long*)(dev0 + offset + 0x250);␉␊
273␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
274␊
275␉ptr = (long*)(dev0 + offset + 0x252);␊
276␉ACT_Register = *ptr & 0xFFFFFFFF;␊
277␊
278␉ptr = (long*)(dev0 + offset + 0x258);␊
279␉Read_Register = *ptr & 0xFFFFFFFF;␊
280␊
281␉ptr = (long*)(dev0 + offset + 0x244);␊
282␉Misc_Register = *ptr & 0xFFFFFFFF;␊
283␊
284␉// 965 Series only support DDR2␊
285␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
286␊
287␉// CAS Latency (tCAS)␊
288␉Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊
289␊
290␉// RAS-To-CAS (tRCD)␊
291␉Platform.RAM.TRC = (Read_Register >> 16) & 0xF;␊
292␊
293␉// RAS Precharge (tRP)␊
294␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
295␊
296␉// RAS Active to precharge (tRAS)␊
297␉Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊
298␊
299␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊
300␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
301␉} else {␊
302␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
303␉}␊
304}␊
305␊
306// Get im965 Memory Timings␊
307static void get_timings_im965(pci_dt_t *dram_dev)␊
308{␊
309␉// Thanks for CDH optis␊
310␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊
311␉long *ptr;␊
312␊
313␉// Read MMR Base Address␊
314␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
315␉dev0 &= 0xFFFFC000;␊
316␊
317␉ptr = (long*)(dev0 + 0x1200);␊
318␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
319␊
320␉ptr = (long*)(dev0 + 0x1300);␊
321␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
322␊
323␉// If DIMM 0 not populated, check DIMM 1␊
324␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊
325␊
326␉ptr = (long*)(dev0 + offset + 0x121C);␊
327␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
328␊
329␉ptr = (long*)(dev0 + offset + 0x1214);␉␊
330␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
331␊
332␉// Series only support DDR2␊
333␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
334␊
335␉// CAS Latency (tCAS)␊
336␉Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊
337␊
338␉// RAS-To-CAS (tRCD)␊
339␉Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊
340␊
341␉// RAS Precharge (tRP)␊
342␉Platform.RAM.TRP= (Precharge_Register & 7) + 2;␊
343␊
344␉// RAS Active to precharge (tRAS)␊
345␉Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊
346␊
347␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊
348␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
349␉} else {␊
350␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
351␉}␊
352}␊
353␊
354// Get P35 Memory Timings␊
355static void get_timings_p35(pci_dt_t *dram_dev)␊
356{␊
357␉// Thanks for CDH optis␊
358␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊
359␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
360␉long *ptr;␊
361␊
362␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊
363␉//Device_ID &= 0xFFFF;␊
364␊
365␉// Now, read MMR Base Address␊
366␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
367␉dev0 &= 0xFFFFC000;␊
368␊
369␉ptr = (long*)(dev0 + 0x260);␊
370␉c0ckectrl = *ptr & 0xFFFFFFFF;␊
371␊
372␉ptr = (long*)(dev0 + 0x660);␊
373␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
374␊
375␉// If DIMM 0 not populated, check DIMM 1␊
376␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
377␊
378␉ptr = (long*)(dev0 + offset + 0x265);␊
379␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
380␊
381␉ptr = (long*)(dev0 + offset + 0x25D);␊
382␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
383␊
384␉ptr = (long*)(dev0 + offset + 0x252);␊
385␉ACT_Register = *ptr & 0xFFFFFFFF;␊
386␊
387␉ptr = (long*)(dev0 + offset + 0x258);␊
388␉Read_Register = *ptr & 0xFFFFFFFF;␊
389␊
390␉ptr = (long*)(dev0 + offset + 0x244);␊
391␉Misc_Register = *ptr & 0xFFFFFFFF;␊
392␊
393␉ptr = (long*)(dev0 + offset + 0x1E8);␊
394␉Memory_Check = *ptr & 0xFFFFFFFF;␊
395␊
396␉// On P45, check 1A8␊
397␉if(dram_dev->device_id > 0x2E00) {␊
398␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊
399␉␉Memory_Check = *ptr & 0xFFFFFFFF;␊
400␉␉Memory_Check >>= 2;␊
401␉␉Memory_Check &= 1;␊
402␉␉Memory_Check = !Memory_Check;␊
403␉} else {␊
404␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊
405␉␉Memory_Check = *ptr & 0xFFFFFFFF;␊
406␉}␊
407␊
408␉// Determine DDR-II or DDR-III␊
409␉if (Memory_Check & 1) {␊
410␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
411␉} else {␊
412␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
413␉}␊
414␊
415␉// CAS Latency (tCAS)␊
416␉if(dram_dev->device_id > 0x2E00) {␊
417␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊
418␉} else {␊
419␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊
420␉}␊
421␊
422␉// RAS-To-CAS (tRCD)␊
423␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊
424␊
425␉// RAS Precharge (tRP)␊
426␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
427␊
428␉// RAS Active to precharge (tRAS)␊
429␉Platform.RAM.RAS = Precharge_Register & 0x3F;␊
430␊
431␉// Channel configuration␊
432␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) {␊
433␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
434␉} else {␊
435␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
436␉}␊
437}␊
438␊
439// Get Nehalem Memory Timings␊
440static void get_timings_nhm(pci_dt_t *dram_dev)␊
441{␊
442␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊
443␉int fvc_bn = 4;␊
444␊
445␉// Find which channels are populated␊
446␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊
447␉mc_control = (mc_control >> 8) & 0x7;␊
448␊
449␉// DDR-III␊
450␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
451␊
452␉// Get the first valid channel␊
453␉if(mc_control & 1) {␊
454␉␉fvc_bn = 4; ␊
455␉} else if(mc_control & 2) {␊
456␉␉fvc_bn = 5; ␊
457␉} else if(mc_control & 7) {␊
458␉␉fvc_bn = 6; ␊
459␉}␊
460␊
461␉// Now, detect timings␊
462␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
463␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
464␊
465␉// CAS Latency (tCAS)␊
466␉Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊
467␊
468␉// RAS-To-CAS (tRCD)␊
469␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
470␊
471␉// RAS Active to precharge (tRAS)␊
472␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
473␊
474␉// RAS Precharge (tRP)␊
475␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
476␊
477␉// Single , Dual or Triple Channels␊
478␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) {␊
479␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
480␉} else if (mc_control == 7) {␊
481␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊
482␉} else ␉{␊
483␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
484␉}␊
485}␊
486␊
487static struct mem_controller_t dram_controllers[] = {␊
488␊
489␉// Default unknown chipset␊
490␉{ 0, 0, "",␉NULL, NULL, NULL },␊
491␊
492␉// Intel␊
493//␉{ 0x8086, 0x0100, "2rd Gen Core processor",␉NULL, NULL, NULL },␊
494//␉{ 0x8086, 0x0104, "2rd Gen Core processor",␉NULL, NULL, NULL },␊
495//␉{ 0x8086, 0x010C, "Xeon E3-1200/2rd Gen Core processor",␉NULL, NULL, NULL },␊
496//␉{ 0x8086, 0x0150, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊
497//␉{ 0x8086, 0x0154, "3rd Gen Core processor",␉NULL, NULL, NULL },␊
498//␉{ 0x8086, 0x0158, "Xeon E3-1200 v2/Ivy Bridge",␉NULL, NULL, NULL },␊
499//␉{ 0x8086, 0x015C, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊
500␊
501//␉{ 0x8086, 0x0BF0, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
502//␉{ 0x8086, 0x0BF1, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
503//␉{ 0x8086, 0x0BF2, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
504//␉{ 0x8086, 0x0BF3, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
505//␉{ 0x8086, 0x0BF4, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
506//␉{ 0x8086, 0x0BF5, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
507//␉{ 0x8086, 0x0BF6, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
508//␉{ 0x8086, 0x0BF7, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
509␊
510//␉{ 0x8086, 0x0C00, "Haswell",␉NULL, NULL, NULL },␊
511//␉{ 0x8086, 0x0C04, "Haswell",␉NULL, NULL, NULL },␊
512//␉{ 0x8086, 0x0C08, "Haswell",␉NULL, NULL, NULL },␊
513␊
514␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
515␊
516␉{ 0x8086, 0x1A30, "82845 845 [Brookdale]",␉NULL, NULL, NULL },␊
517␉␊
518␉{ 0x8086, 0x2970, "82946GZ/PL/GL",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
519␉{ 0x8086, 0x2990, "82Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
520␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
521␊
522␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
523␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
524␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
525␊
526␉{ 0x8086, 0x29B0, "82Q35 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
527␉{ 0x8086, 0x29C0, "82G33/G31/P35/P31",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
528␉{ 0x8086, 0x29D0, "82Q33 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
529␉{ 0x8086, 0x29E0, "82X38/X48 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
530␉{ 0x8086, 0x29F0, "3200/3210",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
531␊
532␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
533␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
534␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
535␉{ 0x8086, 0x2E30, "G41",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
536//␉{ 0x8086, 0x2E40, "4 Series Chipset",␉␉NULL, NULL, NULL },␊
537//␉{ 0x8086, 0x2E90, "4 Series Chipset",␉␉NULL, NULL, NULL },␊
538␊
539␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
540␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
541␉{ 0x8086, 0x3400, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
542␉{ 0x8086, 0x3401, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
543␉{ 0x8086, 0x3402, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
544␉{ 0x8086, 0x3403, "5500",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
545␉{ 0x8086, 0x3404, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
546␉{ 0x8086, 0x3405, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
547␉{ 0x8086, 0x3406, "5520",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
548␉{ 0x8086, 0x3407, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
549};␊
550␊
551static const char *memory_channel_types[] =␊
552{␊
553␉"Unknown", "Single", "Dual", "Triple"␊
554};␊
555␊
556void scan_dram_controller(pci_dt_t *dram_dev)␊
557{␊
558␉int i;␊
559␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) {␊
560␉␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) && (dram_controllers[i].device == dram_dev->device_id)) {␊
561␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
562␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel Corporation " : "" ,␊
563␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊
564␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊
565␊
566␉␉␉if (dram_controllers[i].initialise != NULL) {␊
567␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
568␉␉␉}␊
569␊
570␉␉␉if (dram_controllers[i].poll_timings != NULL) {␊
571␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
572␉␉␉}␊
573␊
574␉␉␉if (dram_controllers[i].poll_speed != NULL) {␊
575␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
576␉␉␉}␊
577␊
578␉␉␉verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊
579␉␉␉␉(uint32_t)Platform.RAM.Frequency / 1000000,␊
580␉␉␉␉(uint32_t)Platform.RAM.Frequency / 500000,␊
581␉␉␉␉memory_channel_types[Platform.RAM.Channels]␊
582␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
583␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS);␊
584//␉␉␉getchar();␊
585␉␉}␊
586␉}␊
587}␊
588

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