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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␊
20#endif␊
21␊
22␊
23boolean_t ForceAmdCpu = false;␊
24␊
25/* For AMD CPU's */␊
26boolean_t IsAmdCPU(void)␊
27{␊
28␉if (ForceAmdCpu)␊
29␉{␊
30␉␉return true;␊
31␉}␊
32␊
33␉uint32_t ourcpuid[4];␊
34␉do_cpuid(0, ourcpuid);␊
35␉if (␊
36␉␉/* This spells out "AuthenticAMD". */␊
37␉␉ourcpuid[ebx] == 0x68747541 && // Auth␊
38␉␉ourcpuid[ecx] == 0x444D4163 && // cAMD␊
39␉␉ourcpuid[edx] == 0x69746E65) // enti␊
40␉{␊
41␉␉return true;␊
42␉}␊
43␊
44␉return false;␊
45};␊
46␊
47/* For Intel CPU's */␊
48boolean_t IsIntelCPU(void)␊
49{␊
50␉uint32_t ourcpuid[4];␊
51␉do_cpuid(0, ourcpuid);␊
52␉if (␊
53␉␉/* This spells out "GenuineIntel". */␊
54␉␉ourcpuid[ebx] == 0x756E6547 && // Genu␊
55␉␉ourcpuid[ecx] == 0x6C65746E && // ntel␊
56␉␉ourcpuid[edx] == 0x49656E69) // ineI␊
57␉{␊
58␉␉return true;␊
59␉}␊
60␊
61␉if (!IsAmdCPU())␊
62␉{␊
63␉␉return true;␊
64␉}␊
65␊
66␉return false;␊
67}␊
68␊
69#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
70␊
71clock_frequency_info_t gPEClockFrequencyInfo;␊
72␊
73static inline uint32_t __unused clockspeed_rdtsc(void)␊
74{␊
75␉uint32_t out;␊
76␉__asm__ volatile (␊
77 "rdtsc\n"␊
78 "shl $32,%%edx\n"␊
79 "or %%edx,%%eax\n"␊
80 : "=a" (out)␊
81 :␊
82 : "%edx"␊
83 );␊
84␉return out;␊
85}␊
86␊
87/*␊
88 * timeRDTSC()␊
89 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
90 * It pauses until the value is latched in the counter␊
91 * and then reads the time stamp counter to return to the caller.␊
92 */␊
93static uint64_t timeRDTSC(void)␊
94{␊
95␉int␉␉attempts = 0;␊
96␉uint64_t ␉latchTime;␊
97␉uint64_t␉saveTime,intermediate;␊
98␉unsigned int␉timerValue, lastValue;␊
99␉//boolean_t␉int_enabled;␊
100␉/*␊
101␉ * Table of correction factors to account for␊
102␉ *␉ - timer counter quantization errors, and␊
103␉ *␉ - undercounts 0..5␊
104␉ */␊
105#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
106#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
107#define SAMPLE_NSECS␉␉(2000000000LL)␊
108#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
109#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
110␉uint64_t␉scale[6] = {␊
111␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
112␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
113␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
114␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
115␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
116␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
117␉};␊
118␊
119␉//int_enabled = ml_set_interrupts_enabled(false);␊
120␊
121restart:␊
122␉if (attempts >= 3) // increase to up to 9 attempts.␊
123␉{␊
124␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
125␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
126␉}␊
127␉attempts++;␊
128␉enable_PIT2();␉␉// turn on PIT2␊
129␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
130␉latchTime = rdtsc64();␉// get the time stamp to time␊
131␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
132␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
133␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
134␉get_PIT2(&lastValue);␊
135␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
136␉do {␊
137␉␉intermediate = get_PIT2(&timerValue);␊
138␉␉if (timerValue > lastValue)␊
139␉␉{␊
140␉␉␉// Timer wrapped␊
141␉␉␉set_PIT2(0);␊
142␉␉␉disable_PIT2();␊
143␉␉␉goto restart;␊
144␉␉}␊
145␉␉lastValue = timerValue;␊
146␉} while (timerValue > 5);␊
147␉//printf("timerValue␉ %d\n",timerValue);␊
148␉//printf("intermediate 0x%016llX\n",intermediate);␊
149␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
150 ␊
151␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
152␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
153␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
154␉intermediate += latchTime;␉␉// add on our save fudge␊
155␊
156␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
157␉disable_PIT2();␉␉␉// turn off PIT 2␊
158␊
159␉//ml_set_interrupts_enabled(int_enabled);␊
160␉return intermediate;␊
161}␊
162␊
163/*␊
164 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
165 */␊
166static uint64_t __unused measure_tsc_frequency(void)␊
167{␊
168␉uint64_t tscStart;␊
169␉uint64_t tscEnd;␊
170␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
171␉unsigned long pollCount;␊
172␉uint64_t retval = 0;␊
173␉int i;␊
174␊
175␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
176␉ * counter 2. We run this loop 3 times to make sure the cache␊
177␉ * is hot and we take the minimum delta from all of the runs.␊
178␉ * That is to say that we're biased towards measuring the minimum␊
179␉ * number of TSC ticks that occur while waiting for the timer to␊
180␉ * expire. That theoretically helps avoid inconsistencies when␊
181␉ * running under a VM if the TSC is not virtualized and the host␊
182␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
183␉ */␊
184␉for(i = 0; i < 10; ++i)␊
185␉{␊
186␉␉enable_PIT2();␊
187␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
188␉␉tscStart = rdtsc64();␊
189␉␉pollCount = poll_PIT2_gate();␊
190␉␉tscEnd = rdtsc64();␊
191␉␉/* The poll loop must have run at least a few times for accuracy */␊
192␉␉if (pollCount <= 1)␊
193␉␉{␊
194␉␉␉continue;␊
195␉␉}␊
196␉␉/* The TSC must increment at LEAST once every millisecond.␊
197␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
198␉␉ * be >= 30. Anything less and the processor is way too slow.␊
199␉␉ */␊
200␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
201␉␉{␊
202␉␉␉continue;␊
203␉␉}␊
204␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
205␉␉if ( (tscEnd - tscStart) < tscDelta )␊
206␉␉{␊
207␉␉␉tscDelta = tscEnd - tscStart;␊
208␉␉}␊
209␉}␊
210␉/* tscDelta is now the least number of TSC ticks the processor made in␊
211␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
212␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
213␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
214␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
215␉ * dividing by the milliseconds, we simply multiply by 1000.␊
216␉ */␊
217␊
218␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
219␉ * that we're going to multiply by 1000 first so we do need at least some␊
220␉ * arithmetic headroom. For now, 32-bit should be enough.␊
221␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
222␉ */␊
223␉if (tscDelta > (1ULL<<32))␊
224␉{␊
225␉␉retval = 0;␊
226␉}␊
227␉else␊
228␉{␊
229␉␉retval = tscDelta * 1000 / 30;␊
230␉}␊
231␉disable_PIT2();␊
232␉return retval;␊
233}␊
234␊
235static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
236#define RTC_FAST_DENOM␉0xFFFFFFFF␊
237␊
238inline static uint32_t␊
239create_mul_quant_GHZ(int shift, uint32_t quant)␊
240{␊
241␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
242}␊
243␊
244struct␉{␊
245␉mach_timespec_t␉␉␉calend_offset;␊
246␉boolean_t␉␉␉calend_is_set;␊
247␊
248␉int64_t␉␉␉␉calend_adjtotal;␊
249␉int32_t␉␉␉␉calend_adjdelta;␊
250␊
251␉uint32_t␉␉␉boottime;␊
252␊
253␉mach_timebase_info_data_t␉timebase_const;␊
254␊
255␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
256} rtclock;␊
257␊
258uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
259uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
260uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
261uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
262//uint64_t cpuFreq;␊
263␊
264static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
265{␊
266␊
267␉if (cycles > (NSEC_PER_SEC/20))␊
268␉{␊
269␉␉// we can use just a "fast" multiply to get nanos␊
270␉␉rtc_quant_shift = 32;␊
271␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
272␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
273␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
274␉}␊
275␉else␊
276␉{␊
277␉␉rtc_quant_shift = 26;␊
278␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
279␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
280␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
281␉}␊
282␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
283␉// BUT we also want to calculate...␊
284␊
285␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
286 / UI_CPUFREQ_ROUNDING_FACTOR)␊
287␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
288␊
289␉/*␊
290␉ * Set current measured speed.␊
291␉ */␊
292␉if (cycles >= 0x100000000ULL)␊
293␉{␊
294␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
295␉}␊
296␉else␊
297␉{␊
298␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
299␉}␊
300␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
301␊
302␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
303␉return(rtc_cyc_per_sec);␊
304}␊
305␊
306/*␊
307 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
308 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
309 *␉ a max multi. (used to calculate the FSB freq.),␊
310 *␉ and a current multi. (used to calculate the CPU freq.)␊
311 * - busFrequency = tscFrequency / multi␊
312 * - cpuFrequency = busFrequency * multi␊
313 */␊
314␊
315/* Decimal powers: */␊
316#define kilo (1000ULL)␊
317#define Mega (kilo * kilo)␊
318#define Giga (kilo * Mega)␊
319#define Tera (kilo * Giga)␊
320#define Peta (kilo * Tera)␊
321␊
322#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
323␊
324void scan_cpu(PlatformInfo_t *p)␊
325{␊
326␉uint64_t␉busFCvtt2n;␊
327␉uint64_t␉tscFCvtt2n;␊
328␉uint64_t␉tscFreq␉␉␉= 0;␊
329␉uint64_t␉busFrequency␉␉= 0;␊
330␉uint64_t␉cpuFrequency␉␉= 0;␊
331␉uint64_t␉msr␉␉␉= 0;␊
332␉uint64_t␉flex_ratio␉␉= 0;␊
333␉uint64_t␉cpuid_features;␊
334␊
335␉uint32_t␉max_ratio␉␉= 0;␊
336␉uint32_t␉min_ratio␉␉= 0;␊
337␉uint32_t␉reg[4];␊
338␉uint32_t␉cores_per_package␉= 0;␊
339␉uint32_t␉logical_per_package␉= 1;␊
340␉uint32_t␉threads_per_core␉= 1;␊
341␊
342␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
343␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
344␉uint8_t␉␉currdiv␉␉␉= 0;␊
345␉uint8_t␉␉currcoef␉␉= 0;␊
346␉uint8_t␉␉maxdiv␉␉␉= 0;␊
347␉uint8_t␉␉maxcoef␉␉␉= 0;␊
348␉uint8_t␉␉cpuMultN2␉␉= 0;␊
349␊
350␉const char␉*newratio;␊
351␉char␉␉str[128];␊
352␉char␉␉*s␉␉␉= 0;␊
353␊
354␉int␉␉len␉␉␉= 0;␊
355␉int␉␉myfsb␉␉␉= 0;␊
356␉int␉␉i␉␉␉= 0;␊
357␊
358␉if(IsIntelCPU())␊
359␉{␊
360␊
361␉␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
362␊
363␉␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
364␊
365␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
366␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
367␉␉{␊
368␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
369␉␉␉{␊
370␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
371␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
372␉␉␉␉{␊
373␉␉␉␉␉break;␊
374␉␉␉␉}␊
375␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
376␉␉␉}␊
377␉ }␊
378␊
379␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
380␊
381␉␉if (i > 0)␊
382␉␉{␊
383␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
384␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
385␉␉}␊
386␊
387␉␉if (cores_per_package == 0)␊
388␉␉{␊
389␉␉␉cores_per_package = 1;␊
390␉␉}␊
391␊
392␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
393␉␉{␊
394␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
395␉␉}␊
396␊
397␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
398␉␉{␊
399␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
400␉␉}␊
401␊
402␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
403␊
404␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
405␉␉{␊
406␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
407␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
408␉␉}␊
409␉␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
410␉␉{␊
411␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
412␉␉}␊
413␉}␊
414␉else if(IsAmdCPU())␊
415␉{␊
416␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
417␊
418␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
419␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
420␉␉{␊
421␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
422␉␉}␊
423␊
424␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
425␉␉{␊
426␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
427␉␉}␊
428␊
429␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
430␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
431␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
432␊
433␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
434␉␉threads_per_core = cores_per_package;␊
435␊
436␉␉if (cores_per_package == 0)␊
437␉␉{␊
438␉␉␉cores_per_package = 1;␊
439␉␉}␊
440␊
441␉␉p->CPU.NoThreads␉= logical_per_package;␊
442␉␉p->CPU.NoCores␉␉= cores_per_package;␊
443␊
444␉␉if (p->CPU.NoCores == 0)␊
445␉␉{␊
446␉␉␉p->CPU.NoCores = 1;␊
447␉␉␉p->CPU.NoThreads␉= 1;␊
448␉␉}␊
449␉}␊
450␉else␊
451␉{␊
452␉␉stop("Unsupported CPU detected! System halted.");␊
453␉}␊
454␊
455/* http://www.flounder.com/cpuid_explorer2.htm␊
456 EAX (Intel):␊
457 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
458 +--------+----------------+--------+----+----+--------+--------+--------+␊
459 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
460 +--------+----------------+--------+----+----+--------+--------+--------+␊
461␊
462 EAX (AMD):␊
463 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
464 +--------+----------------+--------+----+----+--------+--------+--------+␊
465 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
466 +--------+----------------+--------+----+----+--------+--------+--------+␊
467*/␊
468␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
469␊
470␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx],p->CPU.CPUID[CPUID_1][edx]);␊
471␉if (bit(28) & cpuid_features) // HTT/Multicore␊
472␉{␊
473␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
474␉}␊
475␉else␊
476␉{␊
477␉␉logical_per_package = 1;␊
478␉}␊
479␊
480␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
481␊
482␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
483␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
484␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
485␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
486␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
487␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
488␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
489␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
490␊
491␉if (p->CPU.Family == 0x0f)␊
492␉{␊
493␉␉p->CPU.Family += p->CPU.ExtFamily;␊
494␉}␊
495␊
496␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
497␉{␊
498␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
499␉}␊
500␊
501␉/* get BrandString (if supported) */␊
502␉/* Copyright: from Apple's XNU cpuid.c */␊
503␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
504␉{␊
505␉␉bzero(str, 128);␊
506␉␉/*␊
507␉␉ * The BrandString 48 bytes (max), guaranteed to␊
508␉␉ * be NULL terminated.␊
509␉␉ */␊
510␉␉do_cpuid(0x80000002, reg);␊
511␉␉memcpy(&str[0], (char *)reg, 16);␊
512␉␉do_cpuid(0x80000003, reg);␊
513␉␉memcpy(&str[16], (char *)reg, 16);␊
514␉␉do_cpuid(0x80000004, reg);␊
515␉␉memcpy(&str[32], (char *)reg, 16);␊
516␉␉for (s = str; *s != '\0'; s++)␊
517␉␉{␊
518␉␉␉if (*s != ' ')␊
519␉␉␉{␊
520␉␉␉␉break;␊
521␉␉␉}␊
522␉␉}␊
523␉␉strlcpy(p->CPU.BrandString, s, 48);␊
524␊
525␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
526␉␉{␊
527␉␉␉/*␊
528␉␉␉ * This string means we have a firmware-programmable brand string,␊
529␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
530␉␉␉ */␊
531␉␉␉p->CPU.BrandString[0] = '\0';␊
532␉␉}␊
533␉␉p->CPU.BrandString[47] = '\0';␊
534//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
535␉}␊
536␊
537␉/*␊
538␉ * Find the number of enabled cores and threads␊
539␉ * (which determines whether SMT/Hyperthreading is active).␊
540␉ */␊
541␊
542␉if(IsIntelCPU())␊
543␉{␊
544␉␉switch (p->CPU.Model)␊
545␉␉{␊
546␉␉␉case CPUID_MODEL_NEHALEM:␊
547␉␉␉case CPUID_MODEL_FIELDS:␊
548␉␉␉case CPUID_MODEL_DALES:␊
549␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
550␉␉␉case CPUID_MODEL_JAKETOWN:␊
551␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
552␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
553␊
554␉␉␉case CPUID_MODEL_HASWELL:␊
555␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
556␉␉␉//case CPUID_MODEL_HASWELL_H:␊
557␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
558␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
559␉␉␉//case CPUID_MODEL_:␊
560␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
561␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
562␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
563␉␉␉␉break;␊
564␊
565␉␉␉case CPUID_MODEL_DALES_32NM:␊
566␉␉␉case CPUID_MODEL_WESTMERE:␊
567␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
568␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
569␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
570␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
571␉␉␉␉break;␊
572␉␉}␊
573␊
574␉␉if (p->CPU.NoCores == 0)␊
575␉␉{␊
576␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
577␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
578␉␉}␊
579␊
580␉␉// MSR is *NOT* available on the Intel Atom CPU␊
581␉␉//workaround for N270. I don't know why it detected wrong␊
582␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
583␉␉{␊
584␉␉␉p->CPU.NoCores␉␉= 1;␊
585␉␉␉p->CPU.NoThreads␉= 2;␊
586␉␉}␊
587␊
588␉␉//workaround for Quad␊
589␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
590␉␉{␊
591␉␉␉p->CPU.NoCores␉␉= 4;␊
592␉␉␉p->CPU.NoThreads␉= 4;␊
593␉␉}␊
594␉}␊
595␊
596␉/* setup features */␊
597␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
598␉{␊
599␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
600␉}␊
601␊
602␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
603␉{␊
604␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
605␉}␊
606␊
607␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
608␉{␊
609␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
610␉}␊
611␊
612␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
613␉{␊
614␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
615␉}␊
616␊
617␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
618␉{␊
619␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
620␉}␊
621␊
622␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
623␉{␊
624␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
625␉}␊
626␊
627␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
628␉{␊
629␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
630␉}␊
631␊
632␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
633␉{␊
634␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
635␉}␊
636␊
637␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
638␉{␊
639␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
640␉}␊
641␊
642␉uint64_t cycles;␊
643␉cycles = timeRDTSC();␊
644␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
645␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
646␉// if usual method failed␊
647␉if ( tscFreq < 1000 )␉//TEST␊
648␉{␊
649␉␉tscFreq = timeRDTSC() * 20;//measure_tsc_frequency();␊
650␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
651␉}␊
652␊
653␉if (IsIntelCPU() && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
654␉{␊
655␉␉int intelCPU = p->CPU.Model;␊
656␉␉if (p->CPU.Family == 0x06)␊
657␉␉{␊
658␉␉␉/* Nehalem CPU model */␊
659␉␉␉switch (p->CPU.Model)␊
660␉␉␉{␊
661␉␉␉␉case CPUID_MODEL_NEHALEM:␊
662␉␉␉␉case CPUID_MODEL_FIELDS:␊
663␉␉␉␉case CPUID_MODEL_DALES:␊
664␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
665␉␉␉␉case CPUID_MODEL_WESTMERE:␊
666␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
667␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
668/* --------------------------------------------------------- */␊
669␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
670␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
671␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
672␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
673␉␉␉␉case CPUID_MODEL_HASWELL:␊
674␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
675␊
676␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
677␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
678/* --------------------------------------------------------- */␊
679␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
680␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
681␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
682␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
683␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
684␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
685␉␉␉␉␉if (bitfield(msr, 16, 16))␊
686␉␉␉␉␉{␊
687␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
688␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
689␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
690␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
691␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
692␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
693␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
694␉␉␉␉␉␉// is inadvertently set to 0.␊
695␊
696␉␉␉␉␉␉if (flex_ratio == 0)␊
697␉␉␉␉␉␉{␊
698␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
699␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
700␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
701␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
702␉␉␉␉␉␉}␊
703␉␉␉␉␉␉else␊
704␉␉␉␉␉␉{␊
705␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
706␉␉␉␉␉␉␉{␊
707␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
708␉␉␉␉␉␉␉}␊
709␉␉␉␉␉␉}␊
710␉␉␉␉␉}␊
711␊
712␉␉␉␉␉if (bus_ratio_max)␊
713␉␉␉␉␉{␊
714␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
715␉␉␉␉␉}␊
716␊
717␉␉␉␉␉//valv: Turbo Ratio Limit␊
718␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
719␉␉␉␉␉{␊
720␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
721␊
722␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
723␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
724␉␉␉␉␉}␊
725␉␉␉␉␉else␊
726␉␉␉␉␉{␊
727␉␉␉␉␉␉cpuFrequency = tscFreq;␊
728␉␉␉␉␉}␊
729␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
730␉␉␉␉␉{␊
731␉␉␉␉␉␉max_ratio = atoi(newratio);␊
732␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
733␉␉␉␉␉␉if (len >= 3)␊
734␉␉␉␉␉␉{␊
735␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
736␉␉␉␉␉␉}␊
737␊
738␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
739␊
740␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
741␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
742␉␉␉␉␉␉{␊
743␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
744␉␉␉␉␉␉␉if (len >= 3)␊
745␉␉␉␉␉␉␉{␊
746␉␉␉␉␉␉␉␉maxdiv = 1;␊
747␉␉␉␉␉␉␉}␊
748␉␉␉␉␉␉␉else␊
749␉␉␉␉␉␉␉{␊
750␉␉␉␉␉␉␉␉maxdiv = 0;␊
751␉␉␉␉␉␉␉}␊
752␉␉␉␉␉␉}␊
753␉␉␉␉␉␉else␊
754␉␉␉␉␉␉{␊
755␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
756␉␉␉␉␉␉}␊
757␉␉␉␉␉}␊
758␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
759␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
760␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
761␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
762␊
763␉␉␉␉myfsb = busFrequency / 1000000;␊
764␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
765␉␉␉␉currcoef = bus_ratio_max;␊
766␊
767␉␉␉␉break;␊
768␊
769␉␉␉default:␊
770␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
771␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
772␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
773␉␉␉␉// Non-integer bus ratio for the max-multi␊
774␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
775␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
776␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
777␊
778␉␉␉␉// This will always be model >= 3␊
779␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
780␉␉␉␉{␊
781␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
782␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
783␉␉␉␉}␊
784␉␉␉␉else␊
785␉␉␉␉{␊
786␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
787␉␉␉␉␉// XXX␊
788␉␉␉␉␉maxcoef = currcoef;␊
789␉␉␉␉}␊
790␊
791␉␉␉␉if (!currcoef)␊
792␉␉␉␉{␊
793␉␉␉␉␉currcoef = maxcoef;␊
794␉␉␉␉}␊
795␊
796␉␉␉␉if (maxcoef)␊
797␉␉␉␉{␊
798␉␉␉␉␉if (maxdiv)␊
799␉␉␉␉␉{␊
800␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
801␉␉␉␉␉}␊
802␉␉␉␉␉else␊
803␉␉␉␉␉{␊
804␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
805␉␉␉␉␉}␊
806␊
807␉␉␉␉␉if (currdiv)␊
808␉␉␉␉␉{␊
809␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
810␉␉␉␉␉}␊
811␉␉␉␉␉else␊
812␉␉␉␉␉{␊
813␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
814␉␉␉␉␉}␊
815␊
816␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
817␉␉␉␉}␊
818␉␉␉␉break;␊
819␉␉␉}␊
820␉␉}␊
821␉␉// Mobile CPU␊
822␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
823␉␉{␊
824␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
825␉␉}␊
826␉}␊
827␊
828␉else if (IsAmdCPU())␊
829␉{␊
830␉␉switch(p->CPU.Family)␊
831␉␉{␊
832␉␉␉case 0xF: /* K8 */␊
833␉␉␉{␊
834␉␉␉␉uint64_t fidvid = 0;␊
835␉␉␉␉uint64_t cpuMult;␊
836␉␉␉␉uint64_t fid;␊
837␊
838␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
839␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
840␊
841␉␉␉␉cpuMult = (fid + 8) / 2;␊
842␉␉␉␉currcoef = cpuMult;␊
843␊
844␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
845␉␉␉␉currdiv = cpuMultN2;␊
846␉␉␉␉/****** Addon END ******/␊
847␉␉␉}␊
848␉␉␉␉break;␊
849␊
850␉␉␉case 0x10: /*** AMD Family 10h ***/␊
851␉␉␉{␊
852␉␉␉␉uint64_t cofvid = 0;␊
853␉␉␉␉uint64_t cpuMult;␊
854␉␉␉␉uint64_t divisor = 0;␊
855␉␉␉␉uint64_t did;␊
856␉␉␉␉uint64_t fid;␊
857␊
858␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
859␉␉␉␉did = bitfield(cofvid, 8, 6);␊
860␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
861␉␉␉␉if (did == 0) divisor = 2;␊
862␉␉␉␉else if (did == 1) divisor = 4;␊
863␉␉␉␉else if (did == 2) divisor = 8;␊
864␉␉␉␉else if (did == 3) divisor = 16;␊
865␉␉␉␉else if (did == 4) divisor = 32;␊
866␊
867␉␉␉␉cpuMult = (fid + 16) / divisor;␊
868␉␉␉␉currcoef = cpuMult;␊
869␊
870␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
871␉␉␉␉currdiv = cpuMultN2;␊
872␊
873␉␉␉␉/****** Addon END ******/␊
874␉␉␉}␊
875␉␉␉break;␊
876␊
877␉␉␉case 0x11: /*** AMD Family 11h ***/␊
878␉␉␉{␊
879␉␉␉␉uint64_t cofvid = 0;␊
880␉␉␉␉uint64_t cpuMult;␊
881␉␉␉␉uint64_t divisor = 0;␊
882␉␉␉␉uint64_t did;␊
883␉␉␉␉uint64_t fid;␊
884␊
885␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
886␉␉␉␉did = bitfield(cofvid, 8, 6);␊
887␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
888␉␉␉␉if (did == 0) divisor = 2;␊
889␉␉␉␉else if (did == 1) divisor = 4;␊
890␉␉␉␉else if (did == 2) divisor = 8;␊
891␉␉␉␉else if (did == 3) divisor = 16;␊
892␉␉␉␉else if (did == 4) divisor = 32;␊
893␊
894␉␉␉␉cpuMult = (fid + 8) / divisor;␊
895␉␉␉␉currcoef = cpuMult;␊
896␊
897␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
898␉␉␉␉currdiv = cpuMultN2;␊
899␊
900␉␉␉␉/****** Addon END ******/␊
901␉␉␉}␊
902 break;␊
903␊
904␉␉␉case 0x12: /*** AMD Family 12h ***/␊
905␉␉␉{␊
906␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
907␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
908␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
909␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
910␊
911␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
912␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
913␉␉␉␉uint64_t divisor;␊
914␉␉␉␉switch (CpuDid)␊
915␉␉␉␉{␊
916␉␉␉␉␉case 0: divisor = 1; break;␊
917␉␉␉␉␉case 1: divisor = (3/2); break;␊
918␉␉␉␉␉case 2: divisor = 2; break;␊
919␉␉␉␉␉case 3: divisor = 3; break;␊
920␉␉␉␉␉case 4: divisor = 4; break;␊
921␉␉␉␉␉case 5: divisor = 6; break;␊
922␉␉␉␉␉case 6: divisor = 8; break;␊
923␉␉␉␉␉case 7: divisor = 12; break;␊
924␉␉␉␉␉case 8: divisor = 16; break;␊
925␉␉␉␉␉default: divisor = 1; break;␊
926␉␉␉␉}␊
927␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
928␊
929␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
930␉␉␉␉currdiv = cpuMultN2;␊
931␊
932␉␉␉}␊
933␉␉␉␉break;␊
934␊
935␉␉␉case 0x14: /* K14 */␊
936␊
937␉␉␉{␊
938␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
939␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
940␉␉␉␉uint64_t prfsts;␊
941␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
942␊
943␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
944␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
945␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
946␊
947␉␉␉␉uint64_t frequencyId = 0x10;␊
948␉␉␉␉currcoef = (frequencyId + 0x10) /␊
949␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
950␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
951␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
952␊
953␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
954␉␉␉␉currdiv = cpuMultN2;␊
955␉␉␉}␊
956␊
957␉␉␉␉break;␊
958␊
959␉␉␉case 0x15: /*** AMD Family 15h ***/␊
960␉␉␉case 0x06: /*** AMD Family 06h ***/␊
961␉␉␉{␊
962␊
963␉␉␉␉uint64_t cofvid = 0;␊
964␉␉␉␉uint64_t cpuMult;␊
965␉␉␉␉uint64_t divisor = 0;␊
966␉␉␉␉uint64_t did;␊
967␉␉␉␉uint64_t fid;␊
968␊
969␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
970␉␉␉␉did = bitfield(cofvid, 8, 6);␊
971␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
972␉␉␉␉if (did == 0) divisor = 2;␊
973␉␉␉␉else if (did == 1) divisor = 4;␊
974␉␉␉␉else if (did == 2) divisor = 8;␊
975␉␉␉␉else if (did == 3) divisor = 16;␊
976␉␉␉␉else if (did == 4) divisor = 32;␊
977␊
978␉␉␉␉cpuMult = (fid + 16) / divisor;␊
979␉␉␉␉currcoef = cpuMult;␊
980␊
981␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
982␉␉␉␉currdiv = cpuMultN2;␊
983␉␉␉}␊
984␉␉␉␉break;␊
985␊
986␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
987␉␉␉{␊
988␉␉␉␉uint64_t cofvid = 0;␊
989␉␉␉␉uint64_t cpuMult;␊
990␉␉␉␉uint64_t divisor = 0;␊
991␉␉␉␉uint64_t did;␊
992␉␉␉␉uint64_t fid;␊
993␊
994␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
995␉␉␉␉did = bitfield(cofvid, 8, 6);␊
996␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
997␉␉␉␉if (did == 0) divisor = 1;␊
998␉␉␉␉else if (did == 1) divisor = 2;␊
999␉␉␉␉else if (did == 2) divisor = 4;␊
1000␉␉␉␉else if (did == 3) divisor = 8;␊
1001␉␉␉␉else if (did == 4) divisor = 16;␊
1002␊
1003␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1004␉␉␉␉currcoef = cpuMult;␊
1005␊
1006␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1007␉␉␉␉currdiv = cpuMultN2;␊
1008␉␉␉␉/****** Addon END ******/␊
1009␉␉␉}␊
1010␉␉␉␉break;␊
1011␊
1012␉␉␉default:␊
1013␉␉␉{␊
1014␉␉␉␉typedef unsigned long long vlong;␊
1015␉␉␉␉uint64_t prfsts;␊
1016␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1017␉␉␉␉uint64_t r;␊
1018␉␉␉␉vlong hz;␊
1019␉␉␉␉r = (prfsts>>6) & 0x07;␊
1020␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
1021␊
1022␉␉␉␉currcoef = hz / (200 * Mega);␊
1023␉␉␉}␊
1024␉␉}␊
1025␊
1026␉␉if (currcoef)␊
1027␉␉{␊
1028␉␉␉if (currdiv)␊
1029␉␉␉{␊
1030␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
1031␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1032␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
1033␉␉␉␉//cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);//((1 * Giga) << 32) / tscFCvtt2n;␊
1034␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1035␊
1036␉␉␉␉//cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
1037␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
1038␉␉␉}␊
1039␉␉␉else␊
1040␉␉␉{␊
1041␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1042␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1043␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1044␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1045␉␉␉␉DBG("%d\n", currcoef);␊
1046␉␉␉}␊
1047␉␉}␊
1048␉␉else if (!cpuFrequency)␊
1049␉␉{␊
1050␉␉␉cpuFrequency = tscFreq;␊
1051␉␉}␊
1052␉}␊
1053␊
1054#if 0␊
1055␉if (!busFrequency)␊
1056␉{␊
1057␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1058␉␉DBG("CPU: busFrequency = 0! using the default value for FSB!\n");␊
1059␉␉cpuFrequency = tscFreq;␊
1060␉}␊
1061␊
1062␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1063␊
1064#endif␊
1065␊
1066␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1067␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1068␉p->CPU.CurrCoef = currcoef;␊
1069␉p->CPU.CurrDiv = currdiv;␊
1070␉p->CPU.TSCFrequency = tscFreq;␊
1071␉p->CPU.FSBFrequency = busFrequency;␊
1072␉p->CPU.CPUFrequency = cpuFrequency;␊
1073␊
1074␉// keep formatted with spaces instead of tabs␊
1075␉DBG("\n------------------------------\n");␊
1076 ␉DBG("\tCPU INFO\n");␊
1077␉DBG("------------------------------\n");␊
1078␊
1079␉DBG("CPUID Raw Values:\n");␊
1080␉for (i = 0; i < CPUID_MAX; i++)␊
1081␉{␊
1082␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1083␉}␊
1084␉DBG("\n");␊
1085␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1086␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1087␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1088␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊
1089␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1090␉/*switch (p->CPU.Type) {␊
1091␉␉case PT_OEM:␊
1092␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
1093␉␉␉break;␊
1094␉␉case PT_OD:␊
1095␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
1096␉␉␉break;␊
1097␉␉case PT_DUAL:␊
1098␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
1099␉␉␉break;␊
1100␉␉case PT_RES:␊
1101␉␉␉DBG("Processor type: Intel Reserved\n");␊
1102␉␉␉break;␊
1103␉␉default:␊
1104␉␉␉break;␊
1105␉}*/␊
1106␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1107␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊
1108␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1109␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1110␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1111␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1112␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1113␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
1114␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
1115␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
1116␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1117␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1118␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
1119␊
1120␉DBG("\n---------------------------------------------\n");␊
1121#if DEBUG_CPU␊
1122␉pause();␊
1123#endif␊
1124}␊
1125

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