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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␊
20#endif␊
21␊
22␊
23#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
24␊
25clock_frequency_info_t gPEClockFrequencyInfo;␊
26␊
27static inline uint32_t __unused clockspeed_rdtsc(void)␊
28{␊
29␉uint32_t out;␊
30␉__asm__ volatile (␊
31 "rdtsc\n"␊
32 "shl $32,%%edx\n"␊
33 "or %%edx,%%eax\n"␊
34 : "=a" (out)␊
35 :␊
36 : "%edx"␊
37 );␊
38␉return out;␊
39}␊
40␊
41/*␊
42 * timeRDTSC()␊
43 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
44 * It pauses until the value is latched in the counter␊
45 * and then reads the time stamp counter to return to the caller.␊
46 */␊
47static uint64_t timeRDTSC(void)␊
48{␊
49␉int␉␉attempts = 0;␊
50␉uint64_t ␉latchTime;␊
51␉uint64_t␉saveTime,intermediate;␊
52␉unsigned int␉timerValue, lastValue;␊
53␉//boolean_t␉int_enabled;␊
54␉/*␊
55␉ * Table of correction factors to account for␊
56␉ *␉ - timer counter quantization errors, and␊
57␉ *␉ - undercounts 0..5␊
58␉ */␊
59#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
60#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
61#define SAMPLE_NSECS␉␉(2000000000LL)␊
62#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
63#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
64␉uint64_t␉scale[6] = {␊
65␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
66␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
67␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
68␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
69␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
70␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
71␉};␊
72␊
73␉//int_enabled = ml_set_interrupts_enabled(false);␊
74␊
75restart:␊
76␉if (attempts >= 3) // increase to up to 9 attempts.␊
77␉{␊
78␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
79␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
80␉}␊
81␉attempts++;␊
82␉enable_PIT2();␉␉// turn on PIT2␊
83␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
84␉latchTime = rdtsc64();␉// get the time stamp to time␊
85␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
86␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
87␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
88␉get_PIT2(&lastValue);␊
89␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
90␉do {␊
91␉␉intermediate = get_PIT2(&timerValue);␊
92␉␉if (timerValue > lastValue)␊
93␉␉{␊
94␉␉␉// Timer wrapped␊
95␉␉␉set_PIT2(0);␊
96␉␉␉disable_PIT2();␊
97␉␉␉goto restart;␊
98␉␉}␊
99␉␉lastValue = timerValue;␊
100␉} while (timerValue > 5);␊
101␉//printf("timerValue␉ %d\n",timerValue);␊
102␉//printf("intermediate 0x%016llX\n",intermediate);␊
103␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
104 ␊
105␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
106␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
107␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
108␉intermediate += latchTime;␉␉// add on our save fudge␊
109␊
110␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
111␉disable_PIT2();␉␉␉// turn off PIT 2␊
112␊
113␉//ml_set_interrupts_enabled(int_enabled);␊
114␉return intermediate;␊
115}␊
116␊
117/*␊
118 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
119 */␊
120static uint64_t __unused measure_tsc_frequency(void)␊
121{␊
122␉uint64_t tscStart;␊
123␉uint64_t tscEnd;␊
124␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
125␉unsigned long pollCount;␊
126␉uint64_t retval = 0;␊
127␉int i;␊
128␊
129␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
130␉ * counter 2. We run this loop 3 times to make sure the cache␊
131␉ * is hot and we take the minimum delta from all of the runs.␊
132␉ * That is to say that we're biased towards measuring the minimum␊
133␉ * number of TSC ticks that occur while waiting for the timer to␊
134␉ * expire. That theoretically helps avoid inconsistencies when␊
135␉ * running under a VM if the TSC is not virtualized and the host␊
136␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
137␉ */␊
138␉for(i = 0; i < 10; ++i)␊
139␉{␊
140␉␉enable_PIT2();␊
141␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
142␉␉tscStart = rdtsc64();␊
143␉␉pollCount = poll_PIT2_gate();␊
144␉␉tscEnd = rdtsc64();␊
145␉␉/* The poll loop must have run at least a few times for accuracy */␊
146␉␉if (pollCount <= 1)␊
147␉␉{␊
148␉␉␉continue;␊
149␉␉}␊
150␉␉/* The TSC must increment at LEAST once every millisecond.␊
151␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
152␉␉ * be >= 30. Anything less and the processor is way too slow.␊
153␉␉ */␊
154␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
155␉␉{␊
156␉␉␉continue;␊
157␉␉}␊
158␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
159␉␉if ( (tscEnd - tscStart) < tscDelta )␊
160␉␉{␊
161␉␉␉tscDelta = tscEnd - tscStart;␊
162␉␉}␊
163␉}␊
164␉/* tscDelta is now the least number of TSC ticks the processor made in␊
165␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
166␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
167␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
168␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
169␉ * dividing by the milliseconds, we simply multiply by 1000.␊
170␉ */␊
171␊
172␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
173␉ * that we're going to multiply by 1000 first so we do need at least some␊
174␉ * arithmetic headroom. For now, 32-bit should be enough.␊
175␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
176␉ */␊
177␉if (tscDelta > (1ULL<<32))␊
178␉{␊
179␉␉retval = 0;␊
180␉}␊
181␉else␊
182␉{␊
183␉␉retval = tscDelta * 1000 / 30;␊
184␉}␊
185␉disable_PIT2();␊
186␉return retval;␊
187}␊
188␊
189static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
190#define RTC_FAST_DENOM␉0xFFFFFFFF␊
191␊
192inline static uint32_t␊
193create_mul_quant_GHZ(int shift, uint32_t quant)␊
194{␊
195␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
196}␊
197␊
198struct␉{␊
199␉mach_timespec_t␉␉␉calend_offset;␊
200␉boolean_t␉␉␉calend_is_set;␊
201␊
202␉int64_t␉␉␉␉calend_adjtotal;␊
203␉int32_t␉␉␉␉calend_adjdelta;␊
204␊
205␉uint32_t␉␉␉boottime;␊
206␊
207␉mach_timebase_info_data_t␉timebase_const;␊
208␊
209␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
210} rtclock;␊
211␊
212uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
213uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
214uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
215uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
216//uint64_t cpuFreq;␊
217␊
218static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
219{␊
220␊
221␉if (cycles > (NSEC_PER_SEC/20))␊
222␉{␊
223␉␉// we can use just a "fast" multiply to get nanos␊
224␉␉rtc_quant_shift = 32;␊
225␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
226␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
227␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
228␉}␊
229␉else␊
230␉{␊
231␉␉rtc_quant_shift = 26;␊
232␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
233␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
234␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
235␉}␊
236␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
237␉// BUT we also want to calculate...␊
238␊
239␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
240 / UI_CPUFREQ_ROUNDING_FACTOR)␊
241␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
242␊
243␉/*␊
244␉ * Set current measured speed.␊
245␉ */␊
246␉if (cycles >= 0x100000000ULL)␊
247␉{␊
248␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
249␉}␊
250␉else␊
251␉{␊
252␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
253␉}␊
254␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
255␊
256␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
257␉return(rtc_cyc_per_sec);␊
258}␊
259␊
260/*␊
261 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
262 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
263 *␉ a max multi. (used to calculate the FSB freq.),␊
264 *␉ and a current multi. (used to calculate the CPU freq.)␊
265 * - busFrequency = tscFrequency / multi␊
266 * - cpuFrequency = busFrequency * multi␊
267 */␊
268␊
269/* Decimal powers: */␊
270#define kilo (1000ULL)␊
271#define Mega (kilo * kilo)␊
272#define Giga (kilo * Mega)␊
273#define Tera (kilo * Giga)␊
274#define Peta (kilo * Tera)␊
275␊
276#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
277␊
278void scan_cpu(PlatformInfo_t *p)␊
279{␊
280//␉scan();␊
281␉uint64_t␉busFCvtt2n;␊
282␉uint64_t␉tscFCvtt2n;␊
283␉uint64_t␉tscFreq␉␉␉= 0;␊
284␉uint64_t␉busFrequency␉␉= 0;␊
285␉uint64_t␉cpuFrequency␉␉= 0;␊
286␉uint64_t␉msr␉␉␉= 0;␊
287␉uint64_t␉flex_ratio␉␉= 0;␊
288␉uint64_t␉cpuid_features;␊
289␊
290␉uint32_t␉max_ratio␉␉= 0;␊
291␉uint32_t␉min_ratio␉␉= 0;␊
292␉uint32_t␉reg[4];␊
293␉uint32_t␉cores_per_package␉= 0;␊
294␉uint32_t␉logical_per_package␉= 1;␊
295␉uint32_t␉threads_per_core␉= 1;␊
296␊
297␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
298␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
299␉uint8_t␉␉currdiv␉␉␉= 0;␊
300␉uint8_t␉␉currcoef␉␉= 0;␊
301␉uint8_t␉␉maxdiv␉␉␉= 0;␊
302␉uint8_t␉␉maxcoef␉␉␉= 0;␊
303␉uint8_t␉␉cpuMultN2␉␉= 0;␊
304␊
305␉const char␉*newratio;␊
306␉char␉␉str[128];␊
307␉char␉␉*s␉␉␉= 0;␊
308␊
309␉int␉␉len␉␉␉= 0;␊
310␉int␉␉myfsb␉␉␉= 0;␊
311␉int␉␉i␉␉␉= 0;␊
312␊
313␊
314/* http://www.flounder.com/cpuid_explorer2.htm␊
315 EAX (Intel):␊
316 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
317 +--------+----------------+--------+----+----+--------+--------+--------+␊
318 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
319 +--------+----------------+--------+----+----+--------+--------+--------+␊
320␊
321 EAX (AMD):␊
322 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
323 +--------+----------------+--------+----+----+--------+--------+--------+␊
324 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
325 +--------+----------------+--------+----+----+--------+--------+--------+␊
326*/␊
327␉///////////////////-- MaxFn,Vendor --////////////////////////␊
328␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
329␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
330␉/////////////////////////////////////////////////////////////␊
331␊
332␉///////////////////-- Signature, stepping, features -- //////␊
333␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
334␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx],p->CPU.CPUID[CPUID_1][edx]);␊
335␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
336␉{␊
337␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
338␉}␊
339␉else␊
340␉{␊
341␉␉logical_per_package = 1;␊
342␉}␊
343//␉printf("logical %d\n",logical_per_package);␊
344␊
345␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
346␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
347␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
348␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
349␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
350␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
351␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
352␊
353␉if (p->CPU.Family == 0x0f)␊
354␉{␊
355␉␉p->CPU.Family += p->CPU.ExtFamily;␊
356␉}␊
357␊
358␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
359␉{␊
360␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
361␉}␊
362␊
363␉/* get BrandString (if supported) */␊
364␉/* Copyright: from Apple's XNU cpuid.c */␊
365␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
366␉{␊
367␉␉bzero(str, 128);␊
368␉␉/*␊
369␉␉ * The BrandString 48 bytes (max), guaranteed to␊
370␉␉ * be NULL terminated.␊
371␉␉ */␊
372␉␉do_cpuid(0x80000002, reg);␊
373␉␉memcpy(&str[0], (char *)reg, 16);␊
374␉␉do_cpuid(0x80000003, reg);␊
375␉␉memcpy(&str[16], (char *)reg, 16);␊
376␉␉do_cpuid(0x80000004, reg);␊
377␉␉memcpy(&str[32], (char *)reg, 16);␊
378␉␉for (s = str; *s != '\0'; s++)␊
379␉␉{␊
380␉␉␉if (*s != ' ')␊
381␉␉␉{␊
382␉␉␉␉break;␊
383␉␉␉}␊
384␉␉}␊
385␉␉strlcpy(p->CPU.BrandString, s, 48);␊
386␊
387␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
388␉␉{␊
389␉␉␉/*␊
390␉␉␉ * This string means we have a firmware-programmable brand string,␊
391␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
392␉␉␉ */␊
393␉␉␉p->CPU.BrandString[0] = '\0';␊
394␉␉}␊
395␉␉p->CPU.BrandString[47] = '\0';␊
396//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
397␉}␊
398␊
399␉//char *vendor = p->CPU.cpuid_vendor;␊
400␉switch (p->CPU.Vendor){␊
401␉␉case CPUID_VENDOR_INTEL:␊
402␉␉{␊
403␊
404 do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
405␊
406 do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
407␊
408 /* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
409 if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
410 {␊
411 for (i = 0; i < 0xFF; i++) // safe loop␊
412 {␊
413 do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
414 if (bitfield(reg[eax], 4, 0) == 0)␊
415 {␊
416 break;␊
417 }␊
418 cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
419 }␊
420 }␊
421␊
422 do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
423␊
424 if (i > 0)␊
425 {␊
426 cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
427 threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
428 }␊
429␊
430 if (cores_per_package == 0)␊
431 {␊
432 cores_per_package = 1;␊
433 }␊
434␊
435 if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
436 {␊
437 do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
438 }␊
439␊
440 if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
441 {␊
442 do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
443 }␊
444␊
445 do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
446␊
447 if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
448 {␊
449 do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
450 do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
451 }␊
452 else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
453 {␊
454 do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
455 }␊
456␊
457␉␉switch (p->CPU.Model)␊
458␉␉{␊
459␉␉␉case CPUID_MODEL_NEHALEM:␊
460␉␉␉case CPUID_MODEL_FIELDS:␊
461␉␉␉case CPUID_MODEL_DALES:␊
462␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
463␉␉␉case CPUID_MODEL_JAKETOWN:␊
464␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
465␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
466␊
467␉␉␉case CPUID_MODEL_HASWELL:␊
468␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
469␉␉␉//case CPUID_MODEL_HASWELL_H:␊
470␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
471␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
472␉␉␉//case CPUID_MODEL_:␊
473␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
474␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
475␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
476␉␉␉␉break;␊
477␊
478␉␉␉case CPUID_MODEL_DALES_32NM:␊
479␉␉␉case CPUID_MODEL_WESTMERE:␊
480␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
481␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
482␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
483␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
484␉␉␉␉break;␊
485␉␉}␊
486␊
487␉␉if (p->CPU.NoCores == 0)␊
488␉␉{␊
489␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
490␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
491␉␉}␊
492␊
493␉␉// MSR is *NOT* available on the Intel Atom CPU␊
494␉␉//workaround for N270. I don't know why it detected wrong␊
495␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
496␉␉{␊
497␉␉␉p->CPU.NoCores␉␉= 1;␊
498␉␉␉p->CPU.NoThreads␉= 2;␊
499␉␉}␊
500␊
501␉␉//workaround for Quad␊
502␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
503␉␉{␊
504␉␉␉p->CPU.NoCores␉␉= 4;␊
505␉␉␉p->CPU.NoThreads␉= 4;␊
506␉␉}␊
507␉}␊
508␊
509␉break;␊
510␊
511␉case CPUID_VENDOR_AMD:␊
512␉{␊
513␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
514␊
515␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
516␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
517␉␉{␊
518␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
519␉␉}␊
520␊
521␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
522␉␉{␊
523␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
524␉␉}␊
525␊
526␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
527␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
528␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
529␊
530␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
531␉␉threads_per_core = cores_per_package;␊
532␊
533␉␉if (cores_per_package == 0)␊
534␉␉{␊
535␉␉␉cores_per_package = 1;␊
536␉␉}␊
537␊
538␉␉p->CPU.NoCores␉␉= cores_per_package;␊
539␉␉p->CPU.NoThreads␉= logical_per_package;␊
540␊
541␉␉if (p->CPU.NoCores == 0)␊
542␉␉{␊
543␉␉␉p->CPU.NoCores = 1;␊
544␉␉␉p->CPU.NoThreads␉= 1;␊
545␉␉}␊
546␉}␊
547␉break;␊
548␉default :␊
549␉␉stop("Unsupported CPU detected! System halted.");␊
550␉}␊
551␊
552␉/* setup features */␊
553␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
554␉{␊
555␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
556␉}␊
557␊
558␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
559␉{␊
560␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
561␉}␊
562␊
563␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
564␉{␊
565␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
566␉}␊
567␊
568␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
569␉{␊
570␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
571␉}␊
572␊
573␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
574␉{␊
575␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
576␉}␊
577␊
578␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
579␉{␊
580␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
581␉}␊
582␊
583␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
584␉{␊
585␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
586␉}␊
587␊
588␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
589␉{␊
590␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
591␉}␊
592␊
593␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
594␉{␊
595␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
596␉}␊
597␊
598␉uint64_t cycles;␊
599␉cycles = timeRDTSC();␊
600␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
601␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
602␉// if usual method failed␊
603␉if ( tscFreq < 1000 )␉//TEST␊
604␉{␊
605␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
606␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
607␉}␊
608␊
609␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
610␉{␊
611␉␉int intelCPU = p->CPU.Model;␊
612␉␉if (p->CPU.Family == 0x06)␊
613␉␉{␊
614␉␉␉/* Nehalem CPU model */␊
615␉␉␉switch (p->CPU.Model)␊
616␉␉␉{␊
617␉␉␉␉case CPUID_MODEL_NEHALEM:␊
618␉␉␉␉case CPUID_MODEL_FIELDS:␊
619␉␉␉␉case CPUID_MODEL_DALES:␊
620␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
621␉␉␉␉case CPUID_MODEL_WESTMERE:␊
622␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
623␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
624/* --------------------------------------------------------- */␊
625␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
626␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
627␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
628␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
629␉␉␉␉case CPUID_MODEL_HASWELL:␊
630␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
631␊
632␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
633␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
634/* --------------------------------------------------------- */␊
635␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
636␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
637␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
638␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
639␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
640␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
641␉␉␉␉␉if (bitfield(msr, 16, 16))␊
642␉␉␉␉␉{␊
643␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
644␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
645␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
646␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
647␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
648␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
649␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
650␉␉␉␉␉␉// is inadvertently set to 0.␊
651␊
652␉␉␉␉␉␉if (flex_ratio == 0)␊
653␉␉␉␉␉␉{␊
654␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
655␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
656␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
657␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
658␉␉␉␉␉␉}␊
659␉␉␉␉␉␉else␊
660␉␉␉␉␉␉{␊
661␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
662␉␉␉␉␉␉␉{␊
663␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
664␉␉␉␉␉␉␉}␊
665␉␉␉␉␉␉}␊
666␉␉␉␉␉}␊
667␊
668␉␉␉␉␉if (bus_ratio_max)␊
669␉␉␉␉␉{␊
670␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
671␉␉␉␉␉}␊
672␊
673␉␉␉␉␉//valv: Turbo Ratio Limit␊
674␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
675␉␉␉␉␉{␊
676␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
677␊
678␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
679␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
680␉␉␉␉␉}␊
681␉␉␉␉␉else␊
682␉␉␉␉␉{␊
683␉␉␉␉␉␉cpuFrequency = tscFreq;␊
684␉␉␉␉␉}␊
685␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
686␉␉␉␉␉{␊
687␉␉␉␉␉␉max_ratio = atoi(newratio);␊
688␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
689␉␉␉␉␉␉if (len >= 3)␊
690␉␉␉␉␉␉{␊
691␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
692␉␉␉␉␉␉}␊
693␊
694␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
695␊
696␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
697␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
698␉␉␉␉␉␉{␊
699␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
700␉␉␉␉␉␉␉if (len >= 3)␊
701␉␉␉␉␉␉␉{␊
702␉␉␉␉␉␉␉␉maxdiv = 1;␊
703␉␉␉␉␉␉␉}␊
704␉␉␉␉␉␉␉else␊
705␉␉␉␉␉␉␉{␊
706␉␉␉␉␉␉␉␉maxdiv = 0;␊
707␉␉␉␉␉␉␉}␊
708␉␉␉␉␉␉}␊
709␉␉␉␉␉␉else␊
710␉␉␉␉␉␉{␊
711␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
712␉␉␉␉␉␉}␊
713␉␉␉␉␉}␊
714␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
715␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
716␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
717␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
718␊
719␉␉␉␉myfsb = busFrequency / 1000000;␊
720␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
721␉␉␉␉currcoef = bus_ratio_max;␊
722␊
723␉␉␉␉break;␊
724␊
725␉␉␉default:␊
726␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
727␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
728␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
729␉␉␉␉// Non-integer bus ratio for the max-multi␊
730␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
731␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
732␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
733␊
734␉␉␉␉// This will always be model >= 3␊
735␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
736␉␉␉␉{␊
737␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
738␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
739␉␉␉␉}␊
740␉␉␉␉else␊
741␉␉␉␉{␊
742␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
743␉␉␉␉␉// XXX␊
744␉␉␉␉␉maxcoef = currcoef;␊
745␉␉␉␉}␊
746␊
747␉␉␉␉if (!currcoef)␊
748␉␉␉␉{␊
749␉␉␉␉␉currcoef = maxcoef;␊
750␉␉␉␉}␊
751␊
752␉␉␉␉if (maxcoef)␊
753␉␉␉␉{␊
754␉␉␉␉␉if (maxdiv)␊
755␉␉␉␉␉{␊
756␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
757␉␉␉␉␉}␊
758␉␉␉␉␉else␊
759␉␉␉␉␉{␊
760␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
761␉␉␉␉␉}␊
762␊
763␉␉␉␉␉if (currdiv)␊
764␉␉␉␉␉{␊
765␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
766␉␉␉␉␉}␊
767␉␉␉␉␉else␊
768␉␉␉␉␉{␊
769␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
770␉␉␉␉␉}␊
771␊
772␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
773␉␉␉␉}␊
774␉␉␉␉break;␊
775␉␉␉}␊
776␉␉}␊
777␉␉// Mobile CPU␊
778␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
779␉␉{␊
780␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
781␉␉}␊
782␉}␊
783␊
784␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
785␉{␊
786␉␉switch(p->CPU.Family)␊
787␉␉{␊
788␉␉␉case 0xF: /* K8 */␊
789␉␉␉{␊
790␉␉␉␉uint64_t fidvid = 0;␊
791␉␉␉␉uint64_t cpuMult;␊
792␉␉␉␉uint64_t fid;␊
793␊
794␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
795␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
796␊
797␉␉␉␉cpuMult = (fid + 8) / 2;␊
798␉␉␉␉currcoef = cpuMult;␊
799␊
800␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
801␉␉␉␉currdiv = cpuMultN2;␊
802␉␉␉␉/****** Addon END ******/␊
803␉␉␉}␊
804␉␉␉␉break;␊
805␊
806␉␉␉case 0x10: /*** AMD Family 10h ***/␊
807␉␉␉{␊
808␉␉␉␉uint64_t cofvid = 0;␊
809␉␉␉␉uint64_t cpuMult;␊
810␉␉␉␉uint64_t divisor = 0;␊
811␉␉␉␉uint64_t did;␊
812␉␉␉␉uint64_t fid;␊
813␊
814␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
815␉␉␉␉did = bitfield(cofvid, 8, 6);␊
816␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
817␉␉␉␉if (did == 0) divisor = 2;␊
818␉␉␉␉else if (did == 1) divisor = 4;␊
819␉␉␉␉else if (did == 2) divisor = 8;␊
820␉␉␉␉else if (did == 3) divisor = 16;␊
821␉␉␉␉else if (did == 4) divisor = 32;␊
822␊
823␉␉␉␉cpuMult = (fid + 16) / divisor;␊
824␉␉␉␉currcoef = cpuMult;␊
825␊
826␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
827␉␉␉␉currdiv = cpuMultN2;␊
828␊
829␉␉␉␉/****** Addon END ******/␊
830␉␉␉}␊
831␉␉␉break;␊
832␊
833␉␉␉case 0x11: /*** AMD Family 11h ***/␊
834␉␉␉{␊
835␉␉␉␉uint64_t cofvid = 0;␊
836␉␉␉␉uint64_t cpuMult;␊
837␉␉␉␉uint64_t divisor = 0;␊
838␉␉␉␉uint64_t did;␊
839␉␉␉␉uint64_t fid;␊
840␊
841␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
842␉␉␉␉did = bitfield(cofvid, 8, 6);␊
843␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
844␉␉␉␉if (did == 0) divisor = 2;␊
845␉␉␉␉else if (did == 1) divisor = 4;␊
846␉␉␉␉else if (did == 2) divisor = 8;␊
847␉␉␉␉else if (did == 3) divisor = 16;␊
848␉␉␉␉else if (did == 4) divisor = 32;␊
849␊
850␉␉␉␉cpuMult = (fid + 8) / divisor;␊
851␉␉␉␉currcoef = cpuMult;␊
852␊
853␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
854␉␉␉␉currdiv = cpuMultN2;␊
855␊
856␉␉␉␉/****** Addon END ******/␊
857␉␉␉}␊
858 break;␊
859␊
860␉␉␉case 0x12: /*** AMD Family 12h ***/␊
861␉␉␉{␊
862␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
863␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
864␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
865␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
866␊
867␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
868␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
869␉␉␉␉uint64_t divisor;␊
870␉␉␉␉switch (CpuDid)␊
871␉␉␉␉{␊
872␉␉␉␉␉case 0: divisor = 1; break;␊
873␉␉␉␉␉case 1: divisor = (3/2); break;␊
874␉␉␉␉␉case 2: divisor = 2; break;␊
875␉␉␉␉␉case 3: divisor = 3; break;␊
876␉␉␉␉␉case 4: divisor = 4; break;␊
877␉␉␉␉␉case 5: divisor = 6; break;␊
878␉␉␉␉␉case 6: divisor = 8; break;␊
879␉␉␉␉␉case 7: divisor = 12; break;␊
880␉␉␉␉␉case 8: divisor = 16; break;␊
881␉␉␉␉␉default: divisor = 1; break;␊
882␉␉␉␉}␊
883␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
884␊
885␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
886␉␉␉␉currdiv = cpuMultN2;␊
887␊
888␉␉␉}␊
889␉␉␉␉break;␊
890␊
891␉␉␉case 0x14: /* K14 */␊
892␊
893␉␉␉{␊
894␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
895␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
896␉␉␉␉uint64_t prfsts;␊
897␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
898␊
899␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
900␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
901␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
902␊
903␉␉␉␉uint64_t frequencyId = 0x10;␊
904␉␉␉␉currcoef = (frequencyId + 0x10) /␊
905␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
906␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
907␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
908␊
909␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
910␉␉␉␉currdiv = cpuMultN2;␊
911␉␉␉}␊
912␊
913␉␉␉␉break;␊
914␊
915␉␉␉case 0x15: /*** AMD Family 15h ***/␊
916␉␉␉case 0x06: /*** AMD Family 06h ***/␊
917␉␉␉{␊
918␊
919␉␉␉␉uint64_t cofvid = 0;␊
920␉␉␉␉uint64_t cpuMult;␊
921␉␉␉␉uint64_t divisor = 0;␊
922␉␉␉␉uint64_t did;␊
923␉␉␉␉uint64_t fid;␊
924␊
925␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
926␉␉␉␉did = bitfield(cofvid, 8, 6);␊
927␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
928␉␉␉␉if (did == 0) divisor = 2;␊
929␉␉␉␉else if (did == 1) divisor = 4;␊
930␉␉␉␉else if (did == 2) divisor = 8;␊
931␉␉␉␉else if (did == 3) divisor = 16;␊
932␉␉␉␉else if (did == 4) divisor = 32;␊
933␊
934␉␉␉␉cpuMult = (fid + 16) / divisor;␊
935␉␉␉␉currcoef = cpuMult;␊
936␊
937␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
938␉␉␉␉currdiv = cpuMultN2;␊
939␉␉␉}␊
940␉␉␉␉break;␊
941␊
942␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
943␉␉␉{␊
944␉␉␉␉uint64_t cofvid = 0;␊
945␉␉␉␉uint64_t cpuMult;␊
946␉␉␉␉uint64_t divisor = 0;␊
947␉␉␉␉uint64_t did;␊
948␉␉␉␉uint64_t fid;␊
949␊
950␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
951␉␉␉␉did = bitfield(cofvid, 8, 6);␊
952␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
953␉␉␉␉if (did == 0) divisor = 1;␊
954␉␉␉␉else if (did == 1) divisor = 2;␊
955␉␉␉␉else if (did == 2) divisor = 4;␊
956␉␉␉␉else if (did == 3) divisor = 8;␊
957␉␉␉␉else if (did == 4) divisor = 16;␊
958␊
959␉␉␉␉cpuMult = (fid + 16) / divisor;␊
960␉␉␉␉currcoef = cpuMult;␊
961␊
962␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
963␉␉␉␉currdiv = cpuMultN2;␊
964␉␉␉␉/****** Addon END ******/␊
965␉␉␉}␊
966␉␉␉␉break;␊
967␊
968␉␉␉default:␊
969␉␉␉{␊
970␉␉␉␉typedef unsigned long long vlong;␊
971␉␉␉␉uint64_t prfsts;␊
972␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
973␉␉␉␉uint64_t r;␊
974␉␉␉␉vlong hz;␊
975␉␉␉␉r = (prfsts>>6) & 0x07;␊
976␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
977␊
978␉␉␉␉currcoef = hz / (200 * Mega);␊
979␉␉␉}␊
980␉␉}␊
981␊
982␉␉if (currcoef)␊
983␉␉{␊
984␉␉␉if (currdiv)␊
985␉␉␉{␊
986␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
987␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
988␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
989␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
990␊
991␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
992␉␉␉}␊
993␉␉␉else␊
994␉␉␉{␊
995␉␉␉␉busFrequency = (tscFreq / currcoef);␊
996␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
997␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
998␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
999␉␉␉␉DBG("%d\n", currcoef);␊
1000␉␉␉}␊
1001␉␉}␊
1002␉␉else if (!cpuFrequency)␊
1003␉␉{␊
1004␉␉␉cpuFrequency = tscFreq;␊
1005␉␉}␊
1006␉}␊
1007␊
1008#if 0␊
1009␉if (!busFrequency)␊
1010␉{␊
1011␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1012␉␉DBG("CPU: busFrequency = 0! using the default value for FSB!\n");␊
1013␉␉cpuFrequency = tscFreq;␊
1014␉}␊
1015␊
1016␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1017␊
1018#endif␊
1019␊
1020␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1021␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1022␉p->CPU.CurrCoef = currcoef;␊
1023␉p->CPU.CurrDiv = currdiv;␊
1024␉p->CPU.TSCFrequency = tscFreq;␊
1025␉p->CPU.FSBFrequency = busFrequency;␊
1026␉p->CPU.CPUFrequency = cpuFrequency;␊
1027␊
1028␉// keep formatted with spaces instead of tabs␊
1029␉DBG("\n------------------------------\n");␊
1030 ␉DBG("\tCPU INFO\n");␊
1031␉DBG("------------------------------\n");␊
1032␊
1033␉DBG("CPUID Raw Values:\n");␊
1034␉for (i = 0; i < CPUID_MAX; i++)␊
1035␉{␊
1036␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1037␉}␊
1038␉DBG("\n");␊
1039␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1040␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1041␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1042␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊
1043␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1044␉/*switch (p->CPU.Type) {␊
1045␉␉case PT_OEM:␊
1046␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
1047␉␉␉break;␊
1048␉␉case PT_OD:␊
1049␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
1050␉␉␉break;␊
1051␉␉case PT_DUAL:␊
1052␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
1053␉␉␉break;␊
1054␉␉case PT_RES:␊
1055␉␉␉DBG("Processor type: Intel Reserved\n");␊
1056␉␉␉break;␊
1057␉␉default:␊
1058␉␉␉break;␊
1059␉}*/␊
1060␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1061␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊
1062␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1063␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1064␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1065␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1066␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1067␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
1068␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
1069␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
1070␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1071␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1072␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
1073␊
1074␉DBG("\n---------------------------------------------\n");␊
1075#if DEBUG_CPU␊
1076␉pause();␊
1077#endif␊
1078}␊
1079

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