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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␊
20#endif␊
21␊
22␊
23#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
24␊
25clock_frequency_info_t gPEClockFrequencyInfo;␊
26␊
27static inline uint32_t __unused clockspeed_rdtsc(void)␊
28{␊
29␉uint32_t out;␊
30␉__asm__ volatile (␊
31 "rdtsc\n"␊
32 "shl $32,%%edx\n"␊
33 "or %%edx,%%eax\n"␊
34 : "=a" (out)␊
35 :␊
36 : "%edx"␊
37 );␊
38␉return out;␊
39}␊
40␊
41/*␊
42 * timeRDTSC()␊
43 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
44 * It pauses until the value is latched in the counter␊
45 * and then reads the time stamp counter to return to the caller.␊
46 */␊
47static uint64_t timeRDTSC(void)␊
48{␊
49␉int␉␉attempts = 0;␊
50␉uint64_t ␉latchTime;␊
51␉uint64_t␉saveTime,intermediate;␊
52␉unsigned int␉timerValue, lastValue;␊
53␉//boolean_t␉int_enabled;␊
54␉/*␊
55␉ * Table of correction factors to account for␊
56␉ *␉ - timer counter quantization errors, and␊
57␉ *␉ - undercounts 0..5␊
58␉ */␊
59#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
60#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
61#define SAMPLE_NSECS␉␉(2000000000LL)␊
62#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
63#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
64␉uint64_t␉scale[6] = {␊
65␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
66␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
67␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
68␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
69␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
70␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
71␉};␊
72␊
73␉//int_enabled = ml_set_interrupts_enabled(false);␊
74␊
75restart:␊
76␉if (attempts >= 3) // increase to up to 9 attempts.␊
77␉{␊
78␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
79␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
80␉}␊
81␉attempts++;␊
82␉enable_PIT2();␉␉// turn on PIT2␊
83␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
84␉latchTime = rdtsc64();␉// get the time stamp to time␊
85␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
86␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
87␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
88␉get_PIT2(&lastValue);␊
89␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
90␉do {␊
91␉␉intermediate = get_PIT2(&timerValue);␊
92␉␉if (timerValue > lastValue)␊
93␉␉{␊
94␉␉␉// Timer wrapped␊
95␉␉␉set_PIT2(0);␊
96␉␉␉disable_PIT2();␊
97␉␉␉goto restart;␊
98␉␉}␊
99␉␉lastValue = timerValue;␊
100␉} while (timerValue > 5);␊
101␉//printf("timerValue␉ %d\n",timerValue);␊
102␉//printf("intermediate 0x%016llX\n",intermediate);␊
103␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
104 ␊
105␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
106␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
107␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
108␉intermediate += latchTime;␉␉// add on our save fudge␊
109␊
110␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
111␉disable_PIT2();␉␉␉// turn off PIT 2␊
112␊
113␉//ml_set_interrupts_enabled(int_enabled);␊
114␉return intermediate;␊
115}␊
116␊
117/*␊
118 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
119 */␊
120static uint64_t __unused measure_tsc_frequency(void)␊
121{␊
122␉uint64_t tscStart;␊
123␉uint64_t tscEnd;␊
124␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
125␉unsigned long pollCount;␊
126␉uint64_t retval = 0;␊
127␉int i;␊
128␊
129␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
130␉ * counter 2. We run this loop 3 times to make sure the cache␊
131␉ * is hot and we take the minimum delta from all of the runs.␊
132␉ * That is to say that we're biased towards measuring the minimum␊
133␉ * number of TSC ticks that occur while waiting for the timer to␊
134␉ * expire. That theoretically helps avoid inconsistencies when␊
135␉ * running under a VM if the TSC is not virtualized and the host␊
136␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
137␉ */␊
138␉for(i = 0; i < 10; ++i)␊
139␉{␊
140␉␉enable_PIT2();␊
141␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
142␉␉tscStart = rdtsc64();␊
143␉␉pollCount = poll_PIT2_gate();␊
144␉␉tscEnd = rdtsc64();␊
145␉␉/* The poll loop must have run at least a few times for accuracy */␊
146␉␉if (pollCount <= 1)␊
147␉␉{␊
148␉␉␉continue;␊
149␉␉}␊
150␉␉/* The TSC must increment at LEAST once every millisecond.␊
151␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
152␉␉ * be >= 30. Anything less and the processor is way too slow.␊
153␉␉ */␊
154␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
155␉␉{␊
156␉␉␉continue;␊
157␉␉}␊
158␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
159␉␉if ( (tscEnd - tscStart) < tscDelta )␊
160␉␉{␊
161␉␉␉tscDelta = tscEnd - tscStart;␊
162␉␉}␊
163␉}␊
164␉/* tscDelta is now the least number of TSC ticks the processor made in␊
165␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
166␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
167␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
168␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
169␉ * dividing by the milliseconds, we simply multiply by 1000.␊
170␉ */␊
171␊
172␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
173␉ * that we're going to multiply by 1000 first so we do need at least some␊
174␉ * arithmetic headroom. For now, 32-bit should be enough.␊
175␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
176␉ */␊
177␉if (tscDelta > (1ULL<<32))␊
178␉{␊
179␉␉retval = 0;␊
180␉}␊
181␉else␊
182␉{␊
183␉␉retval = tscDelta * 1000 / 30;␊
184␉}␊
185␉disable_PIT2();␊
186␉return retval;␊
187}␊
188␊
189static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
190#define RTC_FAST_DENOM␉0xFFFFFFFF␊
191␊
192inline static uint32_t␊
193create_mul_quant_GHZ(int shift, uint32_t quant)␊
194{␊
195␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
196}␊
197␊
198struct␉{␊
199␉mach_timespec_t␉␉␉calend_offset;␊
200␉boolean_t␉␉␉calend_is_set;␊
201␊
202␉int64_t␉␉␉␉calend_adjtotal;␊
203␉int32_t␉␉␉␉calend_adjdelta;␊
204␊
205␉uint32_t␉␉␉boottime;␊
206␊
207␉mach_timebase_info_data_t␉timebase_const;␊
208␊
209␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
210} rtclock;␊
211␊
212uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
213uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
214uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
215uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
216//uint64_t cpuFreq;␊
217␊
218static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
219{␊
220␊
221␉if (cycles > (NSEC_PER_SEC/20))␊
222␉{␊
223␉␉// we can use just a "fast" multiply to get nanos␊
224␉␉rtc_quant_shift = 32;␊
225␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
226␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
227␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
228␉}␊
229␉else␊
230␉{␊
231␉␉rtc_quant_shift = 26;␊
232␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
233␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
234␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
235␉}␊
236␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
237␉// BUT we also want to calculate...␊
238␊
239␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
240 / UI_CPUFREQ_ROUNDING_FACTOR)␊
241␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
242␊
243␉/*␊
244␉ * Set current measured speed.␊
245␉ */␊
246␉if (cycles >= 0x100000000ULL)␊
247␉{␊
248␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
249␉}␊
250␉else␊
251␉{␊
252␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
253␉}␊
254␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
255␊
256␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
257␉return(rtc_cyc_per_sec);␊
258}␊
259␊
260/*␊
261 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
262 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
263 *␉ a max multi. (used to calculate the FSB freq.),␊
264 *␉ and a current multi. (used to calculate the CPU freq.)␊
265 * - busFrequency = tscFrequency / multi␊
266 * - cpuFrequency = busFrequency * multi␊
267 */␊
268␊
269/* Decimal powers: */␊
270#define kilo (1000ULL)␊
271#define Mega (kilo * kilo)␊
272#define Giga (kilo * Mega)␊
273#define Tera (kilo * Giga)␊
274#define Peta (kilo * Tera)␊
275␊
276#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
277␊
278void scan_cpu(PlatformInfo_t *p)␊
279{␊
280//␉scan();␊
281␉uint64_t␉busFCvtt2n;␊
282␉uint64_t␉tscFCvtt2n;␊
283␉uint64_t␉tscFreq␉␉␉= 0;␊
284␉uint64_t␉busFrequency␉␉= 0;␊
285␉uint64_t␉cpuFrequency␉␉= 0;␊
286␉uint64_t␉msr␉␉␉= 0;␊
287␉uint64_t␉flex_ratio␉␉= 0;␊
288␉uint64_t␉cpuid_features;␊
289␊
290␉uint32_t␉max_ratio␉␉= 0;␊
291␉uint32_t␉min_ratio␉␉= 0;␊
292␉uint32_t␉reg[4];␊
293␉uint32_t␉cores_per_package␉= 0;␊
294␉uint32_t␉logical_per_package␉= 1;␊
295␉uint32_t␉threads_per_core␉= 1;␊
296␊
297␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
298␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
299␉uint8_t␉␉currdiv␉␉␉= 0;␊
300␉uint8_t␉␉currcoef␉␉= 0;␊
301␉uint8_t␉␉maxdiv␉␉␉= 0;␊
302␉uint8_t␉␉maxcoef␉␉␉= 0;␊
303␉uint8_t␉␉pic0_mask;␊
304␉uint8_t␉␉cpuMultN2␉␉= 0;␊
305␊
306␉const char␉*newratio;␊
307␉char␉␉str[128];␊
308␉char␉␉*s␉␉␉= 0;␊
309␊
310␉int␉␉len␉␉␉= 0;␊
311␉int␉␉myfsb␉␉␉= 0;␊
312␉int␉␉i␉␉␉= 0;␊
313␊
314␊
315/* http://www.flounder.com/cpuid_explorer2.htm␊
316 EAX (Intel):␊
317 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
318 +--------+----------------+--------+----+----+--------+--------+--------+␊
319 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
320 +--------+----------------+--------+----+----+--------+--------+--------+␊
321␊
322 EAX (AMD):␊
323 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
324 +--------+----------------+--------+----+----+--------+--------+--------+␊
325 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
326 +--------+----------------+--------+----+----+--------+--------+--------+␊
327*/␊
328␉///////////////////-- MaxFn,Vendor --////////////////////////␊
329␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
330␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
331␉/////////////////////////////////////////////////////////////␊
332␊
333␉///////////////////-- Signature, stepping, features -- //////␊
334␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
335␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx],p->CPU.CPUID[CPUID_1][edx]);␊
336␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
337␉{␊
338␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
339␉}␊
340␉else␊
341␉{␊
342␉␉logical_per_package = 1;␊
343␉}␊
344//␉printf("logical %d\n",logical_per_package);␊
345␊
346␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
347␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
348␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
349␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
350␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
351␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
352␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
353␊
354␉if (p->CPU.Family == 0x0f)␊
355␉{␊
356␉␉p->CPU.Family += p->CPU.ExtFamily;␊
357␉}␊
358␊
359␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
360␉{␊
361␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
362␉}␊
363␊
364␉/* get BrandString (if supported) */␊
365␉/* Copyright: from Apple's XNU cpuid.c */␊
366␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
367␉{␊
368␉␉bzero(str, 128);␊
369␉␉/*␊
370␉␉ * The BrandString 48 bytes (max), guaranteed to␊
371␉␉ * be NULL terminated.␊
372␉␉ */␊
373␉␉do_cpuid(0x80000002, reg);␊
374␉␉memcpy(&str[0], (char *)reg, 16);␊
375␉␉do_cpuid(0x80000003, reg);␊
376␉␉memcpy(&str[16], (char *)reg, 16);␊
377␉␉do_cpuid(0x80000004, reg);␊
378␉␉memcpy(&str[32], (char *)reg, 16);␊
379␉␉for (s = str; *s != '\0'; s++)␊
380␉␉{␊
381␉␉␉if (*s != ' ')␊
382␉␉␉{␊
383␉␉␉␉break;␊
384␉␉␉}␊
385␉␉}␊
386␉␉strlcpy(p->CPU.BrandString, s, 48);␊
387␊
388␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
389␉␉{␊
390␉␉␉/*␊
391␉␉␉ * This string means we have a firmware-programmable brand string,␊
392␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
393␉␉␉ */␊
394␉␉␉p->CPU.BrandString[0] = '\0';␊
395␉␉}␊
396␉␉p->CPU.BrandString[47] = '\0';␊
397//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
398␉}␊
399␊
400␉//char *vendor = p->CPU.cpuid_vendor;␊
401␉switch (p->CPU.Vendor){␊
402␉␉case CPUID_VENDOR_INTEL:␊
403␉␉{␊
404␊
405 do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
406␊
407 do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
408␊
409 /* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
410 if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
411 {␊
412 for (i = 0; i < 0xFF; i++) // safe loop␊
413 {␊
414 do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
415 if (bitfield(reg[eax], 4, 0) == 0)␊
416 {␊
417 break;␊
418 }␊
419 cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
420 }␊
421 }␊
422␊
423 do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
424␊
425 if (i > 0)␊
426 {␊
427 cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
428 threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
429 }␊
430␊
431 if (cores_per_package == 0)␊
432 {␊
433 cores_per_package = 1;␊
434 }␊
435␊
436 if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
437 {␊
438 do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
439 }␊
440␊
441 if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
442 {␊
443 do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
444 }␊
445␊
446 do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
447␊
448 if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
449 {␊
450 do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
451 do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
452 }␊
453 else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
454 {␊
455 do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
456 }␊
457␊
458␉␉switch (p->CPU.Model)␊
459␉␉{␊
460␉␉␉case CPUID_MODEL_NEHALEM:␊
461␉␉␉case CPUID_MODEL_FIELDS:␊
462␉␉␉case CPUID_MODEL_DALES:␊
463␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
464␉␉␉case CPUID_MODEL_JAKETOWN:␊
465␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
466␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
467␊
468␉␉␉case CPUID_MODEL_HASWELL:␊
469␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
470␉␉␉//case CPUID_MODEL_HASWELL_H:␊
471␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
472␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
473␉␉␉//case CPUID_MODEL_:␊
474␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
475␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
476␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
477␉␉␉␉break;␊
478␊
479␉␉␉case CPUID_MODEL_DALES_32NM:␊
480␉␉␉case CPUID_MODEL_WESTMERE:␊
481␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
482␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
483␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
484␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
485␉␉␉␉break;␊
486␉␉}␊
487␊
488␉␉if (p->CPU.NoCores == 0)␊
489␉␉{␊
490␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
491␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
492␉␉}␊
493␊
494␉␉// MSR is *NOT* available on the Intel Atom CPU␊
495␉␉//workaround for N270. I don't know why it detected wrong␊
496␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
497␉␉{␊
498␉␉␉p->CPU.NoCores␉␉= 1;␊
499␉␉␉p->CPU.NoThreads␉= 2;␊
500␉␉}␊
501␊
502␉␉//workaround for Quad␊
503␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
504␉␉{␊
505␉␉␉p->CPU.NoCores␉␉= 4;␊
506␉␉␉p->CPU.NoThreads␉= 4;␊
507␉␉}␊
508␉}␊
509␊
510␉break;␊
511␊
512␉case CPUID_VENDOR_AMD:␊
513␉{␊
514␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
515␊
516␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
517␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
518␉␉{␊
519␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
520␉␉}␊
521␊
522␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
523␉␉{␊
524␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
525␉␉}␊
526␊
527␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
528␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
529␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
530␊
531␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
532␉␉threads_per_core = cores_per_package;␊
533␊
534␉␉if (cores_per_package == 0)␊
535␉␉{␊
536␉␉␉cores_per_package = 1;␊
537␉␉}␊
538␊
539␉␉p->CPU.NoCores␉␉= cores_per_package;␊
540␉␉p->CPU.NoThreads␉= logical_per_package;␊
541␊
542␉␉if (p->CPU.NoCores == 0)␊
543␉␉{␊
544␉␉␉p->CPU.NoCores = 1;␊
545␉␉␉p->CPU.NoThreads␉= 1;␊
546␉␉}␊
547␉}␊
548␉break;␊
549␉default :␊
550␉␉stop("Unsupported CPU detected! System halted.");␊
551␉}␊
552␊
553␉/* setup features */␊
554␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
555␉{␊
556␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
557␉}␊
558␊
559␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
560␉{␊
561␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
562␉}␊
563␊
564␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
565␉{␊
566␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
567␉}␊
568␊
569␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
570␉{␊
571␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
572␉}␊
573␊
574␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
575␉{␊
576␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
577␉}␊
578␊
579␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
580␉{␊
581␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
582␉}␊
583␊
584␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
585␉{␊
586␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
587␉}␊
588␊
589␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
590␉{␊
591␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
592␉}␊
593␊
594␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
595␉{␊
596␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
597␉}␊
598␊
599␉pic0_mask = inb(0x21U);␊
600␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
601␊
602␉uint64_t cycles;␊
603␉cycles = timeRDTSC();␊
604␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
605␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
606␉// if usual method failed␊
607␉if ( tscFreq < 1000 )␉//TEST␊
608␉{␊
609␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
610␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
611␉}␊
612␊
613␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
614␉{␊
615␉␉int intelCPU = p->CPU.Model;␊
616␉␉if (p->CPU.Family == 0x06)␊
617␉␉{␊
618␉␉␉/* Nehalem CPU model */␊
619␉␉␉switch (p->CPU.Model)␊
620␉␉␉{␊
621␉␉␉␉case CPUID_MODEL_NEHALEM:␊
622␉␉␉␉case CPUID_MODEL_FIELDS:␊
623␉␉␉␉case CPUID_MODEL_DALES:␊
624␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
625␉␉␉␉case CPUID_MODEL_WESTMERE:␊
626␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
627␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
628/* --------------------------------------------------------- */␊
629␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
630␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
631␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
632␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
633␉␉␉␉case CPUID_MODEL_HASWELL:␊
634␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
635␊
636␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
637␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
638/* --------------------------------------------------------- */␊
639␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
640␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
641␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
642␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
643␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
644␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
645␉␉␉␉␉if (bitfield(msr, 16, 16))␊
646␉␉␉␉␉{␊
647␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
648␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
649␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
650␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
651␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
652␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
653␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
654␉␉␉␉␉␉// is inadvertently set to 0.␊
655␊
656␉␉␉␉␉␉if (flex_ratio == 0)␊
657␉␉␉␉␉␉{␊
658␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
659␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
660␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
661␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
662␉␉␉␉␉␉}␊
663␉␉␉␉␉␉else␊
664␉␉␉␉␉␉{␊
665␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
666␉␉␉␉␉␉␉{␊
667␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
668␉␉␉␉␉␉␉}␊
669␉␉␉␉␉␉}␊
670␉␉␉␉␉}␊
671␊
672␉␉␉␉␉if (bus_ratio_max)␊
673␉␉␉␉␉{␊
674␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
675␉␉␉␉␉}␊
676␊
677␉␉␉␉␉//valv: Turbo Ratio Limit␊
678␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
679␉␉␉␉␉{␊
680␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
681␊
682␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
683␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
684␉␉␉␉␉}␊
685␉␉␉␉␉else␊
686␉␉␉␉␉{␊
687␉␉␉␉␉␉cpuFrequency = tscFreq;␊
688␉␉␉␉␉}␊
689␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
690␉␉␉␉␉{␊
691␉␉␉␉␉␉max_ratio = atoi(newratio);␊
692␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
693␉␉␉␉␉␉if (len >= 3)␊
694␉␉␉␉␉␉{␊
695␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
696␉␉␉␉␉␉}␊
697␊
698␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
699␊
700␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
701␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
702␉␉␉␉␉␉{␊
703␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
704␉␉␉␉␉␉␉if (len >= 3)␊
705␉␉␉␉␉␉␉{␊
706␉␉␉␉␉␉␉␉maxdiv = 1;␊
707␉␉␉␉␉␉␉}␊
708␉␉␉␉␉␉␉else␊
709␉␉␉␉␉␉␉{␊
710␉␉␉␉␉␉␉␉maxdiv = 0;␊
711␉␉␉␉␉␉␉}␊
712␉␉␉␉␉␉}␊
713␉␉␉␉␉␉else␊
714␉␉␉␉␉␉{␊
715␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
716␉␉␉␉␉␉}␊
717␉␉␉␉␉}␊
718␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
719␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
720␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
721␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
722␊
723␉␉␉␉myfsb = busFrequency / 1000000;␊
724␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
725␉␉␉␉currcoef = bus_ratio_max;␊
726␊
727␉␉␉␉break;␊
728␊
729␉␉␉default:␊
730␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
731␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
732␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
733␉␉␉␉// Non-integer bus ratio for the max-multi␊
734␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
735␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
736␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
737␊
738␉␉␉␉// This will always be model >= 3␊
739␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
740␉␉␉␉{␊
741␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
742␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
743␉␉␉␉}␊
744␉␉␉␉else␊
745␉␉␉␉{␊
746␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
747␉␉␉␉␉// XXX␊
748␉␉␉␉␉maxcoef = currcoef;␊
749␉␉␉␉}␊
750␊
751␉␉␉␉if (!currcoef)␊
752␉␉␉␉{␊
753␉␉␉␉␉currcoef = maxcoef;␊
754␉␉␉␉}␊
755␊
756␉␉␉␉if (maxcoef)␊
757␉␉␉␉{␊
758␉␉␉␉␉if (maxdiv)␊
759␉␉␉␉␉{␊
760␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
761␉␉␉␉␉}␊
762␉␉␉␉␉else␊
763␉␉␉␉␉{␊
764␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
765␉␉␉␉␉}␊
766␊
767␉␉␉␉␉if (currdiv)␊
768␉␉␉␉␉{␊
769␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
770␉␉␉␉␉}␊
771␉␉␉␉␉else␊
772␉␉␉␉␉{␊
773␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
774␉␉␉␉␉}␊
775␊
776␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
777␉␉␉␉}␊
778␉␉␉␉break;␊
779␉␉␉}␊
780␉␉}␊
781␉␉// Mobile CPU␊
782␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
783␉␉{␊
784␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
785␉␉}␊
786␉}␊
787␊
788␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
789␉{␊
790␉␉switch(p->CPU.Family)␊
791␉␉{␊
792␉␉␉case 0xF: /* K8 */␊
793␉␉␉{␊
794␉␉␉␉uint64_t fidvid = 0;␊
795␉␉␉␉uint64_t cpuMult;␊
796␉␉␉␉uint64_t fid;␊
797␊
798␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
799␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
800␊
801␉␉␉␉cpuMult = (fid + 8) / 2;␊
802␉␉␉␉currcoef = cpuMult;␊
803␊
804␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
805␉␉␉␉currdiv = cpuMultN2;␊
806␉␉␉␉/****** Addon END ******/␊
807␉␉␉}␊
808␉␉␉␉break;␊
809␊
810␉␉␉case 0x10: /*** AMD Family 10h ***/␊
811␉␉␉{␊
812␉␉␉␉uint64_t cofvid = 0;␊
813␉␉␉␉uint64_t cpuMult;␊
814␉␉␉␉uint64_t divisor = 0;␊
815␉␉␉␉uint64_t did;␊
816␉␉␉␉uint64_t fid;␊
817␊
818␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
819␉␉␉␉did = bitfield(cofvid, 8, 6);␊
820␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
821␉␉␉␉if (did == 0) divisor = 2;␊
822␉␉␉␉else if (did == 1) divisor = 4;␊
823␉␉␉␉else if (did == 2) divisor = 8;␊
824␉␉␉␉else if (did == 3) divisor = 16;␊
825␉␉␉␉else if (did == 4) divisor = 32;␊
826␊
827␉␉␉␉cpuMult = (fid + 16) / divisor;␊
828␉␉␉␉currcoef = cpuMult;␊
829␊
830␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
831␉␉␉␉currdiv = cpuMultN2;␊
832␊
833␉␉␉␉/****** Addon END ******/␊
834␉␉␉}␊
835␉␉␉break;␊
836␊
837␉␉␉case 0x11: /*** AMD Family 11h ***/␊
838␉␉␉{␊
839␉␉␉␉uint64_t cofvid = 0;␊
840␉␉␉␉uint64_t cpuMult;␊
841␉␉␉␉uint64_t divisor = 0;␊
842␉␉␉␉uint64_t did;␊
843␉␉␉␉uint64_t fid;␊
844␊
845␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
846␉␉␉␉did = bitfield(cofvid, 8, 6);␊
847␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
848␉␉␉␉if (did == 0) divisor = 2;␊
849␉␉␉␉else if (did == 1) divisor = 4;␊
850␉␉␉␉else if (did == 2) divisor = 8;␊
851␉␉␉␉else if (did == 3) divisor = 16;␊
852␉␉␉␉else if (did == 4) divisor = 32;␊
853␊
854␉␉␉␉cpuMult = (fid + 8) / divisor;␊
855␉␉␉␉currcoef = cpuMult;␊
856␊
857␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
858␉␉␉␉currdiv = cpuMultN2;␊
859␊
860␉␉␉␉/****** Addon END ******/␊
861␉␉␉}␊
862 break;␊
863␊
864␉␉␉case 0x12: /*** AMD Family 12h ***/␊
865␉␉␉{␊
866␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
867␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
868␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
869␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
870␊
871␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
872␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
873␉␉␉␉uint64_t divisor;␊
874␉␉␉␉switch (CpuDid)␊
875␉␉␉␉{␊
876␉␉␉␉␉case 0: divisor = 1; break;␊
877␉␉␉␉␉case 1: divisor = (3/2); break;␊
878␉␉␉␉␉case 2: divisor = 2; break;␊
879␉␉␉␉␉case 3: divisor = 3; break;␊
880␉␉␉␉␉case 4: divisor = 4; break;␊
881␉␉␉␉␉case 5: divisor = 6; break;␊
882␉␉␉␉␉case 6: divisor = 8; break;␊
883␉␉␉␉␉case 7: divisor = 12; break;␊
884␉␉␉␉␉case 8: divisor = 16; break;␊
885␉␉␉␉␉default: divisor = 1; break;␊
886␉␉␉␉}␊
887␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
888␊
889␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
890␉␉␉␉currdiv = cpuMultN2;␊
891␊
892␉␉␉}␊
893␉␉␉␉break;␊
894␊
895␉␉␉case 0x14: /* K14 */␊
896␊
897␉␉␉{␊
898␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
899␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
900␉␉␉␉uint64_t prfsts;␊
901␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
902␊
903␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
904␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
905␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
906␊
907␉␉␉␉uint64_t frequencyId = 0x10;␊
908␉␉␉␉currcoef = (frequencyId + 0x10) /␊
909␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
910␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
911␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
912␊
913␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
914␉␉␉␉currdiv = cpuMultN2;␊
915␉␉␉}␊
916␊
917␉␉␉␉break;␊
918␊
919␉␉␉case 0x15: /*** AMD Family 15h ***/␊
920␉␉␉case 0x06: /*** AMD Family 06h ***/␊
921␉␉␉{␊
922␊
923␉␉␉␉uint64_t cofvid = 0;␊
924␉␉␉␉uint64_t cpuMult;␊
925␉␉␉␉uint64_t divisor = 0;␊
926␉␉␉␉uint64_t did;␊
927␉␉␉␉uint64_t fid;␊
928␊
929␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
930␉␉␉␉did = bitfield(cofvid, 8, 6);␊
931␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
932␉␉␉␉if (did == 0) divisor = 2;␊
933␉␉␉␉else if (did == 1) divisor = 4;␊
934␉␉␉␉else if (did == 2) divisor = 8;␊
935␉␉␉␉else if (did == 3) divisor = 16;␊
936␉␉␉␉else if (did == 4) divisor = 32;␊
937␊
938␉␉␉␉cpuMult = (fid + 16) / divisor;␊
939␉␉␉␉currcoef = cpuMult;␊
940␊
941␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
942␉␉␉␉currdiv = cpuMultN2;␊
943␉␉␉}␊
944␉␉␉␉break;␊
945␊
946␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
947␉␉␉{␊
948␉␉␉␉uint64_t cofvid = 0;␊
949␉␉␉␉uint64_t cpuMult;␊
950␉␉␉␉uint64_t divisor = 0;␊
951␉␉␉␉uint64_t did;␊
952␉␉␉␉uint64_t fid;␊
953␊
954␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
955␉␉␉␉did = bitfield(cofvid, 8, 6);␊
956␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
957␉␉␉␉if (did == 0) divisor = 1;␊
958␉␉␉␉else if (did == 1) divisor = 2;␊
959␉␉␉␉else if (did == 2) divisor = 4;␊
960␉␉␉␉else if (did == 3) divisor = 8;␊
961␉␉␉␉else if (did == 4) divisor = 16;␊
962␊
963␉␉␉␉cpuMult = (fid + 16) / divisor;␊
964␉␉␉␉currcoef = cpuMult;␊
965␊
966␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
967␉␉␉␉currdiv = cpuMultN2;␊
968␉␉␉␉/****** Addon END ******/␊
969␉␉␉}␊
970␉␉␉␉break;␊
971␊
972␉␉␉default:␊
973␉␉␉{␊
974␉␉␉␉typedef unsigned long long vlong;␊
975␉␉␉␉uint64_t prfsts;␊
976␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
977␉␉␉␉uint64_t r;␊
978␉␉␉␉vlong hz;␊
979␉␉␉␉r = (prfsts>>6) & 0x07;␊
980␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
981␊
982␉␉␉␉currcoef = hz / (200 * Mega);␊
983␉␉␉}␊
984␉␉}␊
985␊
986␉␉if (currcoef)␊
987␉␉{␊
988␉␉␉if (currdiv)␊
989␉␉␉{␊
990␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
991␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
992␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
993␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
994␊
995␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
996␉␉␉}␊
997␉␉␉else␊
998␉␉␉{␊
999␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1000␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1001␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1002␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1003␉␉␉␉DBG("%d\n", currcoef);␊
1004␉␉␉}␊
1005␉␉}␊
1006␉␉else if (!cpuFrequency)␊
1007␉␉{␊
1008␉␉␉cpuFrequency = tscFreq;␊
1009␉␉}␊
1010␉}␊
1011␊
1012#if 0␊
1013␉if (!busFrequency)␊
1014␉{␊
1015␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1016␉␉DBG("CPU: busFrequency = 0! using the default value for FSB!\n");␊
1017␉␉cpuFrequency = tscFreq;␊
1018␉}␊
1019␊
1020␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1021␊
1022#endif␊
1023␊
1024␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
1025␊
1026␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1027␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1028␉p->CPU.CurrCoef = currcoef;␊
1029␉p->CPU.CurrDiv = currdiv;␊
1030␉p->CPU.TSCFrequency = tscFreq;␊
1031␉p->CPU.FSBFrequency = busFrequency;␊
1032␉p->CPU.CPUFrequency = cpuFrequency;␊
1033␊
1034␉// keep formatted with spaces instead of tabs␊
1035␉DBG("\n------------------------------\n");␊
1036 ␉DBG("\tCPU INFO\n");␊
1037␉DBG("------------------------------\n");␊
1038␊
1039␉DBG("CPUID Raw Values:\n");␊
1040␉for (i = 0; i < CPUID_MAX; i++)␊
1041␉{␊
1042␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1043␉}␊
1044␉DBG("\n");␊
1045␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1046␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1047␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1048␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊
1049␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1050␉/*switch (p->CPU.Type) {␊
1051␉␉case PT_OEM:␊
1052␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
1053␉␉␉break;␊
1054␉␉case PT_OD:␊
1055␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
1056␉␉␉break;␊
1057␉␉case PT_DUAL:␊
1058␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
1059␉␉␉break;␊
1060␉␉case PT_RES:␊
1061␉␉␉DBG("Processor type: Intel Reserved\n");␊
1062␉␉␉break;␊
1063␉␉default:␊
1064␉␉␉break;␊
1065␉}*/␊
1066␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1067␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊
1068␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1069␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1070␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1071␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1072␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1073␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
1074␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
1075␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
1076␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1077␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1078␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
1079␊
1080␉DBG("\n---------------------------------------------\n");␊
1081#if DEBUG_CPU␊
1082␉pause();␊
1083#endif␊
1084}␊
1085

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