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Root/trunk/i386/libsaio/state_generator.c

1/*␊
2 * Copyright 2008 mackerintel␊
3 *␊
4 * state_generator.h␊
5 * Chameleon␊
6 *␊
7 * Created by Mozodojo on 20/07/10.␊
8 * Copyright 2010 mozodojo. All rights reserved.␊
9 *␊
10 */␊
11␊
12#include "libsaio.h"␊
13#include "boot.h"␊
14#include "bootstruct.h"␊
15#include "acpi.h"␊
16#include "efi_tables.h"␊
17#include "fake_efi.h"␊
18#include "acpi_patcher.h"␊
19#include "platform.h"␊
20#include "cpu.h"␊
21#include "aml_generator.h"␊
22#include "state_generator.h"␊
23␊
24#ifndef DEBUG_STATE␊
25#define DEBUG_STATE 0␊
26#endif␊
27␊
28#if DEBUG_STATE==2␊
29#define DBG(x...) {printf(x); sleep(1);}␊
30#elif DEBUG_STATE==1␊
31#define DBG(x...) printf(x)␊
32#else␊
33#define DBG(x...) msglog(x)␊
34#endif␊
35␊
36uint8_t acpi_cpu_count␉= 0;␊
37uint32_t acpi_cpu_p_blk␉= 0;␊
38char *acpi_cpu_name[32];␊
39␊
40void get_acpi_cpu_names(unsigned char *dsdt, uint32_t length)␊
41{␊
42␉uint32_t i;␊
43␊
44␉DBG("ACPIpatcher: start finding cpu names. Length %d\n", length);␊
45␊
46␉for (i=0; i<length-7; i++)␊
47␉{␊
48␉␉if (dsdt[i] == 0x5B && dsdt[i+1] == 0x83) // ProcessorOP␊
49␉␉{␊
50␉␉␉DBG("ACPIpatcher: DSDT[%X%X]\n", dsdt[i], dsdt[i+1]);␊
51␊
52␉␉␉uint32_t offset = i + 3 + (dsdt[i+2] >> 6);␊
53␊
54␉␉␉bool add_name = true;␊
55␊
56␉␉␉uint8_t j;␊
57␊
58␉␉␉for (j=0; j<4; j++)␊
59␉␉␉{␊
60␉␉␉␉char c = dsdt[offset+j];␊
61␊
62␉␉␉␉if (!aml_isvalidchar(c))␊
63␉␉␉␉{␊
64␉␉␉␉␉add_name = false;␊
65␉␉␉␉␉DBG("ACPIpatcher: invalid character found in ProcessorOP '0x%X'!\n", c);␊
66␉␉␉␉␉break;␊
67␉␉␉␉}␊
68␉␉␉}␊
69␊
70␉␉␉if (add_name)␊
71␉␉␉{␊
72␉␉␉␉acpi_cpu_name[acpi_cpu_count] = malloc(4);␊
73␉␉␉␉memcpy(acpi_cpu_name[acpi_cpu_count], dsdt+offset, 4);␊
74␉␉␉␉i = offset + 5;␊
75␊
76␉␉␉␉if (acpi_cpu_count == 0)␊
77␉␉␉␉{␊
78␉␉␉␉␉acpi_cpu_p_blk = dsdt[i] | (dsdt[i+1] << 8);␊
79␉␉␉␉}␊
80␊
81␉␉␉␉DBG("ACPIpatcher: found ACPI CPU [%c%c%c%c]\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);␊
82␊
83␉␉␉␉if (++acpi_cpu_count == 32)␊
84␉␉␉␉{␊
85␉␉␉␉␉return;␊
86␉␉␉␉}␊
87␉␉␉}␊
88␉␉}␊
89␉}␊
90␊
91␉DBG("ACPIpatcher: finished finding cpu names. Found: %d.\n", acpi_cpu_count);␊
92}␊
93␊
94static char const pss_ssdt_header[] =␊
95{␊
96␉0x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */␊
97␉0x01, 0x6A, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x00, /* ..PmRef. */␊
98␉0x43, 0x70, 0x75, 0x50, 0x6D, 0x00, 0x00, 0x00, /* CpuPm... */␊
99␉0x00, 0x30, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* .0..INTL */␊
100␉0x31, 0x03, 0x10, 0x20,␉␉␉␉/* 1.._␉␉*/␊
101};␊
102␊
103static char const cst_ssdt_header[] =␊
104{␊
105␉0x53, 0x53, 0x44, 0x54, 0xE7, 0x00, 0x00, 0x00, /* SSDT.... */␊
106␉0x01, 0x17, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x41, /* ..PmRefA */␊
107␉0x43, 0x70, 0x75, 0x43, 0x73, 0x74, 0x00, 0x00, /* CpuCst.. */␊
108␉0x00, 0x10, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* ....INTL */␊
109␉0x31, 0x03, 0x10, 0x20␉␉␉␉/* 1.._␉␉*/␊
110};␊
111␊
112char resource_template_register_fixedhw[] =␊
113{␊
114␉0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F,␊
115␉0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
116␉0x00, 0x00, 0x01, 0x79, 0x00␊
117};␊
118␊
119char resource_template_register_systemio[] =␊
120{␊
121␉0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x01,␊
122␉0x08, 0x00, 0x00, 0x15, 0x04, 0x00, 0x00, 0x00,␊
123␉0x00, 0x00, 0x00, 0x79, 0x00,␊
124};␊
125␊
126struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt *dsdt)␊
127{␊
128␊
129␉if (Platform.CPU.Vendor != CPUID_VENDOR_INTEL) // 0x756E6547␊
130␉{␊
131␉␉DBG("Not an Intel platform: P-States will not be generated !!!\n");␊
132␉␉return NULL;␊
133␉}␊
134␊
135␉if (!(Platform.CPU.Features & CPU_FEATURE_MSR))␊
136␉{␊
137␉␉DBG("Unsupported CPU: P-States will not be generated !!! No MSR support\n");␊
138␉␉return NULL;␊
139␉}␊
140␊
141␉if (acpi_cpu_count == 0)␊
142␉{␊
143␉␉get_acpi_cpu_names((void*)dsdt, dsdt->Length);␊
144␉}␊
145␊
146␉if (acpi_cpu_count > 0)␊
147␉{␊
148␉␉struct p_state initial, maximum, minimum, p_states[32];␊
149␉␉uint8_t p_states_count = 0;␊
150␊
151␉␉// Retrieving P-States, ported from code by superhai (c)␊
152␉␉switch (Platform.CPU.Family)␊
153␉␉{␊
154␉␉␉case 0x06:␊
155␉␉␉{␊
156␉␉␉␉switch (Platform.CPU.Model)␊
157␉␉␉␉{␊
158␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
159␉␉␉␉␉case CPUID_MODEL_YONAH:␉// Intel Mobile Core Solo, Duo␊
160␉␉␉␉␉case CPUID_MODEL_MEROM:␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
161␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
162␉␉␉␉␉case CPUID_MODEL_ATOM:␉// Intel Atom (45nm)␊
163␉␉␉␉␉{␊
164␉␉␉␉␉␉bool cpu_dynamic_fsb = false;␊
165␊
166␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊
167␉␉␉␉␉␉{␊
168␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28))); ␊
169␉␉␉␉␉␉␉delay(1);␊
170␉␉␉␉␉␉␉cpu_dynamic_fsb = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊
171␉␉␉␉␉␉}␊
172␊
173␉␉␉␉␉␉bool cpu_noninteger_bus_ratio = (rdmsr64(MSR_IA32_PERF_STATUS) & (1ULL << 46));␊
174␊
175␉␉␉␉␉␉initial.Control = rdmsr64(MSR_IA32_PERF_STATUS);␊
176␊
177␉␉␉␉␉␉maximum.Control = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 32) & 0x1F3F) | (0x4000 * cpu_noninteger_bus_ratio);␊
178␉␉␉␉␉␉maximum.CID = ((maximum.FID & 0x1F) << 1) | cpu_noninteger_bus_ratio;␊
179␊
180␉␉␉␉␉␉minimum.FID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 24) & 0x1F) | (0x80 * cpu_dynamic_fsb);␊
181␉␉␉␉␉␉minimum.VID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 48) & 0x3F);␊
182␊
183␉␉␉␉␉␉if (minimum.FID == 0)␊
184␉␉␉␉␉␉{␊
185␉␉␉␉␉␉␉uint64_t msr;␊
186␉␉␉␉␉␉␉uint8_t i;␊
187␉␉␉␉␉␉␉// Probe for lowest fid␊
188␉␉␉␉␉␉␉for (i = maximum.FID; i >= 0x6; i--)␊
189␉␉␉␉␉␉␉{␊
190␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
191␉␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (i << 8) | minimum.VID);␊
192␉␉␉␉␉␉␉␉intel_waitforsts();␊
193␉␉␉␉␉␉␉␉minimum.FID = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0x1F; ␊
194␉␉␉␉␉␉␉␉delay(1);␊
195␉␉␉␉␉␉␉}␊
196␊
197␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
198␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);␊
199␉␉␉␉␉␉␉intel_waitforsts();␊
200␉␉␉␉␉␉}␊
201␊
202␉␉␉␉␉␉if (minimum.VID == maximum.VID) ␊
203␉␉␉␉␉␉{␊
204␉␉␉␉␉␉␉uint64_t msr;␊
205␉␉␉␉␉␉␉uint8_t i;␊
206␉␉␉␉␉␉␉// Probe for lowest vid␊
207␉␉␉␉␉␉␉for (i = maximum.VID; i > 0xA; i--) ␊
208␉␉␉␉␉␉␉{␊
209␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
210␉␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (minimum.FID << 8) | i);␊
211␉␉␉␉␉␉␉␉intel_waitforsts();␊
212␉␉␉␉␉␉␉␉minimum.VID = rdmsr64(MSR_IA32_PERF_STATUS) & 0x3F; ␊
213␉␉␉␉␉␉␉␉delay(1);␊
214␉␉␉␉␉␉␉}␊
215␊
216␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
217␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);␊
218␉␉␉␉␉␉␉intel_waitforsts();␊
219␉␉␉␉␉␉}␊
220␊
221␉␉␉␉␉␉minimum.CID = ((minimum.FID & 0x1F) << 1) >> cpu_dynamic_fsb;␊
222␊
223␉␉␉␉␉␉// Sanity check␊
224␉␉␉␉␉␉if (maximum.CID < minimum.CID)␊
225␉␉␉␉␉␉{␊
226␉␉␉␉␉␉␉DBG("P-States: Insane FID values!");␊
227␉␉␉␉␉␉␉p_states_count = 0;␊
228␉␉␉␉␉␉}␊
229␉␉␉␉␉␉else␊
230␉␉␉␉␉␉{␊
231␉␉␉␉␉␉␉uint8_t vidstep;␊
232␉␉␉␉␉␉␉uint8_t u, invalid = 0;␊
233␉␉␉␉␉␉␉// Finalize P-States␊
234␉␉␉␉␉␉␉// Find how many P-States machine supports␊
235␉␉␉␉␉␉␉p_states_count = (uint8_t)(maximum.CID - minimum.CID + 1);␊
236␊
237␉␉␉␉␉␉␉if (p_states_count > 32)␊
238␉␉␉␉␉␉␉{␊
239␉␉␉␉␉␉␉␉p_states_count = 32;␊
240␉␉␉␉␉␉␉}␊
241␊
242␉␉␉␉␉␉␉vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1);␊
243␊
244␉␉␉␉␉␉␉for (u = 0; u < p_states_count; u++)␊
245␉␉␉␉␉␉␉{␊
246␉␉␉␉␉␉␉␉uint8_t i = u - invalid;␊
247␊
248␉␉␉␉␉␉␉␉p_states[i].CID = maximum.CID - u;␊
249␉␉␉␉␉␉␉␉p_states[i].FID = (uint8_t)(p_states[i].CID >> 1);␊
250␊
251␉␉␉␉␉␉␉␉if (p_states[i].FID < 0x6)␊
252␉␉␉␉␉␉␉␉{␊
253␉␉␉␉␉␉␉␉␉if (cpu_dynamic_fsb)␊
254␉␉␉␉␉␉␉␉␉{␊
255␉␉␉␉␉␉␉␉␉␉p_states[i].FID = (p_states[i].FID << 1) | 0x80;␊
256␉␉␉␉␉␉␉␉␉}␊
257␉␉␉␉␉␉␉␉}␊
258␉␉␉␉␉␉␉␉else if (cpu_noninteger_bus_ratio)␊
259␉␉␉␉␉␉␉␉{␊
260␉␉␉␉␉␉␉␉␉p_states[i].FID = p_states[i].FID | (0x40 * (p_states[i].CID & 0x1));␊
261␉␉␉␉␉␉␉␉}␊
262␊
263␉␉␉␉␉␉␉␉if (i && p_states[i].FID == p_states[i-1].FID)␊
264␉␉␉␉␉␉␉␉{␊
265␉␉␉␉␉␉␉␉␉invalid++;␊
266␉␉␉␉␉␉␉␉}␊
267␉␉␉␉␉␉␉␉p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2;␊
268␉␉␉␉␉␉␉␉uint32_t multiplier = p_states[i].FID & 0x1f;␉␉// = 0x08␊
269␉␉␉␉␉␉␉␉bool half = p_states[i].FID & 0x40;␉␉␉␉␉// = 0x01␊
270␉␉␉␉␉␉␉␉bool dfsb = p_states[i].FID & 0x80;␉␉␉␉␉// = 0x00␊
271␉␉␉␉␉␉␉␉uint32_t fsb = (uint32_t)(Platform.CPU.FSBFrequency / 1000000); // = 400␊
272␉␉␉␉␉␉␉␉uint32_t halffsb = (fsb + 1) >> 1;␉␉␉␉␉// = 200␊
273␉␉␉␉␉␉␉␉uint32_t frequency = (multiplier * fsb);␉␉␉// = 3200␊
274␊
275␉␉␉␉␉␉␉␉p_states[i].Frequency = (uint32_t)(frequency + (half * halffsb)) >> dfsb;␉// = 3200 + 200 = 3400␊
276␉␉␉␉␉␉␉}␊
277␊
278␉␉␉␉␉␉␉p_states_count -= invalid;␊
279␉␉␉␉␉␉}␊
280␊
281␉␉␉␉␉␉break;␊
282␉␉␉␉␉}␊
283␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
284␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉//␊
285␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
286␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
287␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
288␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
289␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊
290␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
291␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
292␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
293␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉//␊
294␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉//␊
295␉␉␉␉␉//case CPUID_MODEL_HASWELL_H:␉␉//␊
296␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉//␊
297␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉//␊
298␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉//␊
299␊
300␉␉␉␉␉{␊
301␉␉␉␉␉if ( (Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE) ||␊
302␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_JAKETOWN) ||␊
303␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE) ||␊
304␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_HASWELL) ||␊
305␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE_XEON) ||␊
306␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_HASWELL_SVR) ||␊
307␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_HASWELL_ULT) ||␊
308␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_CRYSTALWELL) )␊
309␉␉␉␉␉{␊
310␉␉␉␉␉␉maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
311␉␉␉␉␉}␊
312␉␉␉␉␉else␊
313␉␉␉␉␉{␊
314␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff;␊
315␉␉␉␉␉}␊
316␊
317␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
318␊
319␉␉␉␉␉DBG("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);␊
320␊
321␉␉␉␉␉// Sanity check␊
322␉␉␉␉␉if (maximum.Control < minimum.Control)␊
323␉␉␉␉␉{␊
324␉␉␉␉␉␉DBG("Insane control values!");␊
325␉␉␉␉␉␉p_states_count = 0;␊
326␉␉␉␉␉}␊
327␉␉␉␉␉else␊
328␉␉␉␉␉{␊
329␉␉␉␉␉␉uint8_t i;␊
330␉␉␉␉␉␉p_states_count = 0;␊
331␊
332␉␉␉␉␉␉for (i = maximum.Control; i >= minimum.Control; i--)␊
333␉␉␉␉␉␉{␊
334␉␉␉␉␉␉␉p_states[p_states_count].Control = i;␊
335␉␉␉␉␉␉␉p_states[p_states_count].CID = p_states[p_states_count].Control << 1;␊
336␉␉␉␉␉␉␉p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i;␊
337␉␉␉␉␉␉␉p_states_count++;␊
338␉␉␉␉␉␉}␊
339␉␉␉␉␉}␊
340␊
341␉␉␉␉␉break;␊
342␉␉␉␉}␊
343␉␉␉␉default:␊
344␉␉␉␉␉DBG("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);␊
345␉␉␉␉␉break;␊
346␉␉␉}␊
347␉␉}␊
348␉}␊
349␊
350␉// Generating SSDT␊
351␉if (p_states_count > 0)␊
352␉{␊
353␊
354␉␉int i;␊
355␊
356␉␉AML_CHUNK* root = aml_create_node(NULL);␊
357␉␉aml_add_buffer(root, pss_ssdt_header, sizeof(pss_ssdt_header)); // SSDT header␊
358␊
359␉␉AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");␊
360␉␉AML_CHUNK* name = aml_add_name(scop, "PSS_");␊
361␉␉AML_CHUNK* pack = aml_add_package(name);␊
362␊
363␉␉for (i = 0; i < p_states_count; i++)␊
364␉␉{␊
365␉␉␉AML_CHUNK* pstt = aml_add_package(pack);␊
366␊
367␉␉␉aml_add_dword(pstt, p_states[i].Frequency);␊
368␉␉␉aml_add_dword(pstt, 0x00000000); // Power␊
369␉␉␉aml_add_dword(pstt, 0x0000000A); // Latency␊
370␉␉␉aml_add_dword(pstt, 0x0000000A); // Latency␊
371␉␉␉aml_add_dword(pstt, p_states[i].Control);␊
372␉␉␉aml_add_dword(pstt, i+1); // Status␊
373␉␉}␊
374␊
375␉␉␉// Add aliaces␊
376␉␉␉for (i = 0; i < acpi_cpu_count; i++)␊
377␉␉␉{␊
378␉␉␉␉char name[9];␊
379␉␉␉␉sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);␊
380␊
381␉␉␉␉scop = aml_add_scope(root, name);␊
382␉␉␉␉aml_add_alias(scop, "PSS_", "_PSS");␊
383␉␉␉}␊
384␊
385␉␉␉aml_calculate_size(root);␊
386␊
387␉␉␉struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);␊
388␊
389␉␉␉aml_write_node(root, (void*)ssdt, 0);␊
390␊
391␉␉␉ssdt->Length = root->Size;␊
392␉␉␉ssdt->Checksum = 0;␊
393␉␉␉ssdt->Checksum = (uint8_t)(256 - checksum8(ssdt, ssdt->Length));␊
394␊
395␉␉␉aml_destroy_node(root);␊
396␊
397␉␉␉//dumpPhysAddr("P-States SSDT content: ", ssdt, ssdt->Length);␊
398␊
399␉␉␉DBG("SSDT with CPU P-States generated successfully\n");␊
400␊
401␉␉␉return ssdt;␊
402␉␉}␊
403␉}␊
404␉else␊
405␉{␊
406␉␉DBG("ACPI CPUs not found: P-States not generated !!!\n");␊
407␉}␊
408␊
409␉return NULL;␊
410}␊
411␊
412struct acpi_2_ssdt *generate_cst_ssdt(struct acpi_2_fadt *fadt)␊
413{␊
414␊
415␉if (Platform.CPU.Vendor != CPUID_VENDOR_INTEL) // 0x756E6547␊
416␉{␊
417␉␉DBG("Not an Intel platform: C-States will not be generated !!!\n");␊
418␉␉return NULL;␊
419␉}␊
420␊
421␉if (fadt == NULL)␊
422␉{␊
423␉␉DBG("FACP not exists: C-States will not be generated !!!\n");␊
424␉␉return NULL;␊
425␉}␊
426␊
427␉struct acpi_2_dsdt *dsdt = (void *)fadt->DSDT;␊
428␊
429␉if (dsdt == NULL)␊
430␉{␊
431␉␉DBG("DSDT not found: C-States will not be generated !!!\n");␊
432␉␉return NULL;␊
433␉}␊
434␊
435␉if (acpi_cpu_count == 0)␊
436␉␉get_acpi_cpu_names((void*)dsdt, dsdt->Length);␊
437␊
438␉if (acpi_cpu_count > 0)␊
439␉{␊
440␉␉bool c2_enabled = false;␊
441␉␉bool c3_enabled = false;␊
442␉␉bool c4_enabled = false;␊
443␉␉bool c6_enabled = false;␊
444␉␉bool c7_enabled = false;␊
445␉␉bool cst_using_systemio = false;␊
446␊
447␉␉getBoolForKey(kEnableC2State, &c2_enabled, &bootInfo->chameleonConfig);␊
448␉␉getBoolForKey(kEnableC3State, &c3_enabled, &bootInfo->chameleonConfig);␊
449␉␉getBoolForKey(kEnableC4State, &c4_enabled, &bootInfo->chameleonConfig);␊
450␉␉getBoolForKey(kEnableC6State, &c6_enabled, &bootInfo->chameleonConfig);␊
451␉␉getBoolForKey(kEnableC7State, &c7_enabled, &bootInfo->chameleonConfig);␊
452␉␉getBoolForKey(kCSTUsingSystemIO, &cst_using_systemio, &bootInfo->chameleonConfig);␊
453␊
454␉␉c2_enabled = c2_enabled | (fadt->C2_Latency < 100);␊
455␉␉c3_enabled = c3_enabled | (fadt->C3_Latency < 1000);␊
456␊
457␉␉unsigned char cstates_count = 1 + (c2_enabled ? 1 : 0) + ((c3_enabled || c4_enabled)? 1 : 0) + (c6_enabled ? 1 : 0) + (c7_enabled ? 1 : 0);␊
458␊
459␉␉AML_CHUNK* root = aml_create_node(NULL);␊
460␉␉aml_add_buffer(root, cst_ssdt_header, sizeof(cst_ssdt_header)); // SSDT header␊
461␉␉AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");␊
462␉␉AML_CHUNK* name = aml_add_name(scop, "CST_");␊
463␉␉AML_CHUNK* pack = aml_add_package(name);␊
464␉␉aml_add_byte(pack, cstates_count);␊
465␊
466␉␉AML_CHUNK* tmpl = aml_add_package(pack);␊
467␉␉if (cst_using_systemio)␊
468␉␉{␊
469␉␉␉// C1␊
470␉␉␉resource_template_register_fixedhw[8] = 0x00;␊
471␉␉␉resource_template_register_fixedhw[9] = 0x00;␊
472␉␉␉resource_template_register_fixedhw[18] = 0x00;␊
473␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
474␉␉␉aml_add_byte(tmpl, 0x01);␉␉// C1␊
475␉␉␉aml_add_word(tmpl, 0x0001);␉␉// Latency␊
476␉␉␉aml_add_dword(tmpl, 0x000003e8);␉// Power␊
477␊
478␉␉␉uint8_t p_blk_lo, p_blk_hi;␊
479␊
480␉␉␉if (c2_enabled) // C2␊
481␉␉␉{␊
482␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 4;␊
483␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 4) >> 8;␊
484␊
485␉␉␉␉tmpl = aml_add_package(pack);␊
486␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C2␊
487␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C2␊
488␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
489␉␉␉␉aml_add_byte(tmpl, 0x02);␉␉// C2␊
490␉␉␉␉aml_add_word(tmpl, 0x0040);␉␉// Latency␊
491␉␉␉␉aml_add_dword(tmpl, 0x000001f4);␉// Power␊
492␉␉␉}␊
493␊
494␉␉␉if (c4_enabled) // C4␊
495␉␉␉{␊
496␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 5;␊
497␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;␊
498␊
499␉␉␉␉tmpl = aml_add_package(pack);␊
500␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C4␊
501␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C4␊
502␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
503␉␉␉␉aml_add_byte(tmpl, 0x04);␉␉// C4␊
504␉␉␉␉aml_add_word(tmpl, 0x0080);␉␉// Latency␊
505␉␉␉␉aml_add_dword(tmpl, 0x000000C8);␉// Power␊
506␉␉␉}␊
507␉␉␉else if (c3_enabled) // C3␊
508␉␉␉{␊
509␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 5;␊
510␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;␊
511␊
512␉␉␉␉tmpl = aml_add_package(pack);␊
513␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C3␊
514␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C3␊
515␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
516␉␉␉␉aml_add_byte(tmpl, 0x03);␉␉// C3␊
517␉␉␉␉aml_add_word(tmpl, 0x0043);␉␉// Latency␊
518␉␉␉␉aml_add_dword(tmpl, 0x000001F4);␉// Power␊
519␉␉␉}␊
520␉␉␉if (c6_enabled) // C6␊
521␉␉␉{␊
522␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 5;␊
523␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;␊
524␊
525␉␉␉␉tmpl = aml_add_package(pack);␊
526␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C6␊
527␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C6␊
528␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
529␉␉␉␉aml_add_byte(tmpl, 0x06);␉␉␉// C6␊
530␉␉␉␉aml_add_word(tmpl, 0x0046);␉␉␉// Latency␊
531␉␉␉␉aml_add_dword(tmpl, 0x0000015E);␉␉// Power␊
532␉␉␉}␊
533␉␉␉if (c7_enabled) //C7␊
534␉␉␉{␊
535␉␉␉␉p_blk_lo = (acpi_cpu_p_blk + 6) & 0xff;␊
536␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;␊
537␊
538␉␉␉␉tmpl = aml_add_package(pack);␊
539␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C4 or C7␊
540␉␉␉␉resource_template_register_systemio[12] = p_blk_hi;␊
541␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
542␉␉␉␉aml_add_byte(tmpl, 0x07);␉␉␉// C7␊
543␉␉␉␉aml_add_word(tmpl, 0xF5);␉␉␉// Latency as in iMac14,1␊
544␉␉␉␉aml_add_dword(tmpl, 0xC8);␉␉␉// Power␊
545␉␉␉}␊
546␉␉}␊
547␉␉else␊
548␉␉{␊
549␉␉␉// C1␊
550␉␉␉resource_template_register_fixedhw[8] = 0x01;␊
551␉␉␉resource_template_register_fixedhw[9] = 0x02;␊
552␉␉␉resource_template_register_fixedhw[18] = 0x01;␊
553␊
554␉␉␉resource_template_register_fixedhw[11] = 0x00; // C1␊
555␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
556␉␉␉aml_add_byte(tmpl, 0x01);␉␉// C1␊
557␉␉␉aml_add_word(tmpl, 0x0001);␉␉// Latency␊
558␉␉␉aml_add_dword(tmpl, 0x000003e8);␉// Power␊
559␊
560␉␉␉resource_template_register_fixedhw[18] = 0x03;␊
561␊
562␉␉␉if (c2_enabled) // C2␊
563␉␉␉{␊
564␉␉␉␉tmpl = aml_add_package(pack);␊
565␉␉␉␉resource_template_register_fixedhw[11] = 0x10; // C2␊
566␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
567␉␉␉␉aml_add_byte(tmpl, 0x02);␉␉// C2␊
568␉␉␉␉aml_add_word(tmpl, 0x0040);␉␉// Latency␊
569␉␉␉␉aml_add_dword(tmpl, 0x000001f4);␉// Power␊
570␉␉␉}␊
571␊
572␉␉␉if (c4_enabled) // C4␊
573␉␉␉{␊
574␉␉␉␉tmpl = aml_add_package(pack);␊
575␉␉␉␉resource_template_register_fixedhw[11] = 0x30; // C4␊
576␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
577␉␉␉␉aml_add_byte(tmpl, 0x04);␉␉// C4␊
578␉␉␉␉aml_add_word(tmpl, 0x0080);␉␉// Latency␊
579␉␉␉␉aml_add_dword(tmpl, 0x000000C8);␉// Power␊
580␉␉␉}␊
581␉␉␉else if (c3_enabled)␊
582␉␉␉{␊
583␉␉␉␉tmpl = aml_add_package(pack);␊
584␉␉␉␉resource_template_register_fixedhw[11] = 0x20; // C3␊
585␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
586␉␉␉␉aml_add_byte(tmpl, 0x03);␉␉// C3␊
587␉␉␉␉aml_add_word(tmpl, 0x0043);␉␉// Latency␊
588␉␉␉␉aml_add_dword(tmpl, 0x000001F4);␉// Power␊
589␉␉␉}␊
590␉␉␉if (c6_enabled) // C6␊
591␉␉␉{␊
592␉␉␉␉tmpl = aml_add_package(pack);␊
593␉␉␉␉resource_template_register_fixedhw[11] = 0x20; // C6␊
594␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
595␉␉␉␉aml_add_byte(tmpl, 0x06);␉␉␉// C6␊
596␉␉␉␉aml_add_word(tmpl, 0x0046);␉␉␉// Latency as in MacPro6,1␊
597␉␉␉␉aml_add_dword(tmpl, 0x0000015E);␉// Power␊
598␉␉␉}␊
599␉␉␉if (c7_enabled) // C7␊
600␉␉␉{␊
601␉␉␉␉tmpl = aml_add_package(pack);␊
602␉␉␉␉resource_template_register_fixedhw[11] = 0x30; // C4 or C7␊
603␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
604␉␉␉␉aml_add_byte(tmpl, 0x07);␉␉␉// C7␊
605␉␉␉␉aml_add_word(tmpl, 0xF5);␉␉␉// Latency as in iMac14,1␊
606␉␉␉␉aml_add_dword(tmpl, 0xC8);␉// Power␊
607␉␉␉}␊
608␉␉}␊
609␊
610␉␉// Aliaces␊
611␉␉int i;␊
612␉␉for (i = 0; i < acpi_cpu_count; i++)␊
613␉␉{␊
614␉␉␉char name[9];␊
615␉␉␉sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);␊
616␊
617␉␉␉scop = aml_add_scope(root, name);␊
618␉␉␉aml_add_alias(scop, "CST_", "_CST");␊
619␉␉}␊
620␊
621␉␉aml_calculate_size(root);␊
622␊
623␉␉struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);␊
624␊
625␉␉aml_write_node(root, (void*)ssdt, 0);␊
626␊
627␉␉ssdt->Length = root->Size;␊
628␉␉ssdt->Checksum = 0;␊
629␉␉ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);␊
630␊
631␉␉aml_destroy_node(root);␊
632␊
633␉␉// dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length);␊
634␊
635␉␉DBG("SSDT with CPU C-States generated successfully\n");␊
636␊
637␉␉return ssdt;␊
638␉}␊
639␉else␊
640␉{␊
641␉␉DBG("ACPI CPUs not found: C-States not generated !!!\n");␊
642␉}␊
643␊
644␉return NULL;␊
645}␊
646

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