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Root/branches/Chimera/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"", /* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"", /* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"", /* 09h Undefined */␊
40␉"", /* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
73␊
74unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
75{␊
76␉int l1, h1, l2, h2;␊
77␉unsigned long long t;␊
78␊
79␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
80␉outb(base + SMBHSTDAT, 0xff);␊
81␊
82␉rdtsc(l1, h1);␊
83␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
84␉{␊
85␉␉rdtsc(l2, h2);␊
86␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
87␉␉if (t > 5)␊
88␉␉{␊
89␉␉␉return 0xFF;␉// break␊
90␉␉}␊
91␉}␊
92␊
93␉outb(base + SMBHSTCMD, cmd);␊
94␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
95␉outb(base + SMBHSTCNT, 0x48 );␊
96␊
97␉rdtsc(l1, h1);␊
98␊
99␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
100␉{␊
101␉␉rdtsc(l2, h2);␊
102␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
103␉␉if (t > 5)␊
104␉␉{␊
105␉␉␉break;␉// break after 5ms␊
106␉␉}␊
107␉}␊
108␉return inb(base + SMBHSTDAT);␊
109}␊
110␊
111/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
112#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
113␊
114int spd_indexes[] = {␊
115␉SPD_MEMORY_TYPE,␊
116␉SPD_DDR3_MEMORY_BANK,␊
117␉SPD_DDR3_MEMORY_CODE,␊
118␉SPD_NUM_ROWS,␊
119␉SPD_NUM_COLUMNS,␊
120␉SPD_NUM_DIMM_BANKS,␊
121␉SPD_NUM_BANKS_PER_SDRAM,␊
122␉4,7,8,9,12,64, /* TODO: give names to these values */␊
123␉95,96,97,98, 122,123,124,125 /* UIS */␊
124};␊
125#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
126␊
127/** Read from spd *used* values only*/␊
128static void init_spd(char * spd, uint32_t base, int slot)␊
129{␊
130␉int i;␊
131␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
132␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
133␉}␊
134}␊
135␊
136/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
137 have different formats, always return a valid ptr.*/␊
138const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
139{␊
140␉uint8_t bank = 0;␊
141␉uint8_t code = 0;␊
142␉int i = 0;␊
143␉uint8_t * spd = (uint8_t *) slot->spd;␊
144␊
145␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
146␉{ // DDR3␊
147␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
148␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
149␉␉for (i=0; i < VEN_MAP_SIZE; i++) {␊
150␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code) {␊
151␉␉␉␉return vendorMap[i].name;␊
152␉␉␉}␊
153␉␉}␊
154␉} else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) {␊
155␉␉if(spd[64]==0x7f) {␊
156␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++) {␊
157␉␉␉␉bank++;␊
158␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
159␉␉␉}␊
160␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
161␉␉␉code = spd[i];␊
162␉␉} else {␊
163␉␉␉code = spd[64]; ␊
164␉␉␉bank = 0;␊
165␉␉}␊
166␉␉for (i=0; i < VEN_MAP_SIZE; i++) {␊
167␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code) {␊
168␉␉␉␉return vendorMap[i].name;␊
169␉␉␉}␊
170␉␉}␊
171␉}␊
172␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
173␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊
174␉␉return "Unifosa";␊
175␉}␊
176␉return "NoName";␊
177}␊
178␊
179/* Get Default Memory Module Speed (no overclocking handled) */␊
180int getDDRspeedMhz(const char * spd)␊
181{␊
182␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
183␉␉switch(spd[12]) {␊
184␉␉␉case 0x0f:␊
185␉␉␉␉return 1066;␊
186␉␉␉case 0x0c:␊
187␉␉␉␉return 1333;␊
188␉␉␉case 0x0a:␊
189␉␉␉␉return 1600;␊
190␉␉␉case 0x14:␊
191␉␉␉default:␊
192␉␉␉␉return 800;␊
193␉␉}␊
194␉} else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) {␊
195␉␉switch(spd[9]) {␊
196␉␉␉case 0x50:␊
197␉␉␉␉return 400;␊
198␉␉␉case 0x3d:␊
199␉␉␉␉return 533;␊
200␉␉␉case 0x30:␊
201␉␉␉␉return 667;␊
202␉␉␉case 0x25:␊
203␉␉␉default:␊
204␉␉␉␉return 800;␊
205␉␉␉case 0x1E:␊
206␉␉␉␉return 1066;␊
207␉␉}␊
208␉}␊
209␉return 800; // default freq for unknown types␊
210}␊
211␊
212#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
213#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
214␊
215/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
216const char *getDDRSerial(const char* spd)␊
217{␊
218␉static char asciiSerial[16];␊
219␊
220␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
221␉{␊
222␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
223␉}␊
224␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
225␉{␊
226␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
227␉} else {␊
228␉␉sprintf(asciiSerial, "000000000000000");␊
229␉}␊
230␊
231␉return strdup(asciiSerial);␊
232}␊
233␊
234/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
235const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
236{␊
237␉static char asciiPartNo[32];␊
238␉int i, start=0, index = 0;␊
239␊
240␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
241␉␉start = 128;␊
242␉} else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) {␊
243␉␉start = 73;␊
244␉}␊
245␉␊
246␉// Check that the spd part name is zero terminated and that it is ascii:␊
247␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
248␉char c;␊
249␉for (i=start; i < start + sizeof(asciiPartNo); i++) {␊
250␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
251␉␉c = spd[i];␊
252␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) {␊
253␉␉␉// It seems that System Profiler likes only letters and digits...␊
254␉␉␉asciiPartNo[index++] = c;␊
255␉␉} else if (!isascii(c)) {␊
256␉␉␉break;␊
257␉␉}␊
258␉}␊
259␊
260␉return strdup(asciiPartNo);␊
261}␊
262␊
263int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
264␊
265␊
266/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
267static void read_smb_intel(pci_dt_t *smbus_dev) {␊
268␉int i, speed;␊
269␉uint8_t spd_size, spd_type;␊
270␉uint32_t base, mmio, hostc;␊
271//␉bool dump = false;␊
272␉RamSlotInfo_t* slot;␊
273␊
274␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
275␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
276␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
277␊
278␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
279␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
280␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
281␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
282␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
283␊
284␉//Azi: no use for this!␊
285␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
286␉// needed at least for laptops␊
287␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
288␊
289␉char spdbuf[MAX_SPD_SIZE];␊
290␉// Search MAX_RAM_SLOTS slots␊
291␉for (i = 0; i < MAX_RAM_SLOTS; i++) {␊
292␉␉slot = &Platform.RAM.DIMM[i];␊
293␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
294␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
295␉␉// Check spd is present␊
296␉␉if (spd_size && (spd_size != 0xff)) {␊
297␊
298␉␉␉slot->spd = spdbuf;␊
299␉␉␉slot->InUse = true;␊
300␊
301␉␉␉bzero(slot->spd, spd_size);␊
302␊
303␉␉␉// Copy spd data into buffer␊
304␊
305␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
306␉␉␉init_spd(slot->spd, base, i);␊
307␊
308␉␉␉switch (slot->spd[SPD_MEMORY_TYPE]) {␊
309␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
310␊
311␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
312 + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
313 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
314 slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
315␉␉␉␉break;␊
316␊
317␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
318␊
319␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
320␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
321␉␉␉␉break;␊
322␊
323␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
324␊
325␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
326␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
327␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
328␊
329␉␉␉␉break;␊
330␉␉␉}␊
331␊
332␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
333␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
334␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE) {␊
335␉␉␉␉continue;␊
336␉␉␉}␊
337␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
338␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
339␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
340␊
341␉␉␉// determine spd speed␊
342␉␉␉speed = getDDRspeedMhz(slot->spd);␊
343␉␉␉if (slot->Frequency < speed) {␊
344␉␉␉␉slot->Frequency = speed;␊
345␉␉␉}␊
346␊
347␉␉␉// pci memory controller if available, is more reliable␊
348␉␉␉if (Platform.RAM.Frequency > 0) {␊
349␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
350␉␉␉␉// now round off special cases␊
351␉␉␉␉uint32_t fmod100 = freq %100;␊
352␉␉␉␉switch(fmod100) {␊
353␉␉␉␉␉case 1:␉freq--;␉break;␊
354␉␉␉␉␉case 32:␉freq++;␉break;␊
355␉␉␉␉␉case 65:␉freq++; break;␊
356␉␉␉␉␉case 98:␉freq+=2;break;␊
357␉␉␉␉␉case 99:␉freq++; break;␊
358␉␉␉␉}␊
359␉␉␉␉slot->Frequency = freq;␊
360␉␉␉}␊
361␊
362␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
363 i,␊
364 (int)slot->Type,␊
365 slot->ModuleSize, ␊
366 spd_memory_types[spd_type],␊
367 slot->Frequency,␊
368 slot->Vendor,␊
369 slot->PartNo,␊
370 slot->SerialNo);␊
371 slot->InUse = true;␊
372␉␉}␊
373␊
374␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
375␉␉Platform.DMI.DIMM[i]= ␊
376 ␉(uint32_t)((i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2) ?␊
377 ␉mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
378␉␉slot->spd = NULL;␊
379␊
380␉} // for␊
381}␊
382␊
383static struct smbus_controllers_t smbus_controllers[] = {␊
384␊
385 {0x8086, 0x1C22, "6 Series/C200 Series", read_smb_intel },␊
386 {0x8086, 0x1C41, "Mobile 6 Series", read_smb_intel },␊
387 {0x8086, 0x1C42, "6 Series/C200 Series", read_smb_intel },␊
388 {0x8086, 0x1C43, "Mobile 6 Series", read_smb_intel },␊
389 {0x8086, 0x1C44, "6 Series", read_smb_intel },␊
390 {0x8086, 0x1C46, "6 Series", read_smb_intel },␊
391 {0x8086, 0x1C47, "6 Series", read_smb_intel },␊
392 {0x8086, 0x1C49, "Mobile 6 Series", read_smb_intel },␊
393 {0x8086, 0x1C4A, "6 Series", read_smb_intel },␊
394 {0x8086, 0x1C4B, "Mobile 6 Series", read_smb_intel },␊
395 {0x8086, 0x1C4C, "6 Series", read_smb_intel },␊
396 {0x8086, 0x1C4D, "6 Series", read_smb_intel },␊
397 {0x8086, 0x1C4E, "6 Series", read_smb_intel },␊
398 {0x8086, 0x1C4F, "Mobile 6 Series", read_smb_intel },␊
399 {0x8086, 0x1C50, "6 Series", read_smb_intel },␊
400 {0x8086, 0x1C52, "6 Series/C202 Series", read_smb_intel },␊
401 {0x8086, 0x1C54, "6 Series/C204 Series", read_smb_intel },␊
402 {0x8086, 0x1C56, "6 Series/C206 Series", read_smb_intel },␊
403 {0x8086, 0x1C5C, "6 Series", read_smb_intel },␊
404 {0x8086, 0x1D22, "C600/X79 Series", read_smb_intel },␊
405 {0x8086, 0x1D41, "C600/X79 Series", read_smb_intel },␊
406 {0x8086, 0x1D70, "C600/X79 Series", read_smb_intel },␊
407 {0x8086, 0x1D71, "C608/C606/X79 series", read_smb_intel },␊
408 {0x8086, 0x1D72, "C608", read_smb_intel },␊
409 {0x8086, 0x1E22, "7 Series/C210 Series", read_smb_intel },␊
410 {0x8086, 0x1E42, "7 Series", read_smb_intel },␊
411 {0x8086, 0x1E43, "7 Series", read_smb_intel },␊
412 {0x8086, 0x1E44, "7 Series", read_smb_intel },␊
413 {0x8086, 0x1E55, "Mobile 7 Series", read_smb_intel },␊
414 {0x8086, 0x1E56, "7 Series", read_smb_intel },␊
415 {0x8086, 0x1E57, "Mobile 7 Series", read_smb_intel },␊
416 {0x8086, 0x1E58, "Mobile 7 Series", read_smb_intel },␊
417 {0x8086, 0x1E59, "Mobile 7 Series", read_smb_intel },␊
418 {0x8086, 0x1E5D, "Mobile 7 Series", read_smb_intel },␊
419 {0x8086, 0x2330, "DH89xxCC", read_smb_intel },␊
420 {0x8086, 0x2413, "82801AA", read_smb_intel },␊
421 {0x8086, 0x2423, "82801AB", read_smb_intel },␊
422 {0x8086, 0x2443, "82801BA/BAM", read_smb_intel },␊
423 {0x8086, 0x2483, "82801CA/CAM", read_smb_intel },␊
424 {0x8086, 0x24C3, "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)", read_smb_intel },␊
425 {0x8086, 0x24D3, "82801EB/ER (ICH5/ICH5R)", read_smb_intel },␊
426 {0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
427 {0x8086, 0x266A, "82801FB/FBM/FR/FW/FRW (ICH6 Family)", read_smb_intel },␊
428 {0x8086, 0x2670, "631xESB/632xESB/3100", read_smb_intel },␊
429 {0x8086, 0x269B, "631xESB/632xESB/3100", read_smb_intel },␊
430 {0x8086, 0x27B9, "82801GBM (ICH7-M)", read_smb_intel },␊
431 {0x8086, 0x27BD, "82801GHM (ICH7-M DH)", read_smb_intel },␊
432 {0x8086, 0x27DA, "82801GB/GBM/GR/GH/GHM (ICH7 Family)", read_smb_intel },␊
433 {0x8086, 0x2811, "82801HEM (ICH8M-E)", read_smb_intel },␊
434 {0x8086, 0x2815, "82801HM (ICH8M)", read_smb_intel },␊
435 {0x8086, 0x283E, "82801H (ICH8 Family) ", read_smb_intel },␊
436 {0x8086, 0x2916, "82801IR (ICH9R)", read_smb_intel },␊
437 {0x8086, 0x2930, "82801I (ICH9 Family)", read_smb_intel },␊
438 {0x8086, 0x3A18, "82801JIB (ICH10)", read_smb_intel },␊
439 {0x8086, 0x3A30, "82801JI (ICH10 Family)", read_smb_intel },␊
440 {0x8086, 0x3A60, "82801JD/DO (ICH10 Family)", read_smb_intel },␊
441 {0x8086, 0x3B00, "5 Series/3400 Series", read_smb_intel },␊
442 {0x8086, 0x3B01, "Mobile 5 Series", read_smb_intel },␊
443 {0x8086, 0x3B02, "5 Series", read_smb_intel },␊
444 {0x8086, 0x3B09, "Mobile 5 Series", read_smb_intel },␊
445 {0x8086, 0x3B30, "5 Series/3400 Series", read_smb_intel },␊
446 {0x8086, 0x5032, "EP80579", read_smb_intel },␊
447 {0x8086, 0x8119, "6 Series/C200 Series", read_smb_intel },␊
448 {0x8086, 0x8119, "US15W", read_smb_intel },␊
449 {0x8086, 0x8C22, "8 Series/C220 Series", read_smb_intel },␊
450 {0x8086, 0x8C44, "8 Series", read_smb_intel },␊
451 {0x8086, 0x8C4B, "Mobile 8 Series", read_smb_intel },␊
452 {0x8086, 0x8CA2, "9 Series", read_smb_intel },␊
453 {0x8086, 0x8D22, "X99/C610 Series", read_smb_intel },␊
454 {0x8086, 0x9C22, "8 Series", read_smb_intel },␊
455 {0x8086, 0x9C43, "8 Series", read_smb_intel },␊
456 {0x8086, 0x9CC1, "9 Series", read_smb_intel },␊
457 {0x8086, 0x9CC2, "9 Series", read_smb_intel },␊
458 {0x8086, 0x9CC3, "9 Series", read_smb_intel },␊
459 {0x8086, 0x9CC5, "9 Series", read_smb_intel },␊
460 {0x8086, 0x9CC6, "9 Series", read_smb_intel },␊
461 {0x8086, 0x9CC7, "9 Series", read_smb_intel },␊
462 {0x8086, 0x9CC9, "9 Series", read_smb_intel }␊
463};␊
464␊
465// initial call : pci_dt = root_pci_dev;␊
466// find_and_read_smbus_controller(root_pci_dev);␊
467bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
468{␊
469␉pci_dt_t␉*current = pci_dt;␊
470␉int i;␊
471␊
472␉while (current) {␊
473#if 0␊
474␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
475␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
476␉␉current->class_id, current->vendor_id, current->device_id, ␊
477␉␉get_pci_dev_path(current));␊
478#endif␊
479␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ ) {␊
480␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device) {␊
481␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
482␉␉␉␉return true;␊
483␉␉␉}␊
484␉␉}␊
485␉␉find_and_read_smbus_controller(current->children);␊
486␉␉current = current->next;␊
487␉}␊
488␉return false; // not found␊
489}␊
490␊
491void scan_spd(PlatformInfo_t *p)␊
492{␊
493␉find_and_read_smbus_controller(root_pci_dev);␊
494}␊
495␊
496

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