| 1 | /*␊ |
| 2 | * Copyright (c) 2009 Evan Lojewski. All rights reserved.␊ |
| 3 | */␊ |
| 4 | ␊ |
| 5 | /*␊ |
| 6 | * High Precision Event Timer (HPET)␊ |
| 7 | */␊ |
| 8 | ␊ |
| 9 | #include "libsaio.h"␊ |
| 10 | #include "pci.h"␊ |
| 11 | #include "hpet.h"␊ |
| 12 | ␊ |
| 13 | #ifndef DEBUG_HPET␊ |
| 14 | #define DEBUG_HPET 0␊ |
| 15 | #endif␊ |
| 16 | ␊ |
| 17 | #if DEBUG_HPET␊ |
| 18 | #define DBG(x...) printf(x)␊ |
| 19 | #else␊ |
| 20 | #define DBG(x...)␊ |
| 21 | #endif␊ |
| 22 | ␊ |
| 23 | static struct lpc_controller_t lpc_controllers[] = {␊ |
| 24 | ␊ |
| 25 | ␉// Default unknown chipset␊ |
| 26 | ␉{ 0, 0, "" },␊ |
| 27 | ␊ |
| 28 | ␉// Intel␊ |
| 29 | ␉{ 0x8086, 0x24dc, "ICH5" },␊ |
| 30 | ␉{ 0x8086, 0x2640, "ICH6" },␊ |
| 31 | ␉{ 0x8086, 0x2641, "ICH6M" },␊ |
| 32 | ␊ |
| 33 | ␉{ 0x8086, 0x27b0, "ICH7 DH" },␊ |
| 34 | ␉{ 0x8086, 0x27b8, "ICH7" },␊ |
| 35 | ␉{ 0x8086, 0x27b9, "ICH7M" },␊ |
| 36 | ␉{ 0x8086, 0x27bd, "ICH7M DH" },␊ |
| 37 | ␊ |
| 38 | ␉{ 0x8086, 0x2810, "ICH8R" },␊ |
| 39 | ␉{ 0x8086, 0x2811, "ICH8M-E" },␊ |
| 40 | ␉{ 0x8086, 0x2812, "ICH8DH" },␊ |
| 41 | ␉{ 0x8086, 0x2814, "ICH8DO" },␊ |
| 42 | ␉{ 0x8086, 0x2815, "ICH8M" },␊ |
| 43 | ␊ |
| 44 | ␉{ 0x8086, 0x2912, "ICH9DH" },␊ |
| 45 | ␉{ 0x8086, 0x2914, "ICH9DO" },␊ |
| 46 | ␉{ 0x8086, 0x2916, "ICH9R" },␊ |
| 47 | ␉{ 0x8086, 0x2917, "ICH9M-E" },␊ |
| 48 | ␉{ 0x8086, 0x2918, "ICH9" },␊ |
| 49 | ␉{ 0x8086, 0x2919, "ICH9M" },␊ |
| 50 | ␊ |
| 51 | ␉{ 0x8086, 0x3a14, "ICH10DO" },␊ |
| 52 | ␉{ 0x8086, 0x3a16, "ICH10R" },␊ |
| 53 | ␉{ 0x8086, 0x3a18, "ICH10" },␊ |
| 54 | ␉{ 0x8086, 0x3a1a, "ICH10D" },␊ |
| 55 | ␊ |
| 56 | };␊ |
| 57 | ␊ |
| 58 | void force_enable_hpet(pci_dt_t *lpc_dev)␊ |
| 59 | {␊ |
| 60 | ␉int i;␊ |
| 61 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
| 62 | ␉void␉␉*rcba;␊ |
| 63 | ␊ |
| 64 | ␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊ |
| 65 | ␉for(i = 1; i < sizeof(lpc_controllers) / sizeof(lpc_controllers[0]); i++)␊ |
| 66 | ␉␉if ((lpc_controllers[i].vendor == lpc_dev->vendor_id) ␊ |
| 67 | ␉␉␉&& (lpc_controllers[i].device == lpc_dev->device_id))␊ |
| 68 | ␉␉{␊ |
| 69 | ␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊ |
| 70 | ␊ |
| 71 | ␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊ |
| 72 | ␉␉␉␉lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊ |
| 73 | ␊ |
| 74 | ␉␉␉if (rcba == 0)␊ |
| 75 | ␉␉␉{␊ |
| 76 | ␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊ |
| 77 | ␉␉␉}␊ |
| 78 | ␉␉␉else␊ |
| 79 | ␉␉␉{␊ |
| 80 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 81 | ␉␉␉␉if (val & 0x80)␊ |
| 82 | ␉␉␉␉{␊ |
| 83 | ␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊ |
| 84 | ␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊ |
| 85 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 86 | ␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊ |
| 87 | ␉␉␉␉}␊ |
| 88 | ␉␉␉␉else␊ |
| 89 | ␉␉␉␉{␊ |
| 90 | ␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊ |
| 91 | ␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊ |
| 92 | ␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊ |
| 93 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 94 | ␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊ |
| 95 | ␉␉␉␉}␊ |
| 96 | ␊ |
| 97 | ␉␉␉␉// verify if the job is done␊ |
| 98 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 99 | ␉␉␉␉if (!(val & 0x80))␊ |
| 100 | ␉␉␉␉{␊ |
| 101 | ␉␉␉␉␉printf(" Failed to force enable HPET\n");␊ |
| 102 | ␉␉␉␉}␊ |
| 103 | ␉␉␉}␊ |
| 104 | ␉␉␉break;␊ |
| 105 | ␉␉}␊ |
| 106 | ␊ |
| 107 | #if DEBUG_HPET␊ |
| 108 | ␉printf("Press [Enter] to continue...\n");␊ |
| 109 | ␉getchar();␊ |
| 110 | #endif␊ |
| 111 | }␊ |
| 112 | |
