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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * Bronya: 2015 Improve AMD support, cleanup and bugfix␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "bootstruct.h"␊
11#include "boot.h"␊
12␊
13#ifndef DEBUG_CPU␊
14␉#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18␉#define DBG(x...)␉␉printf(x)␊
19#else␊
20␉#define DBG(x...)␊
21#endif␊
22␊
23␊
24#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
25␊
26clock_frequency_info_t gPEClockFrequencyInfo;␊
27␊
28static inline uint32_t __unused clockspeed_rdtsc(void)␊
29{␊
30␉uint32_t out;␊
31␉__asm__ volatile (␊
32 "rdtsc\n"␊
33 "shl $32,%%edx\n"␊
34 "or %%edx,%%eax\n"␊
35 : "=a" (out)␊
36 :␊
37 : "%edx"␊
38 );␊
39␉return out;␊
40}␊
41␊
42/*␊
43 * timeRDTSC()␊
44 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
45 * It pauses until the value is latched in the counter␊
46 * and then reads the time stamp counter to return to the caller.␊
47 */␊
48static uint64_t timeRDTSC(void)␊
49{␊
50␉int␉␉attempts = 0;␊
51␉uint64_t ␉latchTime;␊
52␉uint64_t␉saveTime,intermediate;␊
53␉unsigned int␉timerValue, lastValue;␊
54␉//boolean_t␉int_enabled;␊
55␉/*␊
56␉ * Table of correction factors to account for␊
57␉ *␉ - timer counter quantization errors, and␊
58␉ *␉ - undercounts 0..5␊
59␉ */␊
60#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
61#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
62#define SAMPLE_NSECS␉␉(2000000000LL)␊
63#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
64#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
65␉uint64_t␉scale[6] = {␊
66␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
67␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
68␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
69␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
70␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
71␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
72␉};␊
73␊
74␉//int_enabled = ml_set_interrupts_enabled(false);␊
75␊
76restart:␊
77␉if (attempts >= 3) // increase to up to 9 attempts.␊
78␉{␊
79␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
80␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
81␉}␊
82␉attempts++;␊
83␉enable_PIT2();␉␉// turn on PIT2␊
84␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
85␉latchTime = rdtsc64();␉// get the time stamp to time␊
86␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
87␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
88␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
89␉get_PIT2(&lastValue);␊
90␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
91␉do {␊
92␉␉intermediate = get_PIT2(&timerValue);␊
93␉␉if (timerValue > lastValue)␊
94␉␉{␊
95␉␉␉// Timer wrapped␊
96␉␉␉set_PIT2(0);␊
97␉␉␉disable_PIT2();␊
98␉␉␉goto restart;␊
99␉␉}␊
100␉␉lastValue = timerValue;␊
101␉} while (timerValue > 5);␊
102␉//printf("timerValue␉ %d\n",timerValue);␊
103␉//printf("intermediate 0x%016llX\n",intermediate);␊
104␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
105 ␊
106␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
107␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
108␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
109␉intermediate += latchTime;␉␉// add on our save fudge␊
110␊
111␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
112␉disable_PIT2();␉␉␉// turn off PIT 2␊
113␊
114␉//ml_set_interrupts_enabled(int_enabled);␊
115␉return intermediate;␊
116}␊
117␊
118/*␊
119 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
120 */␊
121static uint64_t __unused measure_tsc_frequency(void)␊
122{␊
123␉uint64_t tscStart;␊
124␉uint64_t tscEnd;␊
125␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
126␉unsigned long pollCount;␊
127␉uint64_t retval = 0;␊
128␉int i;␊
129␊
130␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
131␉ * counter 2. We run this loop 3 times to make sure the cache␊
132␉ * is hot and we take the minimum delta from all of the runs.␊
133␉ * That is to say that we're biased towards measuring the minimum␊
134␉ * number of TSC ticks that occur while waiting for the timer to␊
135␉ * expire. That theoretically helps avoid inconsistencies when␊
136␉ * running under a VM if the TSC is not virtualized and the host␊
137␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
138␉ */␊
139␉for(i = 0; i < 10; ++i)␊
140␉{␊
141␉␉enable_PIT2();␊
142␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
143␉␉tscStart = rdtsc64();␊
144␉␉pollCount = poll_PIT2_gate();␊
145␉␉tscEnd = rdtsc64();␊
146␉␉/* The poll loop must have run at least a few times for accuracy */␊
147␉␉if (pollCount <= 1)␊
148␉␉{␊
149␉␉␉continue;␊
150␉␉}␊
151␉␉/* The TSC must increment at LEAST once every millisecond.␊
152␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
153␉␉ * be >= 30. Anything less and the processor is way too slow.␊
154␉␉ */␊
155␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
156␉␉{␊
157␉␉␉continue;␊
158␉␉}␊
159␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
160␉␉if ( (tscEnd - tscStart) < tscDelta )␊
161␉␉{␊
162␉␉␉tscDelta = tscEnd - tscStart;␊
163␉␉}␊
164␉}␊
165␉/* tscDelta is now the least number of TSC ticks the processor made in␊
166␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
167␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
168␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
169␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
170␉ * dividing by the milliseconds, we simply multiply by 1000.␊
171␉ */␊
172␊
173␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
174␉ * that we're going to multiply by 1000 first so we do need at least some␊
175␉ * arithmetic headroom. For now, 32-bit should be enough.␊
176␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
177␉ */␊
178␉if (tscDelta > (1ULL<<32))␊
179␉{␊
180␉␉retval = 0;␊
181␉}␊
182␉else␊
183␉{␊
184␉␉retval = tscDelta * 1000 / 30;␊
185␉}␊
186␉disable_PIT2();␊
187␉return retval;␊
188}␊
189␊
190static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
191#define RTC_FAST_DENOM␉0xFFFFFFFF␊
192␊
193inline static uint32_t␊
194create_mul_quant_GHZ(int shift, uint32_t quant)␊
195{␊
196␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
197}␊
198␊
199struct␉{␊
200␉mach_timespec_t␉␉␉calend_offset;␊
201␉boolean_t␉␉␉calend_is_set;␊
202␊
203␉int64_t␉␉␉␉calend_adjtotal;␊
204␉int32_t␉␉␉␉calend_adjdelta;␊
205␊
206␉uint32_t␉␉␉boottime;␊
207␊
208␉mach_timebase_info_data_t␉timebase_const;␊
209␊
210␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
211} rtclock;␊
212␊
213uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
214uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
215uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
216uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
217//uint64_t cpuFreq;␊
218␊
219static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
220{␊
221␊
222␉if (cycles > (NSEC_PER_SEC/20))␊
223␉{␊
224␉␉// we can use just a "fast" multiply to get nanos␊
225␉␉rtc_quant_shift = 32;␊
226␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
227␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
228␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
229␉}␊
230␉else␊
231␉{␊
232␉␉rtc_quant_shift = 26;␊
233␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
234␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
235␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
236␉}␊
237␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
238␉// BUT we also want to calculate...␊
239␊
240␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
241 / UI_CPUFREQ_ROUNDING_FACTOR)␊
242␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
243␊
244␉/*␊
245␉ * Set current measured speed.␊
246␉ */␊
247␉if (cycles >= 0x100000000ULL)␊
248␉{␊
249␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
250␉}␊
251␉else␊
252␉{␊
253␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
254␉}␊
255␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
256␊
257␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
258␉return(rtc_cyc_per_sec);␊
259}␊
260␊
261/*␊
262 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
263 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
264 *␉ a max multi. (used to calculate the FSB freq.),␊
265 *␉ and a current multi. (used to calculate the CPU freq.)␊
266 * - busFrequency = tscFrequency / multi␊
267 * - cpuFrequency = busFrequency * multi␊
268 */␊
269␊
270/* Decimal powers: */␊
271#define kilo (1000ULL)␊
272#define Mega (kilo * kilo)␊
273#define Giga (kilo * Mega)␊
274#define Tera (kilo * Giga)␊
275#define Peta (kilo * Tera)␊
276␊
277#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
278␊
279void scan_cpu(PlatformInfo_t *p)␊
280{␊
281//␉scan();␊
282␉uint64_t␉busFCvtt2n;␊
283␉uint64_t␉tscFCvtt2n;␊
284␉uint64_t␉tscFreq␉␉␉= 0;␊
285␉uint64_t␉busFrequency␉␉= 0;␊
286␉uint64_t␉cpuFrequency␉␉= 0;␊
287␉uint64_t␉msr␉␉␉= 0;␊
288␉uint64_t␉flex_ratio␉␉= 0;␊
289␉uint64_t␉cpuid_features;␊
290␊
291␉uint32_t␉max_ratio␉␉= 0;␊
292␉uint32_t␉min_ratio␉␉= 0;␊
293␉uint32_t␉reg[4];␊
294␉uint32_t␉cores_per_package␉= 0;␊
295␉uint32_t␉logical_per_package␉= 1;␊
296␉uint32_t␉threads_per_core␉= 1;␊
297␊
298␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
299␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
300␉uint8_t␉␉currdiv␉␉␉= 0;␊
301␉uint8_t␉␉currcoef␉␉= 0;␊
302␉uint8_t␉␉maxdiv␉␉␉= 0;␊
303␉uint8_t␉␉maxcoef␉␉␉= 0;␊
304␉uint8_t␉␉pic0_mask;␊
305␉uint8_t␉␉cpuMultN2␉␉= 0;␊
306␊
307␉const char␉*newratio;␊
308␉char␉␉str[128];␊
309␉char␉␉*s␉␉␉= 0;␊
310␊
311␉int␉␉len␉␉␉= 0;␊
312␉int␉␉myfsb␉␉␉= 0;␊
313␉int␉␉i␉␉␉= 0;␊
314␊
315␊
316/* http://www.flounder.com/cpuid_explorer2.htm␊
317 EAX (Intel):␊
318 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
319 +--------+----------------+--------+----+----+--------+--------+--------+␊
320 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
321 +--------+----------------+--------+----+----+--------+--------+--------+␊
322␊
323 EAX (AMD):␊
324 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
325 +--------+----------------+--------+----+----+--------+--------+--------+␊
326 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
327 +--------+----------------+--------+----+----+--------+--------+--------+␊
328*/␊
329␉///////////////////-- MaxFn,Vendor --////////////////////////␊
330␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
331␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
332␉/////////////////////////////////////////////////////////////␊
333␊
334␉///////////////////-- Signature, stepping, features -- //////␊
335␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
336␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊
337␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
338␉{␊
339␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
340␉}␊
341␉else␊
342␉{␊
343␉␉logical_per_package = 1;␊
344␉}␊
345//␉printf("logical %d\n",logical_per_package);␊
346␊
347␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
348␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
349␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
350␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
351␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
352␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
353␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
354␊
355␉if (p->CPU.Family == 0x0f)␊
356␉{␊
357␉␉p->CPU.Family += p->CPU.ExtFamily;␊
358␉}␊
359␊
360␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
361␉{␊
362␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
363␉}␊
364␊
365␉switch (p->CPU.Vendor)␊
366␉{␊
367␉␉case CPUID_VENDOR_INTEL:␊
368␉␉{␊
369␊
370␉␉␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
371␊
372␉␉␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
373␊
374␉␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
375␉␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
376␉␉␉{␊
377␉␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
378␉␉␉␉{␊
379␉␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
380␉␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
381␉␉␉␉␉{␊
382␉␉␉␉␉␉break;␊
383␉␉␉␉␉}␊
384␉␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
385␉␉␉␉}␊
386␉␉␉}␊
387␊
388␉␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
389␊
390␉␉␉if (i > 0)␊
391␉␉␉{␊
392␉␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
393␉␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
394␉␉␉}␊
395␊
396␉␉␉if (cores_per_package == 0)␊
397␉␉␉{␊
398␉␉␉␉cores_per_package = 1;␊
399␉␉␉}␊
400␊
401␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
402␉␉␉{␊
403␉␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
404␉␉␉}␊
405␊
406␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
407␉␉␉{␊
408␉␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
409␉␉␉}␊
410␊
411␉␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
412␊
413␉␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
414␉␉␉{␊
415␉␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
416␉␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
417␉␉␉}␊
418␉␉␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
419␉␉␉{␊
420␉␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
421␉␉␉}␊
422␊
423␉␉␉switch (p->CPU.Model)␊
424␉␉␉{␊
425␉␉␉␉case CPUID_MODEL_NEHALEM:␊
426␉␉␉␉case CPUID_MODEL_FIELDS:␊
427␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
428␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
429␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
430␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
431␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
432␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
433␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
434␉␉␉␉case CPUID_MODEL_HASWELL:␊
435␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
436␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊
437␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
438␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
439␉␉␉␉//case CPUID_MODEL_:␊
440␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊
441␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
442␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
443␉␉␉␉␉break;␊
444␊
445␉␉␉␉case CPUID_MODEL_DALES:␊
446␉␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊
447␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
448␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
449␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
450␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
451␉␉␉␉␉break;␊
452␉␉␉}␊
453␊
454␉␉␉if (p->CPU.NoCores == 0)␊
455␉␉␉{␊
456␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
457␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
458␉␉␉}␊
459␊
460␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊
461␉␉␉//workaround for N270. I don't know why it detected wrong␊
462␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
463␉␉␉{␊
464␉␉␉␉p->CPU.NoCores␉␉= 1;␊
465␉␉␉␉p->CPU.NoThreads␉= 2;␊
466␉␉␉}␊
467␊
468␉␉␉//workaround for Quad␊
469␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
470␉␉␉{␊
471␉␉␉␉p->CPU.NoCores␉␉= 4;␊
472␉␉␉␉p->CPU.NoThreads␉= 4;␊
473␉␉␉}␊
474␉␉}␊
475␊
476␉␉break;␊
477␊
478␉␉case CPUID_VENDOR_AMD:␊
479␉␉{␊
480␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
481␊
482␉␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
483␉␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
484␉␉␉{␊
485␉␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
486␉␉␉}␊
487␊
488␉␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
489␉␉␉{␊
490␉␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
491␉␉␉}␊
492␊
493␉␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
494␉␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
495␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
496␊
497␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
498␉␉␉threads_per_core = cores_per_package;␊
499␊
500␉␉␉if (cores_per_package == 0)␊
501␉␉␉{␊
502␉␉␉␉cores_per_package = 1;␊
503␉␉␉}␊
504␊
505␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
506␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
507␊
508␉␉␉if (p->CPU.NoCores == 0)␊
509␉␉␉{␊
510␉␉␉␉p->CPU.NoCores = 1;␊
511␉␉␉␉p->CPU.NoThreads␉= 1;␊
512␉␉␉}␊
513␉␉}␊
514␉␉break;␊
515␊
516␉␉default :␊
517␉␉␉stop("Unsupported CPU detected! System halted.");␊
518␉}␊
519␊
520␉/* get BrandString (if supported) */␊
521␉/* Copyright: from Apple's XNU cpuid.c */␊
522␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
523␉{␊
524␉␉bzero(str, 128);␊
525␉␉/*␊
526␉␉ * The BrandString 48 bytes (max), guaranteed to␊
527␉␉ * be NULL terminated.␊
528␉␉ */␊
529␉␉do_cpuid(0x80000002, reg);␊
530␉␉memcpy(&str[0], (char *)reg, 16);␊
531␉␉do_cpuid(0x80000003, reg);␊
532␉␉memcpy(&str[16], (char *)reg, 16);␊
533␉␉do_cpuid(0x80000004, reg);␊
534␉␉memcpy(&str[32], (char *)reg, 16);␊
535␉␉for (s = str; *s != '\0'; s++)␊
536␉␉{␊
537␉␉␉if (*s != ' ')␊
538␉␉␉{␊
539␉␉␉␉break;␊
540␉␉␉}␊
541␉␉}␊
542␉␉strlcpy(p->CPU.BrandString, s, 48);␊
543␊
544␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
545␉␉{␊
546␉␉␉/*␊
547␉␉␉ * This string means we have a firmware-programmable brand string,␊
548␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
549␉␉␉ */␊
550␉␉␉p->CPU.BrandString[0] = '\0';␊
551␉␉}␊
552␉␉p->CPU.BrandString[47] = '\0';␊
553//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
554␉}␊
555␊
556␉/* setup features */␊
557␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
558␉{␊
559␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
560␉}␊
561␊
562␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
563␉{␊
564␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
565␉}␊
566␊
567␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
568␉{␊
569␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
570␉}␊
571␊
572␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
573␉{␊
574␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
575␉}␊
576␊
577␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
578␉{␊
579␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
580␉}␊
581␊
582␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
583␉{␊
584␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
585␉}␊
586␊
587␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
588␉{␊
589␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
590␉}␊
591␊
592␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
593␉{␊
594␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
595␉}␊
596␊
597␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
598␉{␊
599␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
600␉}␊
601␊
602␉pic0_mask = inb(0x21U);␊
603␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
604␊
605␉uint64_t cycles;␊
606␉cycles = timeRDTSC();␊
607␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
608␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
609␉// if usual method failed␊
610␉if ( tscFreq < 1000 )␉//TEST␊
611␉{␊
612␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
613␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
614␉}␊
615␊
616␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
617␉{␊
618␉␉int intelCPU = p->CPU.Model;␊
619␉␉if (p->CPU.Family == 0x06)␊
620␉␉{␊
621␉␉␉/* Nehalem CPU model */␊
622␉␉␉switch (p->CPU.Model)␊
623␉␉␉{␊
624␉␉␉␉case CPUID_MODEL_NEHALEM:␊
625␉␉␉␉case CPUID_MODEL_FIELDS:␊
626␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
627␉␉␉␉case CPUID_MODEL_DALES:␊
628␉␉␉␉case CPUID_MODEL_WESTMERE:␊
629␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
630␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
631/* --------------------------------------------------------- */␊
632␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
633␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
634␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
635␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
636␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
637␉␉␉␉case CPUID_MODEL_HASWELL:␊
638␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
639␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
640␊
641␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
642␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
643/* --------------------------------------------------------- */␊
644␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
645␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
646␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
647␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
648␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
649␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
650␉␉␉␉␉if (bitfield(msr, 16, 16))␊
651␉␉␉␉␉{␊
652␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
653␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
654␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
655␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
656␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
657␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
658␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
659␉␉␉␉␉␉// is inadvertently set to 0.␊
660␊
661␉␉␉␉␉␉if (flex_ratio == 0)␊
662␉␉␉␉␉␉{␊
663␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
664␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
665␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
666␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
667␉␉␉␉␉␉}␊
668␉␉␉␉␉␉else␊
669␉␉␉␉␉␉{␊
670␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
671␉␉␉␉␉␉␉{␊
672␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
673␉␉␉␉␉␉␉}␊
674␉␉␉␉␉␉}␊
675␉␉␉␉␉}␊
676␊
677␉␉␉␉␉if (bus_ratio_max)␊
678␉␉␉␉␉{␊
679␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
680␉␉␉␉␉}␊
681␊
682␉␉␉␉␉//valv: Turbo Ratio Limit␊
683␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
684␉␉␉␉␉{␊
685␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
686␊
687␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
688␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
689␉␉␉␉␉}␊
690␉␉␉␉␉else␊
691␉␉␉␉␉{␊
692␉␉␉␉␉␉cpuFrequency = tscFreq;␊
693␉␉␉␉␉}␊
694␊
695␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
696␉␉␉␉␉{␊
697␉␉␉␉␉␉max_ratio = atoi(newratio);␊
698␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
699␉␉␉␉␉␉if (len >= 3)␊
700␉␉␉␉␉␉{␊
701␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
702␉␉␉␉␉␉}␊
703␊
704␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
705␊
706␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
707␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
708␉␉␉␉␉␉{␊
709␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
710␉␉␉␉␉␉␉if (len >= 3)␊
711␉␉␉␉␉␉␉{␊
712␉␉␉␉␉␉␉␉maxdiv = 1;␊
713␉␉␉␉␉␉␉}␊
714␉␉␉␉␉␉␉else␊
715␉␉␉␉␉␉␉{␊
716␉␉␉␉␉␉␉␉maxdiv = 0;␊
717␉␉␉␉␉␉␉}␊
718␉␉␉␉␉␉}␊
719␉␉␉␉␉␉else␊
720␉␉␉␉␉␉{␊
721␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
722␉␉␉␉␉␉}␊
723␉␉␉␉␉}␊
724␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
725␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
726␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
727␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
728␊
729␉␉␉␉myfsb = busFrequency / 1000000;␊
730␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
731␉␉␉␉currcoef = bus_ratio_max;␊
732␊
733␉␉␉␉break;␊
734␊
735␉␉␉default:␊
736␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
737␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
738␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
739␉␉␉␉// Non-integer bus ratio for the max-multi␊
740␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
741␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
742␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
743␊
744␉␉␉␉// This will always be model >= 3␊
745␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
746␉␉␉␉{␊
747␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
748␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
749␉␉␉␉}␊
750␉␉␉␉else␊
751␉␉␉␉{␊
752␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
753␉␉␉␉␉// XXX␊
754␉␉␉␉␉maxcoef = currcoef;␊
755␉␉␉␉}␊
756␊
757␉␉␉␉if (!currcoef)␊
758␉␉␉␉{␊
759␉␉␉␉␉currcoef = maxcoef;␊
760␉␉␉␉}␊
761␊
762␉␉␉␉if (maxcoef)␊
763␉␉␉␉{␊
764␉␉␉␉␉if (maxdiv)␊
765␉␉␉␉␉{␊
766␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
767␉␉␉␉␉}␊
768␉␉␉␉␉else␊
769␉␉␉␉␉{␊
770␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
771␉␉␉␉␉}␊
772␊
773␉␉␉␉␉if (currdiv)␊
774␉␉␉␉␉{␊
775␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
776␉␉␉␉␉}␊
777␉␉␉␉␉else␊
778␉␉␉␉␉{␊
779␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
780␉␉␉␉␉}␊
781␊
782␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
783␉␉␉␉}␊
784␉␉␉␉break;␊
785␉␉␉}␊
786␉␉}␊
787␉␉// Mobile CPU␊
788␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
789␉␉{␊
790␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
791␉␉}␊
792␉}␊
793␊
794␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
795␉{␊
796␉␉switch(p->CPU.Family)␊
797␉␉{␊
798␉␉␉case 0xF: /* K8 */␊
799␉␉␉{␊
800␉␉␉␉uint64_t fidvid = 0;␊
801␉␉␉␉uint64_t cpuMult;␊
802␉␉␉␉uint64_t fid;␊
803␊
804␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
805␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
806␊
807␉␉␉␉cpuMult = (fid + 8) / 2;␊
808␉␉␉␉currcoef = cpuMult;␊
809␊
810␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
811␉␉␉␉currdiv = cpuMultN2;␊
812␉␉␉␉/****** Addon END ******/␊
813␉␉␉}␊
814␉␉␉␉break;␊
815␊
816␉␉␉case 0x10: /*** AMD Family 10h ***/␊
817␉␉␉{␊
818␉␉␉␉uint64_t cofvid = 0;␊
819␉␉␉␉uint64_t cpuMult;␊
820␉␉␉␉uint64_t divisor = 0;␊
821␉␉␉␉uint64_t did;␊
822␉␉␉␉uint64_t fid;␊
823␊
824␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
825␉␉␉␉did = bitfield(cofvid, 8, 6);␊
826␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
827␉␉␉␉if (did == 0) divisor = 2;␊
828␉␉␉␉else if (did == 1) divisor = 4;␊
829␉␉␉␉else if (did == 2) divisor = 8;␊
830␉␉␉␉else if (did == 3) divisor = 16;␊
831␉␉␉␉else if (did == 4) divisor = 32;␊
832␊
833␉␉␉␉cpuMult = (fid + 16) / divisor;␊
834␉␉␉␉currcoef = cpuMult;␊
835␊
836␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
837␉␉␉␉currdiv = cpuMultN2;␊
838␊
839␉␉␉␉/****** Addon END ******/␊
840␉␉␉}␊
841␉␉␉break;␊
842␊
843␉␉␉case 0x11: /*** AMD Family 11h ***/␊
844␉␉␉{␊
845␉␉␉␉uint64_t cofvid = 0;␊
846␉␉␉␉uint64_t cpuMult;␊
847␉␉␉␉uint64_t divisor = 0;␊
848␉␉␉␉uint64_t did;␊
849␉␉␉␉uint64_t fid;␊
850␊
851␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
852␉␉␉␉did = bitfield(cofvid, 8, 6);␊
853␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
854␉␉␉␉if (did == 0) divisor = 2;␊
855␉␉␉␉else if (did == 1) divisor = 4;␊
856␉␉␉␉else if (did == 2) divisor = 8;␊
857␉␉␉␉else if (did == 3) divisor = 16;␊
858␉␉␉␉else if (did == 4) divisor = 32;␊
859␊
860␉␉␉␉cpuMult = (fid + 8) / divisor;␊
861␉␉␉␉currcoef = cpuMult;␊
862␊
863␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
864␉␉␉␉currdiv = cpuMultN2;␊
865␊
866␉␉␉␉/****** Addon END ******/␊
867␉␉␉}␊
868 break;␊
869␊
870␉␉␉case 0x12: /*** AMD Family 12h ***/␊
871␉␉␉{␊
872␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
873␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
874␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
875␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
876␊
877␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
878␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
879␉␉␉␉uint64_t divisor;␊
880␉␉␉␉switch (CpuDid)␊
881␉␉␉␉{␊
882␉␉␉␉␉case 0: divisor = 1; break;␊
883␉␉␉␉␉case 1: divisor = (3/2); break;␊
884␉␉␉␉␉case 2: divisor = 2; break;␊
885␉␉␉␉␉case 3: divisor = 3; break;␊
886␉␉␉␉␉case 4: divisor = 4; break;␊
887␉␉␉␉␉case 5: divisor = 6; break;␊
888␉␉␉␉␉case 6: divisor = 8; break;␊
889␉␉␉␉␉case 7: divisor = 12; break;␊
890␉␉␉␉␉case 8: divisor = 16; break;␊
891␉␉␉␉␉default: divisor = 1; break;␊
892␉␉␉␉}␊
893␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
894␊
895␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
896␉␉␉␉currdiv = cpuMultN2;␊
897␊
898␉␉␉}␊
899␉␉␉␉break;␊
900␊
901␉␉␉case 0x14: /* K14 */␊
902␊
903␉␉␉{␊
904␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
905␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
906␉␉␉␉uint64_t prfsts;␊
907␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
908␊
909␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
910␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
911␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
912␊
913␉␉␉␉uint64_t frequencyId = 0x10;␊
914␉␉␉␉currcoef = (frequencyId + 0x10) /␊
915␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
916␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
917␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
918␊
919␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
920␉␉␉␉currdiv = cpuMultN2;␊
921␉␉␉}␊
922␊
923␉␉␉␉break;␊
924␊
925␉␉␉case 0x15: /*** AMD Family 15h ***/␊
926␉␉␉case 0x06: /*** AMD Family 06h ***/␊
927␉␉␉{␊
928␊
929␉␉␉␉uint64_t cofvid = 0;␊
930␉␉␉␉uint64_t cpuMult;␊
931␉␉␉␉uint64_t divisor = 0;␊
932␉␉␉␉uint64_t did;␊
933␉␉␉␉uint64_t fid;␊
934␊
935␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
936␉␉␉␉did = bitfield(cofvid, 8, 6);␊
937␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
938␉␉␉␉if (did == 0) divisor = 2;␊
939␉␉␉␉else if (did == 1) divisor = 4;␊
940␉␉␉␉else if (did == 2) divisor = 8;␊
941␉␉␉␉else if (did == 3) divisor = 16;␊
942␉␉␉␉else if (did == 4) divisor = 32;␊
943␊
944␉␉␉␉cpuMult = (fid + 16) / divisor;␊
945␉␉␉␉currcoef = cpuMult;␊
946␊
947␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
948␉␉␉␉currdiv = cpuMultN2;␊
949␉␉␉}␊
950␉␉␉␉break;␊
951␊
952␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
953␉␉␉{␊
954␉␉␉␉uint64_t cofvid = 0;␊
955␉␉␉␉uint64_t cpuMult;␊
956␉␉␉␉uint64_t divisor = 0;␊
957␉␉␉␉uint64_t did;␊
958␉␉␉␉uint64_t fid;␊
959␊
960␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
961␉␉␉␉did = bitfield(cofvid, 8, 6);␊
962␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
963␉␉␉␉if (did == 0) divisor = 1;␊
964␉␉␉␉else if (did == 1) divisor = 2;␊
965␉␉␉␉else if (did == 2) divisor = 4;␊
966␉␉␉␉else if (did == 3) divisor = 8;␊
967␉␉␉␉else if (did == 4) divisor = 16;␊
968␊
969␉␉␉␉cpuMult = (fid + 16) / divisor;␊
970␉␉␉␉currcoef = cpuMult;␊
971␊
972␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
973␉␉␉␉currdiv = cpuMultN2;␊
974␉␉␉␉/****** Addon END ******/␊
975␉␉␉}␊
976␉␉␉␉break;␊
977␊
978␉␉␉default:␊
979␉␉␉{␊
980␉␉␉␉typedef unsigned long long vlong;␊
981␉␉␉␉uint64_t prfsts;␊
982␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
983␉␉␉␉uint64_t r;␊
984␉␉␉␉vlong hz;␊
985␉␉␉␉r = (prfsts>>6) & 0x07;␊
986␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
987␊
988␉␉␉␉currcoef = hz / (200 * Mega);␊
989␉␉␉}␊
990␉␉}␊
991␊
992␉␉if (currcoef)␊
993␉␉{␊
994␉␉␉if (currdiv)␊
995␉␉␉{␊
996␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
997␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
998␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
999␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1000␊
1001␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
1002␉␉␉}␊
1003␉␉␉else␊
1004␉␉␉{␊
1005␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1006␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1007␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1008␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1009␉␉␉␉DBG("%d\n", currcoef);␊
1010␉␉␉}␊
1011␉␉}␊
1012␉␉else if (!cpuFrequency)␊
1013␉␉{␊
1014␉␉␉cpuFrequency = tscFreq;␊
1015␉␉}␊
1016␉}␊
1017␊
1018#if 0␊
1019␉if (!busFrequency)␊
1020␉{␊
1021␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1022␉␉DBG("CPU: busFrequency = 0! using the default value for FSB!\n");␊
1023␉␉cpuFrequency = tscFreq;␊
1024␉}␊
1025␊
1026␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1027␊
1028#endif␊
1029␊
1030␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
1031␊
1032␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1033␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1034␉p->CPU.CurrCoef = currcoef;␊
1035␉p->CPU.CurrDiv = currdiv;␊
1036␉p->CPU.TSCFrequency = tscFreq;␊
1037␉p->CPU.FSBFrequency = busFrequency;␊
1038␉p->CPU.CPUFrequency = cpuFrequency;␊
1039␊
1040␉// keep formatted with spaces instead of tabs␊
1041␉DBG("\n------------------------------\n");␊
1042 ␉DBG("\tCPU INFO\n");␊
1043␉DBG("------------------------------\n");␊
1044␊
1045␉DBG("CPUID Raw Values:\n");␊
1046␉for (i = 0; i < CPUID_MAX; i++)␊
1047␉{␊
1048␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1049␉}␊
1050␉DBG("\n");␊
1051␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1052␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1053␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1054␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊
1055␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1056␉/*switch (p->CPU.Type) {␊
1057␉␉case PT_OEM:␊
1058␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊
1059␉␉␉break;␊
1060␉␉case PT_OD:␊
1061␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊
1062␉␉␉break;␊
1063␉␉case PT_DUAL:␊
1064␉␉␉DBG("Processor type: Intel Dual Processor\n");␊
1065␉␉␉break;␊
1066␉␉case PT_RES:␊
1067␉␉␉DBG("Processor type: Intel Reserved\n");␊
1068␉␉␉break;␊
1069␉␉default:␊
1070␉␉␉break;␊
1071␉}*/␊
1072␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1073␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊
1074␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1075␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1076␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1077␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1078␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1079␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
1080␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
1081␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
1082␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1083␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1084␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
1085␊
1086␉DBG("\n---------------------------------------------\n");␊
1087#if DEBUG_CPU␊
1088␉pause();␊
1089#endif␊
1090}␊
1091

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