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Root/trunk/i386/libsaio/platform.h

1/*
2 * platform.h
3 * AsereBLN: reworked and extended
4 *
5 */
6
7#ifndef __LIBSAIO_PLATFORM_H
8#define __LIBSAIO_PLATFORM_H
9
10//#include "libsaio.h"
11
12extern bool platformCPUFeature(uint32_t);
13extern void scan_platform(void);
14extern void dumpPhysAddr(const char * title, void * a, int len);
15
16/* CPUID index into cpuid_raw */
17#define CPUID_00
18#define CPUID_11
19#define CPUID_22
20#define CPUID_33
21#define CPUID_44
22#define CPUID_55
23#define CPUID_66
24#define CPUID_807
25#define CPUID_818
26#define CPUID_859
27#define CPUID_8610
28#define CPUID_8711
29#define CPUID_8812
30#define CPUID_MAX13
31
32#define CPUID_MODEL_ANY0x00
33#define CPUID_MODEL_UNKNOWN0x01
34#define CPUID_MODEL_PRESCOTT0x03// Celeron D, Pentium 4 (90nm)
35#define CPUID_MODEL_NOCONA0x04// Xeon Nocona/Paxville, Irwindale (90nm)
36#define CPUID_MODEL_PRESLER0x06// Pentium 4, Pentium D (65nm)
37#define CPUID_MODEL_PENTIUM_M0x09// Banias Pentium M (130nm)
38#define CPUID_MODEL_DOTHAN0x0D// Dothan Pentium M, Celeron M (90nm)
39#define CPUID_MODEL_YONAH0x0E// Sossaman, Yonah
40#define CPUID_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
41#define CPUID_MODEL_CONROE0x0F//
42#define CPUID_MODEL_CELERON0x16// Merom, Conroe (65nm), Celeron (45nm)
43#define CPUID_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
44#define CPUID_MODEL_WOLFDALE0x17// Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx
45#define CPUID_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
46#define CPUID_MODEL_ATOM0x1C// Pineview, Bonnell
47#define CPUID_MODEL_XEON_MP0x1D// MP 7400
48#define CPUID_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
49#define CPUID_MODEL_CLARKDALE0x1F// Havendale, Auburndale
50#define CPUID_MODEL_DALES0x25// Clarkdale, Arrandale
51#define CPUID_MODEL_ATOM_SAN0x26// Lincroft
52#define CPUID_MODEL_LINCROFT0x27// Bonnell
53#define CPUID_MODEL_SANDYBRIDGE0x2A// Sandy Bridge
54#define CPUID_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
55#define CPUID_MODEL_JAKETOWN0x2D// Sandy Bridge-E, Sandy Bridge-EP
56#define CPUID_MODEL_NEHALEM_EX0x2E// Beckton
57#define CPUID_MODEL_WESTMERE_EX0x2F// Westmere-EX
58//#define CPUID_MODEL_BONNELL_ATOM0x35// Atom Family Bonnell
59#define CPUID_MODEL_ATOM_20000x36// Cedarview / Saltwell
60#define CPUID_MODEL_ATOM_37000x37// Atom E3000, Z3000 Atom Silvermont
61#define CPUID_MODEL_IVYBRIDGE0x3A// Ivy Bridge
62#define CPUID_MODEL_HASWELL0x3C// Haswell DT
63#define CPUID_MODEL_HASWELL_U50x3D// Haswell U5 5th generation Broadwell, Core M / Core-AVX2
64#define CPUID_MODEL_IVYBRIDGE_XEON0x3E// Ivy Bridge Xeon
65#define CPUID_MODEL_HASWELL_SVR0x3F// Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E)
66//#define CPUID_MODEL_HASWELL_H0x??// Haswell H
67#define CPUID_MODEL_HASWELL_ULT0x45// Haswell ULT, 4th gen Core, Xeon E3-12xx v3
68#define CPUID_MODEL_HASWELL_ULX0x46// Crystal Well, 4th gen Core, Xeon E3-12xx v3
69//#define CPUID_MODEL_0x4A// Future Atom E3000, Z3000 silvermont / atom
70#define CPUID_MODEL_AVOTON0x4D// Silvermont/Avoton Atom C2000
71//#define CPUID_MODEL_0x4E// Future Core
72#define CPUID_MODEL_BRODWELL_SVR0x4F// Broadwell Server
73#define CPUID_MODEL_BRODWELL_MSVR0x56// Broadwell Micro Server, Future Xeon
74//#define CPUID_MODEL_0x5A// Silvermont, Future Atom E3000, Z3000
75//#define CPUID_MODEL_0x5D// Silvermont, Future Atom E3000, Z3000
76
77/* CPUID Vendor */
78#defineCPUID_VID_INTEL"GenuineIntel"
79#defineCPUID_VID_AMD"AuthenticAMD"
80
81#define CPUID_VENDOR_INTEL0x756E6547
82#define CPUID_VENDOR_AMD0x68747541
83
84/* This spells out "GenuineIntel". */
85//#define is_intel \
86// ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69
87
88/* This spells out "AuthenticAMD". */
89//#define is_amd \
90// ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65
91
92/* Unknown CPU */
93#define CPU_STRING_UNKNOWN"Unknown CPU Typ"
94
95//definitions from Apple XNU
96
97/* CPU defines */
98#define bit(n)(1ULL << (n))
99#define bitmask(h,l)((bit(h) | (bit(h)-1)) & ~(bit(l)-1))
100#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
101#define hbit(n)(1ULL << ((n)+32))
102#define min(a,b)((a) < (b) ? (a) : (b))
103#define quad32(hi,lo)((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))
104#define quad64(hi,lo)((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))
105
106/*
107 * The CPUID_FEATURE_XXX values define 64-bit values
108 * returned in %ecx:%edx to a CPUID request with %eax of 1:
109 */
110#define CPUID_FEATURE_FPUbit(0) /* Floating point unit on-chip */
111#define CPUID_FEATURE_VMEbit(1) /* Virtual Mode Extension */
112#define CPUID_FEATURE_DEbit(2) /* Debugging Extension */
113#define CPUID_FEATURE_PSEbit(3) /* Page Size Extension */
114#define CPUID_FEATURE_TSCbit(4) /* Time Stamp Counter */
115#define CPUID_FEATURE_MSRbit(5) /* Model Specific Registers */
116#define CPUID_FEATURE_PAEbit(6) /* Physical Address Extension */
117#define CPUID_FEATURE_MCEbit(7) /* Machine Check Exception */
118#define CPUID_FEATURE_CX8bit(8) /* CMPXCHG8B */
119#define CPUID_FEATURE_APICbit(9) /* On-chip APIC */
120#define CPUID_FEATURE_SEPbit(11) /* Fast System Call */
121#define CPUID_FEATURE_MTRRbit(12) /* Memory Type Range Register */
122#define CPUID_FEATURE_PGEbit(13) /* Page Global Enable */
123#define CPUID_FEATURE_MCAbit(14) /* Machine Check Architecture */
124#define CPUID_FEATURE_CMOVbit(15) /* Conditional Move Instruction */
125#define CPUID_FEATURE_PATbit(16) /* Page Attribute Table */
126#define CPUID_FEATURE_PSE36bit(17) /* 36-bit Page Size Extension */
127#define CPUID_FEATURE_PSNbit(18) /* Processor Serial Number */
128#define CPUID_FEATURE_CLFSHbit(19) /* CLFLUSH Instruction supported */
129#define CPUID_FEATURE_DSbit(21) /* Debug Store */
130#define CPUID_FEATURE_ACPIbit(22) /* Thermal monitor and Clock Ctrl */
131#define CPUID_FEATURE_MMXbit(23) /* MMX supported */
132#define CPUID_FEATURE_FXSRbit(24) /* Fast floating pt save/restore */
133#define CPUID_FEATURE_SSEbit(25) /* Streaming SIMD extensions */
134#define CPUID_FEATURE_SSE2bit(26) /* Streaming SIMD extensions 2 */
135#define CPUID_FEATURE_SSbit(27) /* Self-Snoop */
136#define CPUID_FEATURE_HTTbit(28) /* Hyper-Threading Technology */
137#define CPUID_FEATURE_TMbit(29) /* Thermal Monitor (TM1) */
138#define CPUID_FEATURE_PBEbit(31) /* Pend Break Enable */
139
140#define CPUID_FEATURE_SSE3hbit(0) /* Streaming SIMD extensions 3 */
141#define CPUID_FEATURE_PCLMULQDQhbit(1) /* PCLMULQDQ Instruction */
142#define CPUID_FEATURE_DTES64hbit(2) /* 64-bit DS layout */
143#define CPUID_FEATURE_MONITORhbit(3) /* Monitor/mwait */
144#define CPUID_FEATURE_DSCPLhbit(4) /* Debug Store CPL */
145#define CPUID_FEATURE_VMXhbit(5) /* VMX */
146#define CPUID_FEATURE_SMXhbit(6) /* SMX */
147#define CPUID_FEATURE_ESThbit(7) /* Enhanced SpeedsTep (GV3) */
148#define CPUID_FEATURE_TM2hbit(8) /* Thermal Monitor 2 */
149#define CPUID_FEATURE_SSSE3hbit(9) /* Supplemental SSE3 instructions */
150#define CPUID_FEATURE_CIDhbit(10) /* L1 Context ID */
151#define CPUID_FEATURE_SEGLIM64hbit(11) /* 64-bit segment limit checking */
152#define CPUID_FEATURE_FMAhbit(12) /* Fused-Multiply-Add support */
153#define CPUID_FEATURE_CX16hbit(13) /* CmpXchg16b instruction */
154#define CPUID_FEATURE_xTPRhbit(14) /* Send Task PRiority msgs */
155#define CPUID_FEATURE_PDCMhbit(15) /* Perf/Debug Capability MSR */
156
157#define CPUID_FEATURE_PCIDhbit(17) /* ASID-PCID support */
158#define CPUID_FEATURE_DCAhbit(18) /* Direct Cache Access */
159#define CPUID_FEATURE_SSE4_1hbit(19) /* Streaming SIMD extensions 4.1 */
160#define CPUID_FEATURE_SSE4_2hbit(20) /* Streaming SIMD extensions 4.2 */
161#define CPUID_FEATURE_x2APIChbit(21) /* Extended APIC Mode */
162#define CPUID_FEATURE_MOVBEhbit(22) /* MOVBE instruction */
163#define CPUID_FEATURE_POPCNThbit(23) /* POPCNT instruction */
164#define CPUID_FEATURE_TSCTMRhbit(24) /* TSC deadline timer */
165#define CPUID_FEATURE_AEShbit(25) /* AES instructions */
166#define CPUID_FEATURE_XSAVEhbit(26) /* XSAVE instructions */
167#define CPUID_FEATURE_OSXSAVEhbit(27) /* XGETBV/XSETBV instructions */
168#define CPUID_FEATURE_AVX1_0hbit(28) /* AVX 1.0 instructions */
169#define CPUID_FEATURE_F16Chbit(29) /* Float16 convert instructions */
170#define CPUID_FEATURE_RDRANDhbit(30) /* RDRAND instruction */
171#define CPUID_FEATURE_VMMhbit(31) /* VMM (Hypervisor) present */
172
173/*
174 * Leaf 7, subleaf 0 additional features.
175 * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
176 */
177#define CPUID_LEAF7_FEATURE_RDWRFSGSbit(0)/* FS/GS base read/write */
178#define CPUID_LEAF7_FEATURE_TSCOFFbit(1)/* TSC thread offset */
179#define CPUID_LEAF7_FEATURE_BMI1bit(3)/* Bit Manipulation Instrs, set 1 */
180#define CPUID_LEAF7_FEATURE_HLEbit(4)/* Hardware Lock Elision*/
181#define CPUID_LEAF7_FEATURE_AVX2bit(5)/* AVX2 Instructions */
182#define CPUID_LEAF7_FEATURE_SMEPbit(7)/* Supervisor Mode Execute Protect */
183#define CPUID_LEAF7_FEATURE_BMI2bit(8)/* Bit Manipulation Instrs, set 2 */
184#define CPUID_LEAF7_FEATURE_ENFSTRGbit(9)/* ENhanced Fast STRinG copy */
185#define CPUID_LEAF7_FEATURE_INVPCIDbit(10)/* INVPCID intruction, TDB */
186#define CPUID_LEAF7_FEATURE_RTMbit(11)/* TBD */
187
188/*
189 * The CPUID_EXTFEATURE_XXX values define 64-bit values
190 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
191 */
192#define CPUID_EXTFEATURE_SYSCALLbit(11)/* SYSCALL/sysret */
193#define CPUID_EXTFEATURE_XDbit(20)/* eXecute Disable */
194
195#define CPUID_EXTFEATURE_1GBPAGEbit(26)/* 1GB pages support */
196#define CPUID_EXTFEATURE_RDTSCPbit(27)/* RDTSCP */
197#define CPUID_EXTFEATURE_EM64Tbit(29)/* Extended Mem 64 Technology */
198
199
200#define CPUID_EXTFEATURE_LAHFhbit(0)/* LAFH/SAHF instructions */
201
202/*
203 * The CPUID_EXTFEATURE_XXX values define 64-bit values
204 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
205 */
206#define CPUID_EXTFEATURE_TSCIbit(8)/* TSC Invariant */
207
208#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
209
210#define CPUID_MWAIT_EXTENSIONbit(0)/* enumeration of WMAIT extensions */
211#define CPUID_MWAIT_BREAKbit(1)/* interrupts are break events */
212
213//-- processor type -> p_type:
214#define PT_OEM0x00// Intel Original OEM Processor;
215#define PT_OD0x01 // Intel Over Drive Processor;
216#define PT_DUAL0x02// Intel Dual Processor;
217#define PT_RES0x03// Intel Reserved;
218
219/* Known MSR registers */
220#define MSR_IA32_PLATFORM_ID0x0017
221#define IA32_APIC_BASE0x001B /* used also for AMD */
222#define MSR_CORE_THREAD_COUNT0x0035/* limited use - not for Penryn or older */
223#define IA32_TSC_ADJUST0x003B
224#define MSR_IA32_BIOS_SIGN_ID0x008B/* microcode version */
225#define MSR_FSB_FREQ0x00CD/* limited use - not for i7 */
226#defineMSR_PLATFORM_INFO0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
227/* turbo for penryn */
228#define MSR_PKG_CST_CONFIG_CONTROL0x00E2// sandy and ivy
229#define MSR_PMG_IO_CAPTURE_BASE0x00E4
230#define IA32_MPERF0x00E7// TSC in C0 only
231#define IA32_APERF0x00E8// actual clocks in C0
232#define MSR_IA32_EXT_CONFIG0x00EE// limited use - not for i7
233#define MSR_FLEX_RATIO0x0194// limited use - not for Penryn or older
234//see no value on most CPUs
235#defineMSR_IA32_PERF_STATUS0x0198
236#define MSR_IA32_PERF_CONTROL0x0199
237#define MSR_IA32_CLOCK_MODULATION0x019A
238#define MSR_THERMAL_STATUS0x019C
239#define MSR_IA32_MISC_ENABLE0x01A0
240#define MSR_THERMAL_TARGET0x01A2// TjMax limited use - not for Penryn or older
241#define MSR_MISC_PWR_MGMT0x01AA
242#define MSR_TURBO_RATIO_LIMIT0x01AD// limited use - not for Penryn or older
243
244#define IA32_ENERGY_PERF_BIAS0x01B0
245#define MSR_PACKAGE_THERM_STATUS0x01B1
246#define IA32_PLATFORM_DCA_CAP0x01F8
247#define MSR_POWER_CTL0x01FC// MSR 000001FC 0000-0000-0004-005F
248
249// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
250#define MSR_RAPL_POWER_UNIT0x606// R/O
251//MSR 00000606 0000-0000-000A-1003
252#define MSR_PKGC3_IRTL0x60A// RW time limit to go C3
253// bit 15 = 1 -- the value valid for C-state PM
254#define MSR_PKGC6_IRTL0x60B// RW time limit to go C6
255//MSR 0000060B 0000-0000-0000-8854
256//Valid + 010=1024ns + 0x54=84mks
257#define MSR_PKGC7_IRTL0x60C// RW time limit to go C7
258//MSR 0000060C 0000-0000-0000-8854
259#define MSR_PKG_C2_RESIDENCY0x60D// same as TSC but in C2 only
260
261#define MSR_PKG_RAPL_POWER_LIMIT0x610//MSR 00000610 0000-A580-0000-8960
262#define MSR_PKG_ENERGY_STATUS0x611//MSR 00000611 0000-0000-3212-A857
263#define MSR_PKG_POWER_INFO0x614//MSR 00000614 0000-0000-01E0-02F8
264
265// Sandy Bridge IA (Core) domain MSR's.
266#define MSR_PP0_POWER_LIMIT0x638
267#define MSR_PP0_ENERGY_STATUS0x639
268#define MSR_PP0_POLICY0x63A
269#define MSR_PP0_PERF_STATUS0x63B
270
271// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
272#define MSR_PP1_POWER_LIMIT0x640
273#define MSR_PP1_ENERGY_STATUS 0x641
274//MSR 00000641 0000-0000-0000-0000
275#define MSR_PP1_POLICY0x642
276
277// JakeTown only Memory MSR's.
278#define MSR_PKG_PERF_STATUS0x613
279#define MSR_DRAM_POWER_LIMIT 0x618
280#define MSR_DRAM_ENERGY_STATUS0x619
281#define MSR_DRAM_PERF_STATUS0x61B
282#define MSR_DRAM_POWER_INFO0x61C
283
284//IVY_BRIDGE
285#define MSR_CONFIG_TDP_NOMINAL0x648
286#define MSR_CONFIG_TDP_LEVEL10x649
287#define MSR_CONFIG_TDP_LEVEL20x64A
288#define MSR_CONFIG_TDP_CONTROL0x64B// write once to lock
289#define MSR_TURBO_ACTIVATION_RATIO0x64C
290
291/* AMD Defined MSRs */
292#define MSR_K6_EFER0xC0000080
293#define MSR_K6_STAR0xC0000081
294#define MSR_K6_WHCR0xC0000082
295#define MSR_K6_UWCCR0xC0000085
296#define MSR_K6_EPMR0xC0000086
297#define MSR_K6_PSOR0xC0000087
298#define MSR_K6_PFIR0xC0000088
299
300#define MSR_K7_EVNTSEL00xC0010000
301#define MSR_K7_PERFCTR00xC0010004
302#define MSR_K7_HWCR0xC0010015
303#define MSR_K7_CLK_CTL0xC001001b
304#define MSR_K7_FID_VID_CTL0xC0010041
305
306#define K8_FIDVID_STATUS0xC0010042
307#define K10_COFVID_LIMIT0xC0010061// max enabled p-state (msr >> 4) & 7
308#define K10_COFVID_CONTROL0xC0010062// switch to p-state
309#define K10_PSTATE_STATUS0xC0010064
310#define K10_COFVID_STATUS0xC0010071// current p-state (msr >> 16) & 7
311
312#define MSR_AMD_MPERF0x000000E7
313#define MSR_AMD_APERF0x000000E8
314
315#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
316
317// DFE: This constant comes from older xnu:
318#define CLKNUM1193182/* formerly 1193167 */
319
320/* CPU Features */
321#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
322#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
323#define CPU_FEATURE_SSE20x00000004// SSE2 Instruction Set
324#define CPU_FEATURE_SSE30x00000008// SSE3 Instruction Set
325#define CPU_FEATURE_SSE410x00000010// SSE41 Instruction Set
326#define CPU_FEATURE_SSE420x00000020// SSE42 Instruction Set
327#define CPU_FEATURE_EM64T0x00000040// 64Bit Support
328#define CPU_FEATURE_HTT0x00000080// HyperThreading
329#define CPU_FEATURE_MOBILE0x00000100// Mobile CPU
330#define CPU_FEATURE_MSR0x00000200// MSR Support
331
332/* SMBIOS Memory Types */
333#define SMB_MEM_TYPE_UNDEFINED0
334#define SMB_MEM_TYPE_OTHER1
335#define SMB_MEM_TYPE_UNKNOWN2
336#define SMB_MEM_TYPE_DRAM3
337#define SMB_MEM_TYPE_EDRAM4
338#define SMB_MEM_TYPE_VRAM5
339#define SMB_MEM_TYPE_SRAM6
340#define SMB_MEM_TYPE_RAM7
341#define SMB_MEM_TYPE_ROM8
342#define SMB_MEM_TYPE_FLASH9
343#define SMB_MEM_TYPE_EEPROM10
344#define SMB_MEM_TYPE_FEPROM11
345#define SMB_MEM_TYPE_EPROM12
346#define SMB_MEM_TYPE_CDRAM13
347#define SMB_MEM_TYPE_3DRAM14
348#define SMB_MEM_TYPE_SDRAM15
349#define SMB_MEM_TYPE_SGRAM16
350#define SMB_MEM_TYPE_RDRAM17
351#define SMB_MEM_TYPE_DDR18
352#define SMB_MEM_TYPE_DDR219
353#define SMB_MEM_TYPE_FBDIMM20
354#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
355#define SMB_MEM_TYPE_DDR426
356
357/* Memory Configuration Types */
358#define SMB_MEM_CHANNEL_UNKNOWN0
359#define SMB_MEM_CHANNEL_SINGLE1
360#define SMB_MEM_CHANNEL_DUAL2
361#define SMB_MEM_CHANNEL_TRIPLE3
362
363/* Maximum number of ram slots */
364#define MAX_RAM_SLOTS8
365
366#define RAM_SLOT_ENUMERATOR{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}
367
368/* Maximum number of SPD bytes */
369#define MAX_SPD_SIZE256
370
371/* Size of SMBIOS UUID in bytes */
372#define UUID_LEN16
373
374typedef struct _RamSlotInfo_t
375{
376uint32_tModuleSize;// Size of Module in MB
377uint32_tFrequency;// in Mhz
378const char*Vendor;
379const char*PartNo;
380const char*SerialNo;
381char*spd;// SPD Dump
382boolInUse;
383uint8_tType;
384uint8_tBankConnections;// table type 6, see (3.3.7)
385uint8_tBankConnCnt;
386} RamSlotInfo_t;
387
388//==============================================================================
389
390typedef struct _PlatformInfo_t
391{
392struct CPU {
393uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
394uint32_tVendor;// Vendor
395uint32_tCoresPerPackage;
396uint32_tLogicalPerPackage;
397uint32_tSignature;// Processor Signature
398uint32_tStepping;// Stepping
399//uint16_tType;// Type
400uint32_tModel;// Model
401uint32_tExtModel;// Extended Model
402uint32_tFamily;// Family
403uint32_tExtFamily;// Extended Family
404uint32_tNoCores;// No Cores per Package
405uint32_tNoThreads;// Threads per Package
406uint8_tMaxCoef;// Max Multiplier
407uint8_tMaxDiv;// Min Multiplier
408uint8_tCurrCoef;// Current Multiplier
409uint8_tCurrDiv;
410uint64_tTSCFrequency;// TSC Frequency Hz
411uint64_tFSBFrequency;// FSB Frequency Hz
412uint64_tCPUFrequency;// CPU Frequency Hz
413uint32_tMaxRatio;// Max Bus Ratio
414uint32_tMinRatio;// Min Bus Ratio
415charBrandString[48];// 48 Byte Branding String
416uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
417
418} CPU;
419
420struct RAM {
421uint64_tFrequency;// Ram Frequency
422uint32_tDivider;// Memory divider
423uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
424uint8_tTRC;
425uint8_tTRP;
426uint8_tRAS;
427uint8_tChannels;// Channel Configuration Single,Dual, Triple or Quad
428uint8_tNoSlots;// Maximum no of slots available
429uint8_tType;// Standard SMBIOS v2.5 Memory Type
430RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
431} RAM;
432
433struct DMI {
434intMaxMemorySlots;// number of memory slots populated by SMBIOS
435intCntMemorySlots;// number of memory slots counted
436intMemoryModules;// number of memory modules installed
437intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
438} DMI;
439
440uint8_tType;// system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)
441uint8_t*UUID;// system-id (SMBIOS Table 1: system uuid)
442uint32_tHWSignature;// machine-signature (FACS: Hardware Signature)
443} PlatformInfo_t;
444
445extern PlatformInfo_t Platform;
446
447#endif /* !__LIBSAIO_PLATFORM_H */
448

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