Chameleon

Chameleon Svn Source Tree

Root/trunk/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12␉#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16␉#define DBG(x...)␉printf(x)␊
17#else␊
18␉#define DBG(x...)␊
19#endif␊
20␊
21#define XEON "Xeon"␊
22#define CORE_I3 "Core(TM) i3"␊
23#define CORE_I5 "Core(TM) i5"␊
24#define CORE_I7 "Core(TM) i7"␊
25␊
26bool getProcessorInformationExternalClock(returnType *value)␊
27{␊
28␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
29␉{␊
30␉␉switch (Platform.CPU.Family)␊
31␉␉{␊
32␉␉␉case 0x06:␊
33␉␉␉␉switch (Platform.CPU.Model)␊
34␉␉␉␉{␊
35␉␉␉␉␉// set external clock to 0 for SANDY␊
36␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
37␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
38␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
39␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
40␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
41␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
42␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
43␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
44␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
45␊
46␉␉␉␉␉␉value->word = 0;␊
47␉␉␉␉␉␉break;␊
48␉␉␉␉␉default:␊
49␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
50␉␉␉␉␉␉break;␊
51␉␉␉␉}␊
52␉␉␉␉break;␊
53␊
54␉␉␉default:␊
55␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
56␉␉␉␉break;␊
57␉␉}␊
58␉}␊
59␉else␊
60␉{␊
61␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
62␉}␊
63␊
64␉return true;␊
65}␊
66␊
67bool getProcessorInformationMaximumClock(returnType *value)␊
68{␊
69␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
70␉return true;␊
71}␊
72␊
73bool getSMBOemProcessorBusSpeed(returnType *value)␊
74{␊
75␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
76␉{␊
77␉␉switch (Platform.CPU.Family)␊
78␉␉{␊
79␉␉␉case 0x06:␊
80␉␉␉␉switch (Platform.CPU.Model)␊
81␉␉␉␉{␊
82␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
83␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
84␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
85␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
86␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
87␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
88␉␉␉␉␉␉return false;␊
89␊
90␉␉␉␉␉case 0x19:␊
91␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
92␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
93␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
94␉␉␉␉␉case CPUID_MODEL_DALES:␉// Intel Core i3, i5 LGA1156 (32nm)␊
95␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
96␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
97␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
98␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
99␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
100␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
101␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
102␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
103␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
104␉␉␉␉␉{␊
105␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
106␉␉␉␉␉␉int nhm_bus = 0x3F;␊
107␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
108␉␉␉␉␉␉unsigned long did, vid;␊
109␉␉␉␉␉␉unsigned int i;␊
110␉␉␉␉␉␉␊
111␉␉␉␉␉␉// Nehalem supports Scrubbing␊
112␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
113␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
114␉␉␉␉␉␉{␊
115␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
116␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
117␉␉␉␉␉␉␉vid &= 0xFFFF;␊
118␉␉␉␉␉␉␉did &= 0xFF00;␊
119␉␉␉␉␉␉␉␊
120␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
121␉␉␉␉␉␉␉{␊
122␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
123␉␉␉␉␉␉␉}␊
124␉␉␉␉␉␉}␊
125␊
126␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
127␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
128␉␉␉␉␉␉qpimult &= 0x7F;␊
129␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
130␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
131␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
132␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
133␉␉␉␉␉␉{␊
134␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
135␉␉␉␉␉␉}␊
136␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
137␉␉␉␉␉␉value->word = qpibusspeed;␊
138␉␉␉␉␉␉return true;␊
139␉␉␉␉␉}␊
140␉␉␉␉␉break;␊
141␊
142␉␉␉␉␉default:␊
143␉␉␉␉␉␉break;␊
144␉␉␉␉}␊
145␉␉␉␉break;␊
146␊
147␉␉␉default:␊
148␉␉␉␉break;␊
149␉␉}␊
150␉}␊
151␊
152␉return false; //Unsupported CPU type␊
153}␊
154␊
155//bool getSMBOemPlatformFeature(returnType *value)␊
156//{␊
157// value->word = (uint64_t)(0x0000000000000001);␊
158// return true;␊
159//}␊
160␊
161uint16_t simpleGetSMBOemProcessorType(void)␊
162{␊
163␉if (Platform.CPU.NoCores >= 4)␊
164␉{␊
165␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊
166␉}␊
167␉else if (Platform.CPU.NoCores == 1)␊
168␉{␊
169␉␉return 0x201;␉// 513 - Core Duo␊
170␉};␊
171␉␊
172␉return 0x301;␉␉// 769 - Core 2 Duo␊
173}␊
174␊
175bool getSMBOemProcessorType(returnType *value)␊
176{␊
177␉static bool done = false;␊
178␊
179␉value->word = simpleGetSMBOemProcessorType();␊
180␊
181␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
182␉{␊
183␉␉if (!done)␊
184␉␉{␊
185␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
186␉␉␉done = true;␊
187␉␉}␊
188␊
189␉␉switch (Platform.CPU.Family)␊
190␉␉{␊
191␉␉␉case 0x0F:␊
192␉␉␉case 0x06:␊
193␊
194␉␉␉␉switch (Platform.CPU.Model)␊
195␉␉␉␉{␊
196␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
197␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
198␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
199␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
200␊
201␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
202␉␉␉␉␉␉{␊
203␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
204␉␉␉␉␉␉␉return true;␊
205␉␉␉␉␉␉}␊
206␊
207␉␉␉␉␉␉return true;␊
208␊
209␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
210␉␉␉␉␉case CPUID_MODEL_CELERON:␊
211␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
212␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
213␉␉␉␉␉␉return true;␊
214␊
215␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
216␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
217␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
218␊
219␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
220␉␉␉␉␉␉{␊
221␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
222␉␉␉␉␉␉␉return true;␊
223␉␉␉␉␉␉}␊
224␊
225␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
226␉␉␉␉␉␉{␊
227␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
228␉␉␉␉␉␉␉return true;␊
229␉␉␉␉␉␉}␊
230␉␉␉␉␉␉else␊
231␉␉␉␉␉␉{␊
232␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
233␉␉␉␉␉␉␉return true;␊
234␉␉␉␉␉␉}␊
235␊
236␉␉␉␉␉␉return true;␊
237␊
238␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
239␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
240␊
241␉␉␉␉␉␉return true;␊
242␊
243␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
244␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
245␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
246␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
247␊
248␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
249␉␉␉␉␉␉{␊
250␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
251␉␉␉␉␉␉␉return true;␊
252␉␉␉␉␉␉}␊
253␊
254␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
255␉␉␉␉␉␉{␊
256␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
257␉␉␉␉␉␉␉return true;␊
258␉␉␉␉␉␉}␊
259␊
260␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
261␉␉␉␉␉␉{␊
262␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
263␉␉␉␉␉␉␉return true;␊
264␉␉␉␉␉␉}␊
265␊
266␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
267␉␉␉␉␉␉{␊
268␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
269␉␉␉␉␉␉␉return true;␊
270␉␉␉␉␉␉}␊
271␊
272␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
273␉␉␉␉␉␉{␊
274␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
275␉␉␉␉␉␉␉return true;␊
276␉␉␉␉␉␉}␊
277␊
278␉␉␉␉␉␉return true;␊
279␊
280␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
281␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
282␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
283␊
284␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
285␉␉␉␉␉␉{␊
286␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
287␉␉␉␉␉␉␉return true;␊
288␉␉␉␉␉␉}␊
289␊
290␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
291␉␉␉␉␉␉{␊
292␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
293␉␉␉␉␉␉␉return true;␊
294␉␉␉␉␉␉}␊
295␊
296␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
297␉␉␉␉␉␉{␊
298␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
299␉␉␉␉␉␉␉return true;␊
300␉␉␉␉␉␉}␊
301␊
302␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
303␉␉␉␉␉␉{␊
304␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
305␉␉␉␉␉␉␉return true;␊
306␉␉␉␉␉␉}␊
307␊
308␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
309␉␉␉␉␉␉{␊
310␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
311␉␉␉␉␉␉␉return true;␊
312␉␉␉␉␉␉}␊
313␊
314␉␉␉␉␉␉return true;␊
315␊
316␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
317␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
318␊
319␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
320␉␉␉␉␉␉{␊
321␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
322␉␉␉␉␉␉␉return true;␊
323␉␉␉␉␉␉}␊
324␊
325␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
326␉␉␉␉␉␉{␊
327␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
328␉␉␉␉␉␉␉return true;␊
329␉␉␉␉␉␉}␊
330␊
331␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
332␉␉␉␉␉␉{␊
333␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
334␉␉␉␉␉␉␉return true;␊
335␉␉␉␉␉␉}␊
336␊
337␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
338␉␉␉␉␉␉{␊
339␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
340␉␉␉␉␉␉␉return true;␊
341␉␉␉␉␉␉}␊
342␊
343␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
344␉␉␉␉␉␉{␊
345␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
346␉␉␉␉␉␉␉return true;␊
347␉␉␉␉␉␉}␊
348␊
349␉␉␉␉␉␉return true;␊
350␊
351␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
352␊
353␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
354␉␉␉␉␉␉{␊
355␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
356␉␉␉␉␉␉␉return true;␊
357␉␉␉␉␉␉}␊
358␊
359␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
360␉␉␉␉␉␉{␊
361␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
362␉␉␉␉␉␉␉return true;␊
363␉␉␉␉␉␉}␊
364␊
365␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
366␉␉␉␉␉␉{␊
367␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
368␉␉␉␉␉␉␉return true;␊
369␉␉␉␉␉␉}␊
370␊
371␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
372␉␉␉␉␉␉{␊
373␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
374␉␉␉␉␉␉␉return true;␊
375␉␉␉␉␉␉}␊
376␊
377␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
378␉␉␉␉␉␉{␊
379␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
380␉␉␉␉␉␉␉return true;␊
381␉␉␉␉␉␉}␊
382␊
383␉␉␉␉␉␉return true;␊
384␊
385␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␉␉␉// 0x3D -␊
386␊
387␉␉␉␉␉␉value->word = 0x606;␉␉␉// 1542␊
388␉␉␉␉␉␉return true;␊
389␊
390␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
391␊
392␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
393␉␉␉␉␉␉return true;␊
394␊
395␉␉␉␉␉case CPUID_MODEL_ATOM_3700:␉␉␉// 0x37 -␊
396␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊
397␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
398␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
399␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46 -␊
400␊
401␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
402␉␉␉␉␉␉{␊
403␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
404␉␉␉␉␉␉␉return true;␊
405␉␉␉␉␉␉}␊
406␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
407␉␉␉␉␉␉{␊
408␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
409␉␉␉␉␉␉␉return true;␊
410␉␉␉␉␉␉}␊
411␊
412␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
413␉␉␉␉␉␉{␊
414␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
415␉␉␉␉␉␉␉return true;␊
416␉␉␉␉␉␉}␊
417␊
418␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
419␉␉␉␉␉␉{␊
420␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
421␉␉␉␉␉␉␉return true;␊
422␉␉␉␉␉␉}␊
423␊
424␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
425␉␉␉␉␉␉{␊
426␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
427␉␉␉␉␉␉␉return true;␊
428␉␉␉␉␉␉}␊
429␊
430␉␉␉␉␉␉return true;␊
431␊
432␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
433␊
434␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
435␉␉␉␉␉␉return true;␊
436␊
437␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
438␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
439␊
440␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
441␉␉␉␉␉␉return true;␊
442␊
443␉␉␉␉␉default:␊
444␊
445␉␉␉␉␉␉return true;␊
446␉␉␉␉␉␉break; // Unsupported CPU type␊
447␉␉␉␉}␊
448␉␉␉␉break;␊
449␊
450␉␉␉default:␊
451␉␉␉␉break;␊
452␉␉}␊
453␉}␊
454/*␊
455␉if (Platform.CPU.Vendor == CPUID_VENDOR_AMD) // AMD␊
456␉{␊
457␉␉value->word = simpleGetSMBOemProcessorType();␊
458␉␉return true;␊
459␉}␊
460*/␊
461␉return false;␊
462}␊
463␊
464bool getSMBMemoryDeviceMemoryType(returnType *value)␊
465{␊
466␉static int idx = -1;␊
467␉int␉map;␊
468␊
469␉if (!bootInfo->memDetect)␊
470␉{␊
471␉␉return false;␊
472␉}␊
473␊
474␉idx++;␊
475␉if (idx < MAX_RAM_SLOTS)␊
476␉{␊
477␉␉map = Platform.DMI.DIMM[idx];␊
478␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
479␉␉{␊
480␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
481␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
482␉␉␉return true;␊
483␉␉}␊
484␉}␊
485␊
486␉value->byte = 2; // means Unknown␊
487␉return true;␊
488//␉value->byte = SMB_MEM_TYPE_DDR2;␊
489//␉return true;␊
490}␊
491␊
492bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
493{␊
494␉value->word = 0xFFFF;␊
495␉return true;␊
496}␊
497␊
498bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
499{␊
500␉static int idx = -1;␊
501␉int␉map;␊
502␊
503␉if (!bootInfo->memDetect)␊
504␉{␊
505␉␉return false;␊
506␉}␊
507␊
508␉idx++;␊
509␉if (idx < MAX_RAM_SLOTS)␊
510␉{␊
511␉␉map = Platform.DMI.DIMM[idx];␊
512␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
513␉␉{␊
514␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
515␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
516␉␉␉return true;␊
517␉␉}␊
518␉}␊
519␊
520␉value->dword = 0; // means Unknown␊
521␉return true;␊
522//␉value->dword = 800;␊
523//␉return true;␊
524}␊
525␊
526bool getSMBMemoryDeviceManufacturer(returnType *value)␊
527{␊
528␉static int idx = -1;␊
529␉int␉map;␊
530␊
531␉if (!bootInfo->memDetect)␊
532␉{␊
533␉␉return false;␊
534␉}␊
535␊
536␉idx++;␊
537␉if (idx < MAX_RAM_SLOTS)␊
538␉{␊
539␉␉map = Platform.DMI.DIMM[idx];␊
540␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
541␉␉{␊
542␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
543␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
544␉␉␉return true;␊
545␉␉}␊
546␉}␊
547␊
548␉value->string = NOT_AVAILABLE;␊
549␉return true;␊
550}␊
551␊
552bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
553{␊
554␉static int idx = -1;␊
555␉int␉map;␊
556␊
557␉if (!bootInfo->memDetect)␊
558␉{␊
559␉␉return false;␊
560␉}␊
561␊
562␉idx++;␊
563␊
564␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
565␊
566␉if (idx < MAX_RAM_SLOTS)␊
567␉{␊
568␉␉map = Platform.DMI.DIMM[idx];␊
569␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
570␉␉{␊
571␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
572␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
573␉␉␉return true;␊
574␉␉}␊
575␉}␊
576␊
577␉value->string = NOT_AVAILABLE;␊
578␉return true;␊
579}␊
580␊
581bool getSMBMemoryDevicePartNumber(returnType *value)␊
582{␊
583␉static int idx = -1;␊
584␉int␉map;␊
585␊
586␉if (!bootInfo->memDetect)␊
587␉{␊
588␉␉return false;␊
589␉}␊
590␊
591␉idx++;␊
592␉if (idx < MAX_RAM_SLOTS)␊
593␉{␊
594␉␉map = Platform.DMI.DIMM[idx];␊
595␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
596␉␉{␊
597␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
598␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
599␉␉␉return true;␊
600␉␉}␊
601␉}␊
602␊
603␉value->string = NOT_AVAILABLE;␊
604␉return true;␊
605}␊
606␊
607␊
608// getting smbios addr with fast compare ops, late checksum testing ...␊
609#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
610static const char * const SMTAG = "_SM_";␊
611static const char* const DMITAG = "_DMI_";␊
612␊
613SMBEntryPoint *getAddressOfSmbiosTable(void)␊
614{␊
615␉SMBEntryPoint␉*smbios;␊
616␉/*␊
617␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
618␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
619␉ */␊
620␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
621␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊
622␉{␊
623␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
624␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
625␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
626␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
627␉␉{␊
628␉␉␉return smbios;␊
629␉ }␊
630␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
631␉}␊
632␉printf("ERROR: Unable to find SMBIOS!\n");␊
633␉pause();␊
634␉return NULL;␊
635}␊
636␊
637

Archive Download this file

Revision: 2687