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Root/trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19␉#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23␉#define DBG(x...)␉printf(x)␊
24#else␊
25␉#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM",␉␉␉␉/* 00h Undefined */␊
31␉"STD FPM DRAM",␉␉␉/* 01h FPM */␊
32␉"EDO",␉␉␉␉/* 02h EDO */␊
33␉"PIPE NIBBLE",␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM",␉␉␉/* 04h SDRAM */␊
35␉"ROM",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉␉␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉␉␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM",␉␉␉/* 08h SDRAM DDR 2 */␊
39␉"DDR2 SDRAM FB-DIMM",␉␉/* 09h Undefined */␊
40␉"DDR2 SDRAM FB-DIMM Probe",␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM",␉␉␉/* 0Bh SDRAM DDR 3 */␊
42␉"DDR4 SDRAM"␉␉␉/* 0Ch SDRAM DDR 4 */␊
43};␊
44␊
45#define UNKNOWN_MEM_TYPE 2␊
46static uint8_t spd_mem_to_smbios[] =␊
47{␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
51␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
52␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
53␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
54␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
55␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
56␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
58␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
59␉SMB_MEM_TYPE_DDR3,␉␉/* 0Bh SDRAM DDR 3 */␊
60␉SMB_MEM_TYPE_DDR4␉␉/* 0Ch SDRAM DDR 4 */␊
61};␊
62#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
63␊
64#define rdtsc(low,high) \␊
65__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
66␊
67#define SMBHSTSTS 0␊
68#define SMBHSTCNT 2␊
69#define SMBHSTCMD 3␊
70#define SMBHSTADD 4␊
71#define SMBHSTDAT 5␊
72#define SBMBLKDAT 7␊
73␊
74int spd_indexes[] = {␊
75␉SPD_MEMORY_TYPE,␊
76␉SPD_DDR3_MEMORY_BANK,␊
77␉SPD_DDR3_MEMORY_CODE,␊
78␉SPD_NUM_ROWS,␊
79␉SPD_NUM_COLUMNS,␊
80␉SPD_NUM_DIMM_BANKS,␊
81␉SPD_NUM_BANKS_PER_SDRAM,␊
82␉4,7,8,9,12,64, /* TODO: give names to these values */␊
83␉95,96,97,98, 122,123,124,125 /* UIS */␊
84};␊
85#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
86␊
87/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
88␊
89unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
90{␊
91␉int l1, h1, l2, h2;␊
92␉unsigned long long t;␊
93␊
94␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
95␉outb(base + SMBHSTDAT, 0xff);␊
96␊
97␉rdtsc(l1, h1);␊
98␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
99␉{␊
100␉␉rdtsc(l2, h2);␊
101␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
102␉␉if (t > 5)␊
103␉␉{␊
104␉␉␉return 0xFF;␉// break␊
105␉␉}␊
106␉}␊
107␊
108␉outb(base + SMBHSTCMD, cmd);␊
109␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
110␉outb(base + SMBHSTCNT, 0x48 );␊
111␊
112␉rdtsc(l1, h1);␊
113␊
114␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait till command finished␊
115␉{␊
116␉␉rdtsc(l2, h2);␊
117␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
118␉␉if (t > 5)␊
119␉␉{␊
120␉␉␉break;␉// break after 5ms␊
121␉␉}␊
122␉}␊
123␉return inb(base + SMBHSTDAT);␊
124}␊
125␊
126/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
127#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
128␊
129/** Read from spd *used* values only*/␊
130static void init_spd(char *spd, uint32_t base, int slot)␊
131{␊
132␉int i;␊
133␉for (i = 0; i < SPD_INDEXES_SIZE; i++)␊
134␉{␊
135␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
136␉}␊
137}␊
138␊
139// Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,␊
140// have different formats, always return a valid ptr.␊
141const char *getVendorName(RamSlotInfo_t *slot, uint32_t base, int slot_num)␊
142{␊
143␉uint8_t bank = 0;␊
144␉uint8_t code = 0;␊
145␉int i = 0;␊
146␉uint8_t *spd = (uint8_t *) slot->spd;␊
147␊
148␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
149␉{␊
150␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
151␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
152␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
153␉␉{␊
154␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
155␉␉␉{␊
156␉␉␉␉return vendorMap[i].name;␊
157␉␉␉}␊
158␉␉}␊
159␉}␊
160␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
161␉{␊
162␉␉if(spd[64]==0x7f)␊
163␉␉{␊
164␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
165␉␉␉{␊
166␉␉␉␉bank++;␊
167␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
168␉␉␉}␊
169␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
170␉␉␉code = spd[i];␊
171␉␉}␊
172␉␉else␊
173␉␉{␊
174␉␉␉code = spd[64];␊
175␉␉␉bank = 0;␊
176␉␉}␊
177␊
178␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
179␉␉{␊
180␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
181␉␉␉{␊
182␉␉␉␉return vendorMap[i].name;␊
183␉␉␉}␊
184␉␉}␊
185␉}␊
186␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
187␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊
188␉␉return "Unifosa";␊
189␉}␊
190␉return "NoName";␊
191}␊
192␊
193/* Get Default Memory Module Speed (no overclocking handled) */␊
194int getDDRspeedMhz(const char * spd)␊
195{␊
196␊
197␉if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))␊
198␉{␊
199␉␉switch(spd[9])␊
200␉␉{␊
201␉␉␉case 0x50:␊
202␉␉␉␉return 400;␊
203␉␉␉case 0x3d:␊
204␉␉␉␉return 533;␊
205␉␉␉case 0x30:␊
206␉␉␉␉return 667;␊
207␉␉␉case 0x25:␊
208␉␉␉default:␊
209␉␉␉␉return 800;␊
210␉␉␉case 0x1E:␊
211␉␉␉␉return 1066;␊
212␉␉}␊
213␉}␊
214␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
215␉{␊
216␉␉switch(spd[12])␊
217␉␉{␊
218␉␉␉case 0x0f:␊
219␉␉␉␉return 1066;␊
220␉␉␉case 0x0c:␊
221␉␉␉␉return 1333;␊
222␉␉␉case 0x0a:␊
223␉␉␉␉return 1600;␊
224␉␉␉case 0x14:␊
225␉␉␉default:␊
226␉␉␉␉return 800;␊
227␉␉}␊
228␉}␊
229␉return 800; // default freq for unknown types␊
230}␊
231␊
232#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
233#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
234␊
235/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
236const char *getDDRSerial(const char *spd)␊
237{␊
238␉static char asciiSerial[17];␊
239␊
240␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
241␉{␊
242␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
243␉}␊
244␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
245␉{␊
246␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
247␉}␊
248␉else␊
249␉{␊
250␉␉strcpy(asciiSerial, "0000000000000000");␊
251␉}␊
252␊
253␉return strdup(asciiSerial);␊
254}␊
255␊
256/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
257const char *getDDRPartNum(char *spd, uint32_t base, int slot)␊
258{␊
259␉int i, start = 0, index = 0;␊
260␉char c;␊
261␉static char asciiPartNo[32];␊
262␊
263␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
264␉{␊
265␉␉start = 128;␊
266␉}␊
267␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR)␊
268␉{␊
269␉␉start = 73;␊
270␉}␊
271␉␊
272␉// Check that the spd part name is zero terminated and that it is ascii:␊
273␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
274␉for (i = start; i < start + sizeof(asciiPartNo); i++)␊
275␉{␊
276␉␉READ_SPD(spd, base, slot, (uint8_t)i); // only read once the corresponding model part (ddr3 or ddr2)␊
277␉␉c = spd[i];␊
278␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
279␉␉{␊
280␉␉␉// It seems that System Profiler likes only letters and digits...␊
281␉␉␉asciiPartNo[index++] = c;␊
282␉␉}␊
283␉␉else if (!isascii(c))␊
284␉␉{␊
285␉␉␉break;␊
286␉␉}␊
287␉}␊
288␊
289␉return strdup(asciiPartNo);␊
290}␊
291␊
292int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
293␊
294/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
295static void read_smb_intel(pci_dt_t *smbus_dev)␊
296{␊
297␉int␉␉i, speed;␊
298␉uint8_t␉␉spd_size, spd_type;␊
299␉uint32_t␉base, mmio, hostc;␊
300␉uint16_t␉cmd;␊
301//␉bool␉␉dump = false;␊
302␉RamSlotInfo_t␉*slot;␊
303␊
304␉cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
305␊
306␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
307␊
308␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
309␊
310␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
311␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
312␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
313␊
314␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",␊
315␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
316␊
317␉//Azi: no use for this!␊
318␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
319␉// needed at least for laptops␊
320␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
321␊
322␉char spdbuf[MAX_SPD_SIZE];␊
323␉// Search MAX_RAM_SLOTS slots␊
324␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊
325␉{␊
326␉␉slot = &Platform.RAM.DIMM[i];␊
327␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
328␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
329␉␉// Check spd is present␊
330␉␉if (spd_size && (spd_size != 0xff))␊
331␉␉{␊
332␉␉␉slot->spd = spdbuf;␊
333␉␉␉slot->InUse = true;␊
334␊
335␉␉␉bzero(slot->spd, spd_size);␊
336␊
337␉␉␉// Copy spd data into buffer␊
338␊
339␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
340␉␉␉init_spd(slot->spd, base, i);␊
341␊
342␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
343␉␉␉{␊
344␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
345␊
346␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
347␉␉␉␉␉+ (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
348␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
349␉␉␉␉␉slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
350␉␉␉␉break;␊
351␊
352␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
353␊
354␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
355␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
356␉␉␉␉break;␊
357␊
358␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
359␊
360␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
361␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
362␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
363␊
364␉␉␉␉break;␊
365␊
366␉␉␉␉default:␊
367␉␉␉␉␉slot->ModuleSize = 0;␊
368␉␉␉␉break;␊
369␊
370␉␉␉}␊
371␊
372␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
373␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
374␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE)␊
375␉␉␉{␊
376␉␉␉␉continue;␊
377␉␉␉}␊
378␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
379␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
380␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
381␊
382␉␉␉// determine spd speed␊
383␉␉␉speed = (uint16_t)getDDRspeedMhz(slot->spd);␊
384␉␉␉if (slot->Frequency < speed)␊
385␉␉␉{␊
386␉␉␉␉slot->Frequency = speed;␊
387␉␉␉}␊
388␊
389␉␉␉// pci memory controller if available, is more reliable␊
390␉␉␉if (Platform.RAM.Frequency > 0)␊
391␉␉␉{␊
392␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
393␉␉␉␉// now round off special cases␊
394␉␉␉␉uint32_t fmod100 = freq %100;␊
395␉␉␉␉switch(fmod100)␊
396␉␉␉␉{␊
397␉␉␉␉␉case 1:␉freq--;␉break;␊
398␉␉␉␉␉case 32:␉freq++;␉break;␊
399␉␉␉␉␉case 65:␉freq++; break;␊
400␉␉␉␉␉case 98:␉freq+=2;break;␊
401␉␉␉␉␉case 99:␉freq++; break;␊
402␉␉␉␉}␊
403␉␉␉␉slot->Frequency = freq;␊
404␉␉␉␉DBG("RAM speed %dMHz \n", freq);␊
405␉␉␉}␊
406␊
407␉␉␉verbose("\tSlot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n\t\tPartNo=%s SerialNo=%s\n",␊
408␉␉␉␉i,␊
409␉␉␉␉(int)slot->Type,␊
410␉␉␉␉slot->ModuleSize, ␊
411␉␉␉␉spd_memory_types[spd_type],␊
412␉␉␉␉slot->Frequency,␊
413␉␉␉␉slot->Vendor,␊
414␉␉␉␉slot->PartNo,␊
415␉␉␉␉slot->SerialNo);␊
416␉␉␉slot->InUse = true;␊
417␉␉}␊
418␊
419␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
420␉␉Platform.DMI.DIMM[i]= ␊
421 ␉(uint32_t)((i > 0 && Platform.RAM.DIMM[1].InUse == false && fullBanks && Platform.DMI.CntMemorySlots == 2) ? mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
422␊
423␉␉slot->spd = NULL;␊
424␊
425␉} // for␊
426}␊
427␊
428static struct smbus_controllers_t smbus_controllers[] = {␊
429␊
430␉// Intel␊
431␉{0x8086, 0x1C22, "P67",␉␉␉read_smb_intel },␊
432␉{0x8086, 0x1D22, "X79",␉␉␉read_smb_intel },␊
433␉{0x8086, 0x1D70, "X79",␉␉␉read_smb_intel },␊
434␉{0x8086, 0x1D71, "X79",␉␉␉read_smb_intel },␊
435␉{0x8086, 0x1D72, "C608",␉␉read_smb_intel },␊
436␉{0x8086, 0x1E22, "Z77",␉␉␉read_smb_intel },␊
437␉{0x8086, 0x2330, "DH89xxCC",␉␉read_smb_intel },␊
438␉{0x8086, 0x2413, "82801AA",␉␉read_smb_intel },␊
439␉{0x8086, 0x2423, "BAM",␉␉␉read_smb_intel },␊
440␉{0x8086, 0x2443, "BAM",␉␉␉read_smb_intel },␊
441␉{0x8086, 0x2483, "CAM",␉␉␉read_smb_intel },␊
442␉{0x8086, 0x24C3, "ICH4",␉␉read_smb_intel },␊
443␉{0x8086, 0x24D3, "ICH5",␉␉read_smb_intel },␊
444␉{0x8086, 0x25A4, "6300ESB",␉␉read_smb_intel },␊
445␉{0x8086, 0x266A, "ICH6",␉␉read_smb_intel },␊
446␉{0x8086, 0x269B, "ESB",␉␉␉read_smb_intel },␊
447␉{0x8086, 0x27DA, "ICH7",␉␉read_smb_intel },␊
448␉{0x8086, 0x283E, "ICH8",␉␉read_smb_intel },␊
449␉{0x8086, 0x2930, "ICH9",␉␉read_smb_intel },␊
450␉{0x8086, 0x3A30, "ICH10",␉␉read_smb_intel },␊
451␉{0x8086, 0x3A60, "ICH10",␉␉read_smb_intel },␊
452␉{0x8086, 0x3B30, "P55",␉␉␉read_smb_intel },␊
453␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel },␊
454␉{0x8086, 0x8119, "US15W",␉␉read_smb_intel },␊
455␉{0x8086, 0x8C22, "HSW",␉␉␉read_smb_intel },␊
456␉{0x8086, 0x8CA2, "Z97/H97",␉␉read_smb_intel },␊
457␉{0x8086, 0x8D22, "X99",␉␉␉read_smb_intel },␊
458␉{0x8086, 0x9C22, "HSW-ULT",␉␉read_smb_intel }␊
459␊
460␉// AMD␊
461//␉{0x1002, 0x4385, "AMD SB600/700",␉... },␊
462//␉{0x1022, 0x780B, "AMD SB800/900",␉... }␊
463␊
464};␊
465␊
466// initial call : pci_dt = root_pci_dev;␊
467// find_and_read_smbus_controller(root_pci_dev);␊
468bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
469{␊
470␉pci_dt_t␉*current = pci_dt;␊
471␉int i;␊
472␊
473␉while (current)␊
474␉{␊
475#if 0␊
476␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
477␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
478␉␉current->class_id, current->vendor_id, current->device_id, ␊
479␉␉get_pci_dev_path(current));␊
480#endif␊
481␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
482␉␉{␊
483␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
484␉␉␉{␊
485␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
486␉␉␉␉return true;␊
487␉␉␉}␊
488␉␉}␊
489␉␉find_and_read_smbus_controller(current->children);␊
490␉␉current = current->next;␊
491␉}␊
492␉return false; // not found␊
493}␊
494␊
495void scan_spd(PlatformInfo_t *p)␊
496{␊
497␉find_and_read_smbus_controller(root_pci_dev);␊
498}␊
499␊
500

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