| 1 | /*␊ |
| 2 | *␉HDA injector / Audio Enabler␊ |
| 3 | *␊ |
| 4 | *␉Copyright (C) 2012␉Chameleon Team␊ |
| 5 | *␉Edit by Fabio (ErmaC)␊ |
| 6 | *␉HDA bus scans and codecs enumeration by Zenith432␊ |
| 7 | *␊ |
| 8 | *␉HDA injector is free software: you can redistribute it and/or modify␊ |
| 9 | *␉it under the terms of the GNU General Public License as published by␊ |
| 10 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
| 11 | *␉(at your option) any later version.␊ |
| 12 | *␊ |
| 13 | *␉HDA injector is distributed in the hope that it will be useful,␊ |
| 14 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 15 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 16 | *␉GNU General Public License for more details.␊ |
| 17 | *␊ |
| 18 | *␉Alternatively you can choose to comply with APSL␊ |
| 19 | *␊ |
| 20 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
| 21 | *␉copy of this software and associated documentation files (the "Software"),␊ |
| 22 | *␉to deal in the Software without restriction, including without limitation␊ |
| 23 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
| 24 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
| 25 | *␉Software is furnished to do so, subject to the following conditions:␊ |
| 26 | *␊ |
| 27 | *␉The above copyright notice and this permission notice shall be included in␊ |
| 28 | *␉all copies or substantial portions of the Software.␊ |
| 29 | *␊ |
| 30 | ******************************************************************************␊ |
| 31 | * http://www.leidinger.net/FreeBSD/dox/dev_sound/html/df/d54/hdac_8c_source.html␊ |
| 32 | *␊ |
| 33 | * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>␊ |
| 34 | * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>␊ |
| 35 | * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>␊ |
| 36 | * All rights reserved.␊ |
| 37 | *␊ |
| 38 | * Redistribution and use in source and binary forms, with or without␊ |
| 39 | * modification, are permitted provided that the following conditions␊ |
| 40 | * are met:␊ |
| 41 | * 1. Redistributions of source code must retain the above copyright␊ |
| 42 | * notice, this list of conditions and the following disclaimer.␊ |
| 43 | * 2. Redistributions in binary form must reproduce the above copyright␊ |
| 44 | * notice, this list of conditions and the following disclaimer in the␊ |
| 45 | * documentation and/or other materials provided with the distribution.␊ |
| 46 | *␊ |
| 47 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND␊ |
| 48 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE␊ |
| 49 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE␊ |
| 50 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE␊ |
| 51 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL␊ |
| 52 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS␊ |
| 53 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)␊ |
| 54 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT␊ |
| 55 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY␊ |
| 56 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF␊ |
| 57 | * SUCH DAMAGE.␊ |
| 58 | *␊ |
| 59 | * Intel High Definition Audio (Controller) driver for FreeBSD.␊ |
| 60 | *␊ |
| 61 | ******************************************************************************/␊ |
| 62 | ␊ |
| 63 | #include "boot.h"␊ |
| 64 | #include "bootstruct.h"␊ |
| 65 | #include "cpu.h"␊ |
| 66 | #include "pci.h"␊ |
| 67 | #include "pci_root.h"␊ |
| 68 | #include "platform.h"␊ |
| 69 | #include "device_inject.h"␊ |
| 70 | #include "convert.h"␊ |
| 71 | #include "hda.h"␊ |
| 72 | ␊ |
| 73 | #define STRINGIFY(x) #x␊ |
| 74 | #define TOSTRING(x) STRINGIFY(x)␊ |
| 75 | ␊ |
| 76 | #define HEADER __FILE__ " [" TOSTRING(__LINE__) "]: "␊ |
| 77 | ␊ |
| 78 | #ifndef DEBUG_HDA␊ |
| 79 | ␉#define DEBUG_HDA 0␊ |
| 80 | #endif␊ |
| 81 | ␊ |
| 82 | #if DEBUG_HDA␊ |
| 83 | ␉#define DBG(x...) verbose(x)␊ |
| 84 | #else␊ |
| 85 | ␉#define DBG(x...)␊ |
| 86 | #endif␊ |
| 87 | ␊ |
| 88 | #ifndef DEBUG_CODEC␊ |
| 89 | ␉#define DEBUG_CODEC 0␊ |
| 90 | #endif␊ |
| 91 | ␊ |
| 92 | #if DEBUG_CODEC␊ |
| 93 | ␉#define CDBG(x...) verbose(x)␊ |
| 94 | #else␊ |
| 95 | ␉#define CDBG(x...)␊ |
| 96 | #endif␊ |
| 97 | ␊ |
| 98 | #define UNKNOWN "Unknown "␊ |
| 99 | ␊ |
| 100 | #define hdacc_lock(codec) snd_mtxlock((codec)->lock)␊ |
| 101 | #define hdacc_unlock(codec) snd_mtxunlock((codec)->lock)␊ |
| 102 | #define hdacc_lockassert(codec) snd_mtxassert((codec)->lock)␊ |
| 103 | #define hdacc_lockowned(codec) mtx_owned((codec)->lock)␊ |
| 104 | ␊ |
| 105 | const char *hda_slot_name[]␉␉=␉{ "AAPL,slot-name", "Built In" };␊ |
| 106 | ␊ |
| 107 | uint8_t default_HDEF_layout_id[]␉␉=␉{0x01, 0x00, 0x00, 0x00};␊ |
| 108 | #define HDEF_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) )␊ |
| 109 | uint8_t default_HDAU_layout_id[]␉␉=␉{0x01, 0x00, 0x00, 0x00};␊ |
| 110 | #define HDAU_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) )␊ |
| 111 | static uint8_t connector_type_value[] =␉{0x00, 0x08, 0x00, 0x00};␊ |
| 112 | ␊ |
| 113 | /* Structures */␊ |
| 114 | ␊ |
| 115 | static hda_controller_devices know_hda_controller[] = {␊ |
| 116 | ␉//8086 Intel Corporation␊ |
| 117 | ␉{ HDA_INTEL_OAK,␉"Oaktrail"␉␉/*, 0, 0 */ },␊ |
| 118 | ␉{ HDA_INTEL_BAY,␉"BayTrail"␉␉/*, 0, 0 */ },␊ |
| 119 | ␉{ HDA_INTEL_HSW1,␉"Haswell"␉␉/*, 0, 0 */ },␊ |
| 120 | ␉{ HDA_INTEL_HSW2,␉"Haswell"␉␉/*, 0, 0 */ },␊ |
| 121 | ␉{ HDA_INTEL_HSW3,␉"Haswell"␉␉/*, 0, 0 */ },␊ |
| 122 | ␉{ HDA_INTEL_BDW,␉"Broadwell"␉␉/*, 0, 0 */ },␊ |
| 123 | ␉{ HDA_INTEL_CPT,␉"Cougar Point"␉␉/*, 0, 0 */ },␊ |
| 124 | ␉{ HDA_INTEL_PATSBURG,␉"Patsburg"␉␉/*, 0, 0 */ },␊ |
| 125 | ␉{ HDA_INTEL_PPT1,␉"Panther Point"␉␉/*, 0, 0 */ },␊ |
| 126 | ␉{ HDA_INTEL_BRASWELL,␉"Braswell"␉␉/*, 0, 0 */ },␊ |
| 127 | ␉{ HDA_INTEL_82801F,␉"82801F"␉␉/*, 0, 0 */ },␊ |
| 128 | ␉{ HDA_INTEL_63XXESB,␉"631x/632xESB"␉␉/*, 0, 0 */ },␊ |
| 129 | ␉{ HDA_INTEL_82801G,␉"82801G"␉␉/*, 0, 0 */ },␊ |
| 130 | ␉{ HDA_INTEL_82801H,␉"82801H"␉␉/*, 0, 0 */ },␊ |
| 131 | ␉{ HDA_INTEL_82801I,␉"82801I"␉␉/*, 0, 0 */ },␊ |
| 132 | ␉{ HDA_INTEL_ICH9,␉"ICH9"␉␉␉/*, 0, 0 */ },␊ |
| 133 | ␉{ HDA_INTEL_82801JI,␉"82801JI"␉␉/*, 0, 0 */ },␊ |
| 134 | ␉{ HDA_INTEL_82801JD,␉"82801JD"␉␉/*, 0, 0 */ },␊ |
| 135 | ␉{ HDA_INTEL_PCH,␉"5 Series/3400 Series"␉/*, 0, 0 */ },␊ |
| 136 | ␉{ HDA_INTEL_PCH2,␉"5 Series/3400 Series"␉/*, 0, 0 */ },␊ |
| 137 | ␉{ HDA_INTEL_SCH,␉"SCH"␉␉␉/*, 0, 0 */ },␊ |
| 138 | ␉{ HDA_INTEL_LPT1,␉"Lynx Point"␉␉/*, 0, 0 */ },␊ |
| 139 | ␉{ HDA_INTEL_LPT2,␉"Lynx Point"␉␉/*, 0, 0 */ },␊ |
| 140 | ␉{ HDA_INTEL_WCPT,␉"Wildcat Point"␉␉/*, 0, 0 */ },␊ |
| 141 | ␉{ HDA_INTEL_WELLS1,␉"Wellsburg"␉␉/*, 0, 0 */ },␊ |
| 142 | ␉{ HDA_INTEL_WELLS2,␉"Wellsburg"␉␉/*, 0, 0 */ },␊ |
| 143 | ␉{ HDA_INTEL_WCPTLP,␉"Wildcat Point-LP"␉/*, 0, 0 */ },␊ |
| 144 | ␉{ HDA_INTEL_LPTLP1,␉"Lynx Point-LP"␉␉/*, 0, 0 */ },␊ |
| 145 | ␉{ HDA_INTEL_LPTLP2,␉"Lynx Point-LP"␉␉/*, 0, 0 */ },␊ |
| 146 | ␉{ HDA_INTEL_SRSPLP,␉"Sunrise Point-LP"␉/*, 0, 0 */ },␊ |
| 147 | ␉{ HDA_INTEL_SRSP,␉"Sunrise Point"␉␉/*, 0, 0 */ },␊ |
| 148 | ␊ |
| 149 | ␉//10de NVIDIA Corporation␊ |
| 150 | ␉{ HDA_NVIDIA_MCP51,␉"MCP51" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 151 | ␉{ HDA_NVIDIA_MCP55,␉"MCP55" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 152 | ␉{ HDA_NVIDIA_MCP61_1,␉"MCP61" /*, 0, 0 */ },␊ |
| 153 | ␉{ HDA_NVIDIA_MCP61_2,␉"MCP61" /*, 0, 0 */ },␊ |
| 154 | ␉{ HDA_NVIDIA_MCP65_1,␉"MCP65" /*, 0, 0 */ },␊ |
| 155 | ␉{ HDA_NVIDIA_MCP65_2,␉"MCP65" /*, 0, 0 */ },␊ |
| 156 | ␉{ HDA_NVIDIA_MCP67_1,␉"MCP67" /*, 0, 0 */ },␊ |
| 157 | ␉{ HDA_NVIDIA_MCP67_2,␉"MCP67" /*, 0, 0 */ },␊ |
| 158 | ␉{ HDA_NVIDIA_MCP73_1,␉"MCP73" /*, 0, 0 */ },␊ |
| 159 | ␉{ HDA_NVIDIA_MCP73_2,␉"MCP73" /*, 0, 0 */ },␊ |
| 160 | ␉{ HDA_NVIDIA_MCP78_1,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
| 161 | ␉{ HDA_NVIDIA_MCP78_2,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
| 162 | ␉{ HDA_NVIDIA_MCP78_3,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
| 163 | ␉{ HDA_NVIDIA_MCP78_4,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
| 164 | ␉{ HDA_NVIDIA_MCP79_1,␉"MCP79" /*, 0, 0 */ },␊ |
| 165 | ␉{ HDA_NVIDIA_MCP79_2,␉"MCP79" /*, 0, 0 */ },␊ |
| 166 | ␉{ HDA_NVIDIA_MCP79_3,␉"MCP79" /*, 0, 0 */ },␊ |
| 167 | ␉{ HDA_NVIDIA_MCP79_4,␉"MCP79" /*, 0, 0 */ },␊ |
| 168 | ␉{ HDA_NVIDIA_MCP89_1,␉"MCP89" /*, 0, 0 */ },␊ |
| 169 | ␉{ HDA_NVIDIA_MCP89_2,␉"MCP89" /*, 0, 0 */ },␊ |
| 170 | ␉{ HDA_NVIDIA_MCP89_3,␉"MCP89" /*, 0, 0 */ },␊ |
| 171 | ␉{ HDA_NVIDIA_MCP89_4,␉"MCP89" /*, 0, 0 */ },␊ |
| 172 | ␉{ HDA_NVIDIA_0BE2,␉"(0x0be2)" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 173 | ␉{ HDA_NVIDIA_0BE3,␉"(0x0be3)" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 174 | ␉{ HDA_NVIDIA_0BE4,␉"(0x0be4)" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 175 | ␉{ HDA_NVIDIA_GT100,␉"GT100" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 176 | ␉{ HDA_NVIDIA_GT104,␉"GT104" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 177 | ␉{ HDA_NVIDIA_GT106,␉"GT106" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 178 | ␉{ HDA_NVIDIA_GT108,␉"GT108" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 179 | ␉{ HDA_NVIDIA_GT116,␉"GT116" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 180 | ␉{ HDA_NVIDIA_GF119,␉"GF119" /*, 0, 0 */ },␊ |
| 181 | ␉{ HDA_NVIDIA_GF110_1,␉"GF110" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 182 | ␉{ HDA_NVIDIA_GF110_2,␉"GF110" /*, 0, HDAC_QUIRK_MSI */ },␊ |
| 183 | ␉{ HDA_NVIDIA_GK110,␉"GK110" /*, 0, ? */ },␊ |
| 184 | ␉{ HDA_NVIDIA_GK106,␉"GK106" /*, 0, ? */ },␊ |
| 185 | ␉{ HDA_NVIDIA_GK107,␉"GK107" /*, 0, ? */ },␊ |
| 186 | ␉{ HDA_NVIDIA_GK104,␉"GK104" /*, 0, ? */ },␊ |
| 187 | ␊ |
| 188 | ␉//1002 Advanced Micro Devices [AMD] nee ATI Technologies Inc␊ |
| 189 | ␉{ HDA_ATI_SB450,␉"SB4x0" /*, 0, 0 */ },␊ |
| 190 | ␉{ HDA_ATI_SB600,␉"SB600" /*, 0, 0 */ },␊ |
| 191 | ␉{ HDA_ATI_RS600,␉"RS600" /*, 0, 0 */ },␊ |
| 192 | ␉{ HDA_ATI_HUDSON,␉"Hudson" /*, 0, 0 */ },␊ |
| 193 | ␉{ HDA_ATI_RS690,␉"RS690" /*, 0, 0 */ },␊ |
| 194 | ␉{ HDA_ATI_RS780,␉"RS780" /*, 0, 0 */ },␊ |
| 195 | ␉{ HDA_ATI_RS880,␉"RS880" /*, 0, 0 */ },␊ |
| 196 | ␉{ HDA_ATI_TRINITY,␉"Trinity" /*, 0, ? */ },␊ |
| 197 | ␉{ HDA_ATI_R600,␉␉"R600" /*, 0, 0 */ },␊ |
| 198 | ␉{ HDA_ATI_RV610,␉"RV610" /*, 0, 0 */ },␊ |
| 199 | ␉{ HDA_ATI_RV620,␉"RV620" /*, 0, 0 */ },␊ |
| 200 | ␉{ HDA_ATI_RV630,␉"RV630" /*, 0, 0 */ },␊ |
| 201 | ␉{ HDA_ATI_RV635,␉"RV635" /*, 0, 0 */ },␊ |
| 202 | ␉{ HDA_ATI_RV710,␉"RV710" /*, 0, 0 */ },␊ |
| 203 | ␉{ HDA_ATI_RV730,␉"RV730" /*, 0, 0 */ },␊ |
| 204 | ␉{ HDA_ATI_RV740,␉"RV740" /*, 0, 0 */ },␊ |
| 205 | ␉{ HDA_ATI_RV770,␉"RV770" /*, 0, 0 */ },␊ |
| 206 | ␉{ HDA_ATI_RV810,␉"RV810" /*, 0, 0 */ },␊ |
| 207 | ␉{ HDA_ATI_RV830,␉"RV830" /*, 0, 0 */ },␊ |
| 208 | ␉{ HDA_ATI_RV840,␉"RV840" /*, 0, 0 */ },␊ |
| 209 | ␉{ HDA_ATI_RV870,␉"RV870" /*, 0, 0 */ },␊ |
| 210 | ␉{ HDA_ATI_RV910,␉"RV910" /*, 0, 0 */ },␊ |
| 211 | ␉{ HDA_ATI_RV930,␉"RV930" /*, 0, 0 */ },␊ |
| 212 | ␉{ HDA_ATI_RV940,␉"RV940" /*, 0, 0 */ },␊ |
| 213 | ␉{ HDA_ATI_RV970,␉"RV970" /*, 0, 0 */ },␊ |
| 214 | ␉{ HDA_ATI_R1000,␉"R1000" /*, 0, 0 */ }, // HDMi␊ |
| 215 | ␉{ HDA_ATI_SI,␉␉"SI" /*, 0, 0 */ },␊ |
| 216 | ␉{ HDA_ATI_VERDE,␉"Cape Verde" /*, 0, ? */ }, // HDMi␊ |
| 217 | ␊ |
| 218 | ␉//17f3 RDC Semiconductor, Inc.␊ |
| 219 | ␉{ HDA_RDC_M3010,␉"M3010" /*, 0, 0 */ },␊ |
| 220 | ␊ |
| 221 | ␉//1106 VIA Technologies, Inc.␊ |
| 222 | ␉{ HDA_VIA_VT82XX,␉"VT8251/8237A" /*, 0, 0 */ },␊ |
| 223 | ␊ |
| 224 | ␉//1039 Silicon Integrated Systems [SiS]␊ |
| 225 | ␉{ HDA_SIS_966,␉␉"966" /*, 0, 0 */ },␊ |
| 226 | ␊ |
| 227 | ␉//10b9 ULi Electronics Inc.(Split off ALi Corporation in 2003)␊ |
| 228 | ␉{ HDA_ULI_M5461,␉"M5461" /*, 0, 0 */ },␊ |
| 229 | ␊ |
| 230 | ␉/* Unknown */␊ |
| 231 | ␉{ HDA_INTEL_ALL,␉"Unknown Intel device" /*, 0, 0 */ },␊ |
| 232 | ␉{ HDA_NVIDIA_ALL,␉"Unknown NVIDIA device" /*, 0, 0 */ },␊ |
| 233 | ␉{ HDA_ATI_ALL,␉␉"Unknown ATI device" /*, 0, 0 */ },␊ |
| 234 | ␉{ HDA_VIA_ALL,␉␉"Unknown VIA device" /*, 0, 0 */ },␊ |
| 235 | ␉{ HDA_SIS_ALL,␉␉"Unknown SiS device" /*, 0, 0 */ },␊ |
| 236 | ␉{ HDA_ULI_ALL,␉␉"Unknown ULI device" /*, 0, 0 */ },␊ |
| 237 | };␊ |
| 238 | #define HDAC_DEVICES_LEN (sizeof(know_hda_controller) / sizeof(know_hda_controller[0]))␊ |
| 239 | ␊ |
| 240 | /* CODECs */␊ |
| 241 | /*␊ |
| 242 | * ErmaC: There's definitely a lot of different versions of the same audio codec variant out there...␊ |
| 243 | * in the next struct you will find a "generic" but IMHO detailed list of␊ |
| 244 | * possible codec... anyway to specific a new one or find difference beetween revision␊ |
| 245 | * check it under linux enviroment with:␊ |
| 246 | * $cat /proc/asound/Intel/codec#0␊ |
| 247 | * --------------------------------␊ |
| 248 | * Codec: Analog Devices AD1989B␊ |
| 249 | * Address: 0␊ |
| 250 | * AFG Function Id: 0x1 (unsol 0)␊ |
| 251 | * Vendor Id: 0x11d4989b␊ |
| 252 | * Subsystem Id: 0x10438372␊ |
| 253 | * Revision Id: 0x100300␊ |
| 254 | * --------------------------------␊ |
| 255 | * or␊ |
| 256 | * $cat /proc/asound/NVidia/codec#0␊ |
| 257 | * --------------------------------␊ |
| 258 | * Codec: Nvidia GPU 14 HDMI/DP␊ |
| 259 | * Address: 0␊ |
| 260 | * AFG Function Id: 0x1 (unsol 0)␊ |
| 261 | * Vendor Id: 0x10de0014␊ |
| 262 | * Subsystem Id: 0x10de0101␊ |
| 263 | * Revision Id: 0x100100␊ |
| 264 | * --------------------------------␊ |
| 265 | */␊ |
| 266 | ␊ |
| 267 | static hdacc_codecs know_codecs[] = {␊ |
| 268 | ␉{ HDA_CODEC_CS4206, 0,␉␉"CS4206" },␊ |
| 269 | ␉{ HDA_CODEC_CS4207, 0,␉␉"CS4207" },␊ |
| 270 | ␉{ HDA_CODEC_CS4208, 0,␉␉"CS4208" },␊ |
| 271 | ␉{ HDA_CODEC_CS4210, 0,␉␉"CS4210" },␊ |
| 272 | ␉{ HDA_CODEC_CS4213, 0, "CS4213" },␊ |
| 273 | ␊ |
| 274 | ␉{ HDA_CODEC_ALC221, 0, "ALC221" },␊ |
| 275 | ␉{ HDA_CODEC_ALC231, 0, "ALC231" },␊ |
| 276 | ␉{ HDA_CODEC_ALC233, 0, "ALC233" },␊ |
| 277 | ␉{ HDA_CODEC_ALC235, 0, "ALC235" },␊ |
| 278 | ␉{ HDA_CODEC_ALC255, 0, "ALC255" },␊ |
| 279 | ␉{ HDA_CODEC_ALC256, 0, "ALC256" },␊ |
| 280 | ␉{ HDA_CODEC_ALC260, 0, "ALC260" },␊ |
| 281 | //␉{ HDA_CODEC_ALC262, 0x0100,␉"ALC262" }, // Revision Id: 0x100100␊ |
| 282 | ␉{ HDA_CODEC_ALC262, 0, "ALC262" },␊ |
| 283 | ␉{ HDA_CODEC_ALC267, 0, "ALC267" },␊ |
| 284 | ␉{ HDA_CODEC_ALC268, 0, "ALC268" },␊ |
| 285 | ␉{ HDA_CODEC_ALC269, 0, "ALC269" },␊ |
| 286 | ␉{ HDA_CODEC_ALC270, 0, "ALC270" },␊ |
| 287 | ␉{ HDA_CODEC_ALC272, 0, "ALC272" },␊ |
| 288 | ␉{ HDA_CODEC_ALC273, 0, "ALC273" },␊ |
| 289 | ␉{ HDA_CODEC_ALC275, 0, "ALC275" },␊ |
| 290 | ␉{ HDA_CODEC_ALC276, 0, "ALC276" },␊ |
| 291 | ␉{ HDA_CODEC_ALC280, 0, "ALC280" },␊ |
| 292 | ␉{ HDA_CODEC_ALC282, 0, "ALC282" },␊ |
| 293 | ␉{ HDA_CODEC_ALC283, 0, "ALC283" },␊ |
| 294 | ␉{ HDA_CODEC_ALC284, 0, "ALC284" },␊ |
| 295 | ␉{ HDA_CODEC_ALC285, 0, "ALC285" },␊ |
| 296 | ␉{ HDA_CODEC_ALC286, 0, "ALC286" },␊ |
| 297 | ␉{ HDA_CODEC_ALC288, 0, "ALC288" },␊ |
| 298 | ␉{ HDA_CODEC_ALC290, 0, "ALC290" },␊ |
| 299 | ␉{ HDA_CODEC_ALC292, 0, "ALC292" },␊ |
| 300 | ␉{ HDA_CODEC_ALC293, 0, "ALC293" },␊ |
| 301 | ␉{ HDA_CODEC_ALC298, 0, "ALC298" },␊ |
| 302 | ␉{ HDA_CODEC_ALC660, 0, "ALC660-VD" },␊ |
| 303 | ␉{ HDA_CODEC_ALC662, 0, "ALC662" },␊ |
| 304 | ␉{ HDA_CODEC_ALC662, 0x0101,␉"ALC662 rev1" },␊ |
| 305 | ␉{ HDA_CODEC_ALC662, 0x0002,␉"ALC662 rev2" },␊ |
| 306 | ␉{ HDA_CODEC_ALC662, 0x0300,␉"ALC662 rev3" },␊ |
| 307 | ␉{ HDA_CODEC_ALC663, 0, "ALC663" },␊ |
| 308 | ␉{ HDA_CODEC_ALC665, 0, "ALC665" },␊ |
| 309 | ␉{ HDA_CODEC_ALC667, 0, "ALC667" },␊ |
| 310 | ␉{ HDA_CODEC_ALC668, 0, "ALC668" },␊ |
| 311 | ␉{ HDA_CODEC_ALC670, 0, "ALC670" },␊ |
| 312 | ␉{ HDA_CODEC_ALC671, 0, "ALC671" },␊ |
| 313 | ␉{ HDA_CODEC_ALC680, 0, "ALC680" },␊ |
| 314 | ␉{ HDA_CODEC_ALC861, 0x0340,␉"ALC660" },␊ |
| 315 | ␉{ HDA_CODEC_ALC861, 0, "ALC861" },␊ |
| 316 | ␉{ HDA_CODEC_ALC861VD, 0, "ALC861-VD" },␊ |
| 317 | ␉{ HDA_CODEC_ALC867, 0, "ALC891" },␊ |
| 318 | //␉{ HDA_CODEC_ALC880, 0x0800,␉"ALC880" }, // Revision Id: 0x100800␊ |
| 319 | ␉{ HDA_CODEC_ALC880, 0, "ALC880" },␊ |
| 320 | ␉{ HDA_CODEC_ALC882, 0, "ALC882" },␊ |
| 321 | ␉{ HDA_CODEC_ALC883, 0, "ALC883" },␊ |
| 322 | ␉{ HDA_CODEC_ALC885, 0x0101,␉"ALC889A" }, // Revision Id: 0x100101␊ |
| 323 | ␉{ HDA_CODEC_ALC885, 0x0103,␉"ALC889A" }, // Revision Id: 0x100103␊ |
| 324 | ␉{ HDA_CODEC_ALC885, 0, "ALC885" },␊ |
| 325 | ␉{ HDA_CODEC_ALC886, 0, "ALC886" },␊ |
| 326 | ␉{ HDA_CODEC_ALC887, 0, "ALC887" },␊ |
| 327 | ␉{ HDA_CODEC_ALC888, 0x0101,␉"ALC1200" }, // Revision Id: 0x100101␊ |
| 328 | ␉{ HDA_CODEC_ALC888, 0, "ALC888" },␊ |
| 329 | ␉{ HDA_CODEC_ALC889, 0, "ALC889" },␊ |
| 330 | ␉{ HDA_CODEC_ALC892, 0, "ALC892" },␊ |
| 331 | ␉{ HDA_CODEC_ALC898, 0, "ALC898" },␊ |
| 332 | ␉{ HDA_CODEC_ALC899, 0,␉␉"ALC899" },␊ |
| 333 | ␉{ HDA_CODEC_ALC900, 0, "ALC1150" },␊ |
| 334 | ␊ |
| 335 | ␉{ HDA_CODEC_AD1882, 0, "AD1882" },␊ |
| 336 | ␉{ HDA_CODEC_AD1882A, 0, "AD1882A" },␊ |
| 337 | ␉{ HDA_CODEC_AD1883, 0, "AD1883" },␊ |
| 338 | ␉{ HDA_CODEC_AD1884, 0, "AD1884" },␊ |
| 339 | ␉{ HDA_CODEC_AD1884A, 0, "AD1884A" },␊ |
| 340 | ␉{ HDA_CODEC_AD1981HD, 0, "AD1981HD" },␊ |
| 341 | ␉{ HDA_CODEC_AD1983, 0, "AD1983" },␊ |
| 342 | ␉{ HDA_CODEC_AD1984, 0, "AD1984" },␊ |
| 343 | ␉{ HDA_CODEC_AD1984A, 0, "AD1984A" },␊ |
| 344 | ␉{ HDA_CODEC_AD1984B, 0, "AD1984B" },␊ |
| 345 | ␉{ HDA_CODEC_AD1986A, 0, "AD1986A" },␊ |
| 346 | ␉{ HDA_CODEC_AD1987, 0, "AD1987" },␊ |
| 347 | ␉{ HDA_CODEC_AD1988, 0, "AD1988A" },␊ |
| 348 | ␉{ HDA_CODEC_AD1988B, 0, "AD1988B" },␊ |
| 349 | ␉{ HDA_CODEC_AD1989A, 0, "AD1989A" },␊ |
| 350 | ␉{ HDA_CODEC_AD1989B, 0x0200,␉"AD2000B" }, // Revision Id: 0x100200␊ |
| 351 | ␉{ HDA_CODEC_AD1989B, 0x0300,␉"AD2000B" }, // Revision Id: 0x100300␊ |
| 352 | ␉{ HDA_CODEC_AD1989B, 0, "AD1989B" },␊ |
| 353 | ␊ |
| 354 | ␉{ HDA_CODEC_XFIEA, 0, "Creative X-Fi Extreme A" },␊ |
| 355 | ␉{ HDA_CODEC_XFIED, 0, "Creative X-Fi Extreme D" },␊ |
| 356 | ␉{ HDA_CODEC_CA0132, 0, "Creative CA0132" },␊ |
| 357 | ␉{ HDA_CODEC_SB0880, 0, "Creative SB0880 X-Fi" },␊ |
| 358 | ␉{ HDA_CODEC_CMI9880, 0, "CMedia CMI9880" },␊ |
| 359 | ␉{ HDA_CODEC_CMI98802, 0, "CMedia CMI9880" },␊ |
| 360 | ␊ |
| 361 | ␉{ HDA_CODEC_CXD9872RDK, 0, "CXD9872RD/K" },␊ |
| 362 | ␉{ HDA_CODEC_CXD9872AKD, 0, "CXD9872AKD" },␊ |
| 363 | ␉{ HDA_CODEC_STAC9200D, 0, "STAC9200D" },␊ |
| 364 | ␉{ HDA_CODEC_STAC9204X, 0, "STAC9204X" },␊ |
| 365 | ␉{ HDA_CODEC_STAC9204D, 0, "STAC9204D" },␊ |
| 366 | ␉{ HDA_CODEC_STAC9205X, 0, "STAC9205X" },␊ |
| 367 | ␉{ HDA_CODEC_STAC9205D, 0, "STAC9205D" },␊ |
| 368 | ␉{ HDA_CODEC_STAC9220, 0, "STAC9220" },␊ |
| 369 | ␉{ HDA_CODEC_STAC9220_A1, 0, "STAC9220_A1" },␊ |
| 370 | ␉{ HDA_CODEC_STAC9220_A2, 0, "STAC9220_A2" },␊ |
| 371 | ␉{ HDA_CODEC_STAC9221, 0, "STAC9221" },␊ |
| 372 | ␉{ HDA_CODEC_STAC9221_A2, 0, "STAC9221_A2" },␊ |
| 373 | ␉{ HDA_CODEC_STAC9221D, 0, "STAC9221D" },␊ |
| 374 | ␉{ HDA_CODEC_STAC922XD, 0, "STAC9220D/9223D" },␊ |
| 375 | ␉{ HDA_CODEC_STAC9227X, 0, "STAC9227X" },␊ |
| 376 | ␉{ HDA_CODEC_STAC9227D, 0, "STAC9227D" },␊ |
| 377 | ␉{ HDA_CODEC_STAC9228X, 0, "STAC9228X" },␊ |
| 378 | ␉{ HDA_CODEC_STAC9228D, 0, "STAC9228D" },␊ |
| 379 | ␉{ HDA_CODEC_STAC9229X, 0, "STAC9229X" },␊ |
| 380 | ␉{ HDA_CODEC_STAC9229D, 0, "STAC9229D" },␊ |
| 381 | ␉{ HDA_CODEC_STAC9230X, 0, "STAC9230X" },␊ |
| 382 | ␉{ HDA_CODEC_STAC9230D, 0, "STAC9230D" },␊ |
| 383 | ␉{ HDA_CODEC_STAC9250, 0, "STAC9250" },␊ |
| 384 | ␉{ HDA_CODEC_STAC9250D, 0,␉"STAC9250D" },␊ |
| 385 | ␉{ HDA_CODEC_STAC9251, 0, "STAC9251" },␊ |
| 386 | ␉{ HDA_CODEC_STAC9250D_1, 0,␉"STAC9250D" },␊ |
| 387 | ␉{ HDA_CODEC_STAC9255, 0, "STAC9255" },␊ |
| 388 | ␉{ HDA_CODEC_STAC9255D, 0, "STAC9255D" },␊ |
| 389 | ␉{ HDA_CODEC_STAC9254, 0, "STAC9254" },␊ |
| 390 | ␉{ HDA_CODEC_STAC9254D, 0, "STAC9254D" },␊ |
| 391 | ␉{ HDA_CODEC_STAC9271X, 0, "STAC9271X" },␊ |
| 392 | ␉{ HDA_CODEC_STAC9271D, 0, "STAC9271D" },␊ |
| 393 | ␉{ HDA_CODEC_STAC9272X, 0, "STAC9272X" },␊ |
| 394 | ␉{ HDA_CODEC_STAC9272D, 0, "STAC9272D" },␊ |
| 395 | ␉{ HDA_CODEC_STAC9273X, 0, "STAC9273X" },␊ |
| 396 | ␉{ HDA_CODEC_STAC9273D, 0, "STAC9273D" },␊ |
| 397 | ␉{ HDA_CODEC_STAC9274, 0, "STAC9274" },␊ |
| 398 | ␉{ HDA_CODEC_STAC9274D, 0, "STAC9274D" },␊ |
| 399 | ␉{ HDA_CODEC_STAC9274X5NH, 0, "STAC9274X5NH" },␊ |
| 400 | ␉{ HDA_CODEC_STAC9274D5NH, 0, "STAC9274D5NH" },␊ |
| 401 | ␉{ HDA_CODEC_STAC9202, 0,␉"STAC9202" },␊ |
| 402 | ␉{ HDA_CODEC_STAC9202D, 0,␉"STAC9202D" },␊ |
| 403 | ␉{ HDA_CODEC_STAC9872AK, 0, "STAC9872AK" },␊ |
| 404 | ␊ |
| 405 | ␉{ HDA_CODEC_IDT92HD005, 0, "92HD005" },␊ |
| 406 | ␉{ HDA_CODEC_IDT92HD005D, 0, "92HD005D" },␊ |
| 407 | ␉{ HDA_CODEC_IDT92HD206X, 0, "92HD206X" },␊ |
| 408 | ␉{ HDA_CODEC_IDT92HD206D, 0, "92HD206D" },␊ |
| 409 | ␉{ HDA_CODEC_IDT92HD66B1X5, 0, "92HD66B1X5" },␊ |
| 410 | ␉{ HDA_CODEC_IDT92HD66B2X5, 0, "92HD66B2X5" },␊ |
| 411 | ␉{ HDA_CODEC_IDT92HD66B3X5, 0, "92HD66B3X5" },␊ |
| 412 | ␉{ HDA_CODEC_IDT92HD66C1X5, 0, "92HD66C1X5" },␊ |
| 413 | ␉{ HDA_CODEC_IDT92HD66C2X5, 0, "92HD66C2X5" },␊ |
| 414 | ␉{ HDA_CODEC_IDT92HD66C3X5, 0, "92HD66C3X5" },␊ |
| 415 | ␉{ HDA_CODEC_IDT92HD66B1X3, 0, "92HD66B1X3" },␊ |
| 416 | ␉{ HDA_CODEC_IDT92HD66B2X3, 0, "92HD66B2X3" },␊ |
| 417 | ␉{ HDA_CODEC_IDT92HD66B3X3, 0, "92HD66B3X3" },␊ |
| 418 | ␉{ HDA_CODEC_IDT92HD66C1X3, 0, "92HD66C1X3" },␊ |
| 419 | ␉{ HDA_CODEC_IDT92HD66C2X3, 0, "92HD66C2X3" },␊ |
| 420 | ␉{ HDA_CODEC_IDT92HD66C3_65, 0, "92HD66C3_65" },␊ |
| 421 | ␉{ HDA_CODEC_IDT92HD700X, 0, "92HD700X" },␊ |
| 422 | ␉{ HDA_CODEC_IDT92HD700D, 0, "92HD700D" },␊ |
| 423 | ␉{ HDA_CODEC_IDT92HD71B5, 0, "92HD71B5" },␊ |
| 424 | ␉{ HDA_CODEC_IDT92HD71B5_2, 0, "92HD71B5" },␊ |
| 425 | ␉{ HDA_CODEC_IDT92HD71B6, 0, "92HD71B6" },␊ |
| 426 | ␉{ HDA_CODEC_IDT92HD71B6_2, 0, "92HD71B6" },␊ |
| 427 | ␉{ HDA_CODEC_IDT92HD71B7, 0, "92HD71B7" },␊ |
| 428 | ␉{ HDA_CODEC_IDT92HD71B7_2, 0, "92HD71B7" },␊ |
| 429 | ␉{ HDA_CODEC_IDT92HD71B8, 0, "92HD71B8" },␊ |
| 430 | ␉{ HDA_CODEC_IDT92HD71B8_2, 0, "92HD71B8" },␊ |
| 431 | ␉{ HDA_CODEC_IDT92HD73C1, 0, "92HD73C1" },␊ |
| 432 | ␉{ HDA_CODEC_IDT92HD73D1, 0, "92HD73D1" },␊ |
| 433 | ␉{ HDA_CODEC_IDT92HD73E1, 0, "92HD73E1" },␊ |
| 434 | ␉{ HDA_CODEC_IDT92HD95, 0,␉"92HD95" },␊ |
| 435 | ␉{ HDA_CODEC_IDT92HD75B3, 0, "92HD75B3" },␊ |
| 436 | ␉{ HDA_CODEC_IDT92HD88B3, 0, "92HD88B3" },␊ |
| 437 | ␉{ HDA_CODEC_IDT92HD88B1, 0, "92HD88B1" },␊ |
| 438 | ␉{ HDA_CODEC_IDT92HD88B2, 0, "92HD88B2" },␊ |
| 439 | ␉{ HDA_CODEC_IDT92HD88B4, 0, "92HD88B4" },␊ |
| 440 | ␉{ HDA_CODEC_IDT92HD75BX, 0, "92HD75BX" },␊ |
| 441 | ␉{ HDA_CODEC_IDT92HD81B1C, 0, "92HD81B1C" },␊ |
| 442 | ␉{ HDA_CODEC_IDT92HD81B1X, 0, "92HD81B1X" },␊ |
| 443 | ␉{ HDA_CODEC_IDT92HD83C1C, 0, "92HD83C1C" },␊ |
| 444 | ␉{ HDA_CODEC_IDT92HD83C1X, 0, "92HD83C1X" },␊ |
| 445 | ␉{ HDA_CODEC_IDT92HD87B1_3, 0, "92HD87B1/3" },␊ |
| 446 | ␉{ HDA_CODEC_IDT92HD87B2_4, 0, "92HD87B2/4" },␊ |
| 447 | ␉{ HDA_CODEC_IDT92HD89C3, 0, "92HD89C3" },␊ |
| 448 | ␉{ HDA_CODEC_IDT92HD89C2, 0, "92HD89C2" },␊ |
| 449 | ␉{ HDA_CODEC_IDT92HD89C1, 0, "92HD89C1" },␊ |
| 450 | ␉{ HDA_CODEC_IDT92HD89B3, 0, "92HD89B3" },␊ |
| 451 | ␉{ HDA_CODEC_IDT92HD89B2, 0, "92HD89B2" },␊ |
| 452 | ␉{ HDA_CODEC_IDT92HD89B1, 0, "92HD89B1" },␊ |
| 453 | ␉{ HDA_CODEC_IDT92HD89E3, 0, "92HD89E3" },␊ |
| 454 | ␉{ HDA_CODEC_IDT92HD89E2, 0, "92HD89E2" },␊ |
| 455 | ␉{ HDA_CODEC_IDT92HD89E1, 0, "92HD89E1" },␊ |
| 456 | ␉{ HDA_CODEC_IDT92HD89D3, 0, "92HD89D3" },␊ |
| 457 | ␉{ HDA_CODEC_IDT92HD89D2, 0, "92HD89D2" },␊ |
| 458 | ␉{ HDA_CODEC_IDT92HD89D1, 0, "92HD89D1" },␊ |
| 459 | ␉{ HDA_CODEC_IDT92HD89F3, 0, "92HD89F3" },␊ |
| 460 | ␉{ HDA_CODEC_IDT92HD89F2, 0, "92HD89F2" },␊ |
| 461 | ␉{ HDA_CODEC_IDT92HD89F1, 0, "92HD89F1" },␊ |
| 462 | ␉{ HDA_CODEC_IDT92HD90BXX, 0, "92HD90BXX" },␊ |
| 463 | ␉{ HDA_CODEC_IDT92HD91BXX, 0, "92HD91BXX" },␊ |
| 464 | ␉{ HDA_CODEC_IDT92HD93BXX, 0, "92HD93BXX" },␊ |
| 465 | ␉{ HDA_CODEC_IDT92HD98BXX, 0, "92HD98BXX" },␊ |
| 466 | ␉{ HDA_CODEC_IDT92HD99BXX, 0, "92HD99BXX" },␊ |
| 467 | ␊ |
| 468 | ␉{ HDA_CODEC_CX20549, 0, "CX20549 (Venice)" },␊ |
| 469 | ␉{ HDA_CODEC_CX20551, 0, "CX20551 (Waikiki)" },␊ |
| 470 | ␉{ HDA_CODEC_CX20561, 0, "CX20561 (Hermosa)" },␊ |
| 471 | ␉{ HDA_CODEC_CX20582, 0, "CX20582 (Pebble)" },␊ |
| 472 | ␉{ HDA_CODEC_CX20583, 0, "CX20583 (Pebble HSF)" },␊ |
| 473 | ␉{ HDA_CODEC_CX20584, 0, "CX20584" },␊ |
| 474 | ␉{ HDA_CODEC_CX20585, 0, "CX20585" },␊ |
| 475 | ␉{ HDA_CODEC_CX20588, 0, "CX20588" },␊ |
| 476 | ␉{ HDA_CODEC_CX20590, 0, "CX20590" },␊ |
| 477 | ␉{ HDA_CODEC_CX20631, 0, "CX20631" },␊ |
| 478 | ␉{ HDA_CODEC_CX20632, 0, "CX20632" },␊ |
| 479 | ␉{ HDA_CODEC_CX20641, 0, "CX20641" },␊ |
| 480 | ␉{ HDA_CODEC_CX20642, 0, "CX20642" },␊ |
| 481 | ␉{ HDA_CODEC_CX20651, 0, "CX20651" },␊ |
| 482 | ␉{ HDA_CODEC_CX20652, 0, "CX20652" },␊ |
| 483 | ␉{ HDA_CODEC_CX20664, 0, "CX20664" },␊ |
| 484 | ␉{ HDA_CODEC_CX20665, 0, "CX20665" },␊ |
| 485 | ␉{ HDA_CODEC_CX20751, 0,␉␉"CX20751/2" },␊ |
| 486 | ␉{ HDA_CODEC_CX20751_2, 0,␉"CX20751/2" },␊ |
| 487 | ␉{ HDA_CODEC_CX20751_4, 0,␉"CX20753/4" },␊ |
| 488 | ␉{ HDA_CODEC_CX20755, 0, "CX20755" },␊ |
| 489 | ␉{ HDA_CODEC_CX20756, 0, "CX20756" },␊ |
| 490 | ␉{ HDA_CODEC_CX20757, 0, "CX20757" },␊ |
| 491 | ␉{ HDA_CODEC_CX20952, 0, "CX20952" },␊ |
| 492 | ␊ |
| 493 | ␉{ HDA_CODEC_VT1708_8, 0, "VT1708_8" },␊ |
| 494 | ␉{ HDA_CODEC_VT1708_9, 0, "VT1708_9" },␊ |
| 495 | ␉{ HDA_CODEC_VT1708_A, 0, "VT1708_A" },␊ |
| 496 | ␉{ HDA_CODEC_VT1708_B, 0, "VT1708_B" },␊ |
| 497 | ␉{ HDA_CODEC_VT1709_0, 0, "VT1709_0" },␊ |
| 498 | ␉{ HDA_CODEC_VT1709_1, 0, "VT1709_1" },␊ |
| 499 | ␉{ HDA_CODEC_VT1709_2, 0, "VT1709_2" },␊ |
| 500 | ␉{ HDA_CODEC_VT1709_3, 0, "VT1709_3" },␊ |
| 501 | ␉{ HDA_CODEC_VT1709_4, 0, "VT1709_4" },␊ |
| 502 | ␉{ HDA_CODEC_VT1709_5, 0, "VT1709_5" },␊ |
| 503 | ␉{ HDA_CODEC_VT1709_6, 0, "VT1709_6" },␊ |
| 504 | ␉{ HDA_CODEC_VT1709_7, 0, "VT1709_7" },␊ |
| 505 | ␉{ HDA_CODEC_VT1708B_0, 0, "VT1708B_0" },␊ |
| 506 | ␉{ HDA_CODEC_VT1708B_1, 0, "VT1708B_1" },␊ |
| 507 | ␉{ HDA_CODEC_VT1708B_2, 0, "VT1708B_2" },␊ |
| 508 | ␉{ HDA_CODEC_VT1708B_3, 0, "VT1708B_3" },␊ |
| 509 | ␉{ HDA_CODEC_VT1708B_4, 0, "VT1708B_4" },␊ |
| 510 | ␉{ HDA_CODEC_VT1708B_5, 0, "VT1708B_5" },␊ |
| 511 | ␉{ HDA_CODEC_VT1708B_6, 0, "VT1708B_6" },␊ |
| 512 | ␉{ HDA_CODEC_VT1708B_7, 0, "VT1708B_7" },␊ |
| 513 | ␉{ HDA_CODEC_VT1708S_0, 0, "VT1708S_0" },␊ |
| 514 | ␉{ HDA_CODEC_VT1708S_1, 0, "VT1708S_1" },␊ |
| 515 | ␉{ HDA_CODEC_VT1708S_2, 0, "VT1708S_2" },␊ |
| 516 | ␉{ HDA_CODEC_VT1708S_3, 0, "VT1708S_3" },␊ |
| 517 | ␉{ HDA_CODEC_VT1708S_4, 0, "VT1708S_4" },␊ |
| 518 | ␉{ HDA_CODEC_VT1708S_5, 0, "VT1708S_5" },␊ |
| 519 | ␉{ HDA_CODEC_VT1708S_6, 0, "VT1708S_6" },␊ |
| 520 | ␉{ HDA_CODEC_VT1708S_7, 0, "VT1708S_7" },␊ |
| 521 | ␉{ HDA_CODEC_VT1702_0, 0, "VT1702_0" },␊ |
| 522 | ␉{ HDA_CODEC_VT1702_1, 0, "VT1702_1" },␊ |
| 523 | ␉{ HDA_CODEC_VT1702_2, 0, "VT1702_2" },␊ |
| 524 | ␉{ HDA_CODEC_VT1702_3, 0, "VT1702_3" },␊ |
| 525 | ␉{ HDA_CODEC_VT1702_4, 0, "VT1702_4" },␊ |
| 526 | ␉{ HDA_CODEC_VT1702_5, 0, "VT1702_5" },␊ |
| 527 | ␉{ HDA_CODEC_VT1702_6, 0, "VT1702_6" },␊ |
| 528 | ␉{ HDA_CODEC_VT1702_7, 0, "VT1702_7" },␊ |
| 529 | ␉{ HDA_CODEC_VT1716S_0, 0, "VT1716S_0" },␊ |
| 530 | ␉{ HDA_CODEC_VT1716S_1, 0, "VT1716S_1" },␊ |
| 531 | ␉{ HDA_CODEC_VT1718S_0, 0, "VT1718S_0" },␊ |
| 532 | ␉{ HDA_CODEC_VT1718S_1, 0, "VT1718S_1" },␊ |
| 533 | ␉{ HDA_CODEC_VT1802_0, 0, "VT1802_0" },␊ |
| 534 | ␉{ HDA_CODEC_VT1802_1, 0, "VT1802_1" },␊ |
| 535 | ␉{ HDA_CODEC_VT1812, 0, "VT1812" },␊ |
| 536 | ␉{ HDA_CODEC_VT1818S, 0, "VT1818S" },␊ |
| 537 | ␉{ HDA_CODEC_VT1828S, 0, "VT1828S" },␊ |
| 538 | ␉{ HDA_CODEC_VT2002P_0, 0, "VT2002P_0" },␊ |
| 539 | ␉{ HDA_CODEC_VT2002P_1, 0, "VT2002P_1" },␊ |
| 540 | ␉{ HDA_CODEC_VT2020, 0, "VT2020" },␊ |
| 541 | ␊ |
| 542 | ␉{ HDA_CODEC_ATIRS600_1, 0, "RS600" },␊ |
| 543 | ␉{ HDA_CODEC_ATIRS600_2, 0, "RS600" },␊ |
| 544 | ␉{ HDA_CODEC_ATIRS690, 0, "RS690/780" },␊ |
| 545 | ␉{ HDA_CODEC_ATIR6XX, 0, "R6xx" },␊ |
| 546 | ␊ |
| 547 | ␉{ HDA_CODEC_NVIDIAMCP67, 0, "MCP67" },␊ |
| 548 | ␉{ HDA_CODEC_NVIDIAMCP73, 0, "MCP73" },␊ |
| 549 | ␉{ HDA_CODEC_NVIDIAMCP78, 0, "MCP78" },␊ |
| 550 | ␉{ HDA_CODEC_NVIDIAMCP78_2, 0, "MCP78" },␊ |
| 551 | ␉{ HDA_CODEC_NVIDIAMCP78_3, 0, "MCP78" },␊ |
| 552 | ␉{ HDA_CODEC_NVIDIAMCP78_4, 0, "MCP78" },␊ |
| 553 | ␉{ HDA_CODEC_NVIDIAMCP7A, 0, "MCP7A" },␊ |
| 554 | ␉{ HDA_CODEC_NVIDIAGT220, 0, "GT220" },␊ |
| 555 | ␉{ HDA_CODEC_NVIDIAGT21X, 0, "GT21x" },␊ |
| 556 | ␉{ HDA_CODEC_NVIDIAMCP89, 0, "MCP89" },␊ |
| 557 | ␉{ HDA_CODEC_NVIDIAGT240, 0, "GT240" },␊ |
| 558 | ␉{ HDA_CODEC_NVIDIAGTS450, 0, "GTS450" },␊ |
| 559 | ␉{ HDA_CODEC_NVIDIAGT440, 0, "GT440" }, // Revision Id: 0x100100␊ |
| 560 | ␉{ HDA_CODEC_NVIDIAGTX470, 0, "GT470" },␊ |
| 561 | ␉{ HDA_CODEC_NVIDIAGTX550, 0, "GTX550" },␊ |
| 562 | ␉{ HDA_CODEC_NVIDIAGTX570, 0, "GTX570" },␊ |
| 563 | ␉{ HDA_CODEC_NVIDIAGT610, 0,␉"GT610" },␊ |
| 564 | ␊ |
| 565 | ␊ |
| 566 | ␉{ HDA_CODEC_INTELIP, 0, "Ibex Peak" },␊ |
| 567 | ␉{ HDA_CODEC_INTELBL, 0, "Bearlake" },␊ |
| 568 | ␉{ HDA_CODEC_INTELCA, 0, "Cantiga" },␊ |
| 569 | ␉{ HDA_CODEC_INTELEL, 0, "Eaglelake" },␊ |
| 570 | ␉{ HDA_CODEC_INTELIP2, 0, "Ibex Peak" },␊ |
| 571 | ␉{ HDA_CODEC_INTELCPT, 0, "Cougar Point" },␊ |
| 572 | ␉{ HDA_CODEC_INTELPPT, 0, "Panther Point" },␊ |
| 573 | ␉{ HDA_CODEC_INTELLLP, 0, "Lynx Point" },␊ |
| 574 | ␉{ HDA_CODEC_INTELCL, 0, "Crestline" },␊ |
| 575 | ␊ |
| 576 | ␉{ HDA_CODEC_SII1390, 0, "SiI1390 HDMi" },␊ |
| 577 | ␉{ HDA_CODEC_SII1392, 0, "SiI1392 HDMi" },␊ |
| 578 | ␊ |
| 579 | ␉// Unknown CODECs␊ |
| 580 | ␉{ HDA_CODEC_ADXXXX, 0, "Analog Devices" },␊ |
| 581 | ␉{ HDA_CODEC_AGEREXXXX, 0, "Lucent/Agere Systems" },␊ |
| 582 | ␉{ HDA_CODEC_ALCXXXX, 0, "Realtek" },␊ |
| 583 | ␉{ HDA_CODEC_ATIXXXX, 0, "ATI" },␊ |
| 584 | ␉{ HDA_CODEC_CAXXXX, 0, "Creative" },␊ |
| 585 | ␉{ HDA_CODEC_CMIXXXX, 0, "CMedia" },␊ |
| 586 | ␉{ HDA_CODEC_CMIXXXX2, 0, "CMedia" },␊ |
| 587 | ␉{ HDA_CODEC_CSXXXX, 0, "Cirrus Logic" },␊ |
| 588 | ␉{ HDA_CODEC_CXXXXX, 0, "Conexant" },␊ |
| 589 | ␉{ HDA_CODEC_CHXXXX, 0, "Chrontel" },␊ |
| 590 | ␉{ HDA_CODEC_IDTXXXX, 0, "IDT" },␊ |
| 591 | ␉{ HDA_CODEC_INTELXXXX, 0, "Intel" },␊ |
| 592 | ␉{ HDA_CODEC_MOTOXXXX, 0, "Motorola" },␊ |
| 593 | ␉{ HDA_CODEC_NVIDIAXXXX, 0, "NVIDIA" },␊ |
| 594 | ␉{ HDA_CODEC_SIIXXXX, 0, "Silicon Image" },␊ |
| 595 | ␉{ HDA_CODEC_STACXXXX, 0, "Sigmatel" },␊ |
| 596 | ␉{ HDA_CODEC_VTXXXX, 0, "VIA" },␊ |
| 597 | };␊ |
| 598 | ␊ |
| 599 | #define HDACC_CODECS_LEN (sizeof(know_codecs) / sizeof(know_codecs[0]))␊ |
| 600 | ␊ |
| 601 | /*****************␊ |
| 602 | * Device Methods␊ |
| 603 | *****************/␊ |
| 604 | ␊ |
| 605 | /* get HDA device name */␊ |
| 606 | static char *get_hda_controller_name(uint16_t controller_device_id, uint16_t controller_vendor_id)␊ |
| 607 | {␊ |
| 608 | ␉static char desc[128];␊ |
| 609 | ␊ |
| 610 | ␉const char *name_format = "Unknown HD Audio device %s";␊ |
| 611 | ␉uint32_t controller_model = ((controller_device_id << 16) | controller_vendor_id);␊ |
| 612 | ␉int i;␊ |
| 613 | ␊ |
| 614 | ␉/* Get format for vendor ID */␊ |
| 615 | ␉switch (controller_vendor_id)␊ |
| 616 | ␉{␊ |
| 617 | ␉␉case ATI_VENDORID:␊ |
| 618 | ␉␉␉name_format = "ATI %s HDA Controller (HDMi)"; break;␊ |
| 619 | ␊ |
| 620 | ␉␉case INTEL_VENDORID:␊ |
| 621 | ␉␉␉name_format = "Intel %s High Definition Audio Controller"; break;␊ |
| 622 | ␊ |
| 623 | ␉␉case NVIDIA_VENDORID:␊ |
| 624 | ␉␉␉name_format = "nVidia %s HDA Controller (HDMi)"; break;␊ |
| 625 | ␊ |
| 626 | ␉␉case RDC_VENDORID:␊ |
| 627 | ␉␉␉name_format = "RDC %s High Definition Audio Controller"; break;␊ |
| 628 | ␊ |
| 629 | ␉␉case SIS_VENDORID:␊ |
| 630 | ␉␉␉name_format = "SiS %s HDA Controller"; break;␊ |
| 631 | ␊ |
| 632 | ␉␉case ULI_VENDORID:␊ |
| 633 | ␉␉␉name_format = "ULI %s HDA Controller"; break;␊ |
| 634 | ␊ |
| 635 | ␉␉case VIA_VENDORID:␊ |
| 636 | ␉␉␉name_format = "VIA %s HDA Controller"; break;␊ |
| 637 | ␊ |
| 638 | ␉␉default:␊ |
| 639 | ␉␉␉break;␊ |
| 640 | ␉}␊ |
| 641 | ␊ |
| 642 | ␉for (i = 0; i < HDAC_DEVICES_LEN; i++)␊ |
| 643 | ␉{␊ |
| 644 | ␉␉if (know_hda_controller[i].model == controller_model)␊ |
| 645 | ␉␉{␊ |
| 646 | ␉␉␉snprintf(desc, sizeof(desc), name_format, know_hda_controller[i].desc);␊ |
| 647 | ␉␉␉return desc;␊ |
| 648 | ␉␉}␊ |
| 649 | ␉}␊ |
| 650 | ␊ |
| 651 | ␉/* Not in table */␊ |
| 652 | ␉snprintf(desc, sizeof(desc), "Unknown HD Audio device, vendor %04x, model %04x",␊ |
| 653 | ␉␉controller_vendor_id, controller_device_id);␊ |
| 654 | ␉return desc;␊ |
| 655 | }␊ |
| 656 | ␊ |
| 657 | /* get Codec name */␊ |
| 658 | static char *get_hda_codec_name( uint16_t codec_vendor_id, uint16_t codec_device_id, uint8_t codec_revision_id, uint8_t codec_stepping_id )␊ |
| 659 | {␊ |
| 660 | ␉static char desc[128];␊ |
| 661 | ␊ |
| 662 | ␉char␉␉*lName_format = NULL;␊ |
| 663 | ␉uint32_t␉lCodec_model = ((uint32_t)(codec_vendor_id) << 16) + (codec_device_id);␊ |
| 664 | ␉uint32_t␉lCodec_rev = (((uint16_t)(codec_revision_id) << 8) + codec_stepping_id);␊ |
| 665 | ␉int i;␊ |
| 666 | ␊ |
| 667 | ␉// Get format for vendor ID␊ |
| 668 | ␉switch ( codec_vendor_id ) // uint16_t␊ |
| 669 | ␉{␊ |
| 670 | ␉␉case ANALOGDEVICES_VENDORID:␊ |
| 671 | ␉␉␉lName_format = "Analog Devices %s"; break;␊ |
| 672 | ␊ |
| 673 | ␉␉case AGERE_VENDORID:␊ |
| 674 | ␉␉␉lName_format = "Agere Systems %s "; break;␊ |
| 675 | ␊ |
| 676 | ␉␉case REALTEK_VENDORID:␊ |
| 677 | ␉␉␉lName_format = "Realtek %s"; break;␊ |
| 678 | ␊ |
| 679 | ␉␉case ATI_VENDORID:␊ |
| 680 | ␉␉␉lName_format = "ATI %s"; break;␊ |
| 681 | ␊ |
| 682 | ␉␉case CREATIVE_VENDORID:␊ |
| 683 | ␉␉␉lName_format = "Creative %s"; break;␊ |
| 684 | ␊ |
| 685 | ␉␉case CMEDIA_VENDORID:␊ |
| 686 | ␉␉case CMEDIA2_VENDORID:␊ |
| 687 | ␉␉␉lName_format = "CMedia %s"; break;␊ |
| 688 | ␊ |
| 689 | ␉␉case CIRRUSLOGIC_VENDORID:␊ |
| 690 | ␉␉␉lName_format = "Cirrus Logic %s"; break;␊ |
| 691 | ␊ |
| 692 | ␉␉case CONEXANT_VENDORID:␊ |
| 693 | ␉␉␉lName_format = "Conexant %s"; break;␊ |
| 694 | ␊ |
| 695 | ␉␉case CHRONTEL_VENDORID:␊ |
| 696 | ␉␉␉lName_format = "Chrontel %s"; break;␊ |
| 697 | ␊ |
| 698 | ␉␉case IDT_VENDORID:␊ |
| 699 | ␉␉␉lName_format = "IDT %s"; break;␊ |
| 700 | ␊ |
| 701 | ␉␉case INTEL_VENDORID:␊ |
| 702 | ␉␉␉lName_format = "Intel %s"; break;␊ |
| 703 | ␊ |
| 704 | ␉␉case MOTO_VENDORID:␊ |
| 705 | ␉␉␉lName_format = "Motorola %s"; break;␊ |
| 706 | ␊ |
| 707 | ␉␉case NVIDIA_VENDORID:␊ |
| 708 | ␉␉␉lName_format = "nVidia %s"; break;␊ |
| 709 | ␊ |
| 710 | ␉␉case SII_VENDORID:␊ |
| 711 | ␉␉␉lName_format = "Silicon Image %s"; break;␊ |
| 712 | ␊ |
| 713 | ␉␉case SIGMATEL_VENDORID:␊ |
| 714 | ␉␉␉lName_format = "Sigmatel %s"; break;␊ |
| 715 | ␊ |
| 716 | ␉␉case VIA_VENDORID:␊ |
| 717 | ␉␉␉lName_format = "VIA %s"; break;␊ |
| 718 | ␊ |
| 719 | ␉␉default:␊ |
| 720 | ␉␉␉lName_format = UNKNOWN; break;␊ |
| 721 | ␉␉␉break;␊ |
| 722 | ␉}␊ |
| 723 | ␊ |
| 724 | ␉for (i = 0; i < HDACC_CODECS_LEN; i++)␊ |
| 725 | ␉{␊ |
| 726 | ␉␉if ( know_codecs[i].id == lCodec_model )␊ |
| 727 | ␉␉{␊ |
| 728 | ␉␉␉if ( ( know_codecs[i].rev == 0x00000000 ) || ( know_codecs[i].rev == lCodec_rev ) )␊ |
| 729 | ␉␉␉{␊ |
| 730 | //␉␉␉␉verbose("\tRevision in table (%06x) | burned chip revision (%06x).\n", know_codecs[i].rev, lCodec_rev );␊ |
| 731 | ␉␉␉␉snprintf(desc, sizeof(desc), lName_format, know_codecs[i].name);␊ |
| 732 | ␉␉␉␉return desc;␊ |
| 733 | ␉␉␉}␊ |
| 734 | ␉␉}␊ |
| 735 | ␉}␊ |
| 736 | ␊ |
| 737 | ␉if ( ( lName_format != UNKNOWN ) && ( strstr(lName_format, "%s" ) != NULL ) )␊ |
| 738 | ␉{␊ |
| 739 | ␉␉// Dirty way to remove '%s' from the end of the lName_format␊ |
| 740 | ␉␉int len = strlen(lName_format);␊ |
| 741 | ␉␉lName_format[len-2] = '\0';␊ |
| 742 | ␉}␊ |
| 743 | ␊ |
| 744 | ␉// Not in table␊ |
| 745 | ␉snprintf(desc, sizeof(desc), "unknown %s Codec", lName_format);␊ |
| 746 | ␉return desc;␊ |
| 747 | }␊ |
| 748 | ␊ |
| 749 | bool setup_hda_devprop(pci_dt_t *hda_dev)␊ |
| 750 | {␊ |
| 751 | ␉struct␉␉DevPropDevice␉*device = NULL;␊ |
| 752 | ␉char␉␉*devicepath = NULL;␊ |
| 753 | ␉char␉␉*controller_name = NULL;␊ |
| 754 | ␉int␉␉len;␊ |
| 755 | ␉uint8_t␉␉BuiltIn = 0x00;␊ |
| 756 | ␉uint16_t␉controller_vendor_id = hda_dev->vendor_id;␊ |
| 757 | ␉uint16_t␉controller_device_id = hda_dev->device_id;␊ |
| 758 | ␉const char␉*value;␊ |
| 759 | ␊ |
| 760 | ␉// Skip keys␊ |
| 761 | ␉bool do_skip_n_devprop = false;␊ |
| 762 | ␉bool do_skip_a_devprop = false;␊ |
| 763 | ␉getBoolForKey(kSkipNvidiaGfx, &do_skip_n_devprop, &bootInfo->chameleonConfig);␊ |
| 764 | ␉getBoolForKey(kSkipAtiGfx, &do_skip_a_devprop, &bootInfo->chameleonConfig);␊ |
| 765 | ␊ |
| 766 | ␉verbose("\tClass code: [%04X]\n", hda_dev->class_id);␊ |
| 767 | ␊ |
| 768 | ␉devicepath = get_pci_dev_path(hda_dev);␊ |
| 769 | ␉controller_name = get_hda_controller_name(controller_device_id, controller_vendor_id);␊ |
| 770 | ␊ |
| 771 | ␉if (!string)␊ |
| 772 | ␉{␊ |
| 773 | ␉␉string = devprop_create_string();␊ |
| 774 | ␉␉if (!string)␊ |
| 775 | ␉␉{␊ |
| 776 | ␉␉␉return 0;␊ |
| 777 | ␉␉}␊ |
| 778 | ␉}␊ |
| 779 | ␊ |
| 780 | ␉if (!devicepath)␊ |
| 781 | ␉{␊ |
| 782 | ␉␉return 0;␊ |
| 783 | ␉}␊ |
| 784 | ␊ |
| 785 | ␉device = devprop_add_device(string, devicepath);␊ |
| 786 | ␉if (!device)␊ |
| 787 | ␉{␊ |
| 788 | ␉␉return 0;␊ |
| 789 | ␉}␊ |
| 790 | ␊ |
| 791 | ␉verbose("\tModel name: %s [%04x:%04x] (rev %02x)\n\tSubsystem: [%04x:%04x]\n\t%s\n",␊ |
| 792 | ␉␉ controller_name, hda_dev->vendor_id, hda_dev->device_id, hda_dev->revision_id,␊ |
| 793 | ␉␉hda_dev->subsys_id.subsys.vendor_id, hda_dev->subsys_id.subsys.device_id, devicepath);␊ |
| 794 | ␊ |
| 795 | ␉probe_hda_bus(hda_dev->dev.addr);␊ |
| 796 | ␊ |
| 797 | ␉switch ((controller_device_id << 16) | controller_vendor_id)␊ |
| 798 | ␉{␊ |
| 799 | ␊ |
| 800 | ␉/***********************************************************************␊ |
| 801 | ␉* The above case are intended as for HDEF device at address 0x001B0000␊ |
| 802 | ␉***********************************************************************/␊ |
| 803 | ␉␉case HDA_INTEL_OAK:␊ |
| 804 | ␉␉case HDA_INTEL_BAY:␊ |
| 805 | ␉␉case HDA_INTEL_HSW1:␊ |
| 806 | ␉␉case HDA_INTEL_HSW2:␊ |
| 807 | ␉␉case HDA_INTEL_HSW3:␊ |
| 808 | ␉␉case HDA_INTEL_BDW:␊ |
| 809 | ␉␉case HDA_INTEL_CPT:␊ |
| 810 | ␉␉case HDA_INTEL_PATSBURG:␊ |
| 811 | ␉␉case HDA_INTEL_PPT1:␊ |
| 812 | ␉␉case HDA_INTEL_BRASWELL:␊ |
| 813 | ␉␉case HDA_INTEL_82801F:␊ |
| 814 | ␉␉case HDA_INTEL_63XXESB:␊ |
| 815 | ␉␉case HDA_INTEL_82801G:␊ |
| 816 | ␉␉case HDA_INTEL_82801H:␊ |
| 817 | ␉␉case HDA_INTEL_82801I:␊ |
| 818 | ␉␉case HDA_INTEL_ICH9:␊ |
| 819 | ␉␉case HDA_INTEL_82801JI:␊ |
| 820 | ␉␉case HDA_INTEL_82801JD:␊ |
| 821 | ␉␉case HDA_INTEL_PCH:␊ |
| 822 | ␉␉case HDA_INTEL_PCH2:␊ |
| 823 | ␉␉case HDA_INTEL_SCH:␊ |
| 824 | ␉␉case HDA_INTEL_LPT1:␊ |
| 825 | ␉␉case HDA_INTEL_LPT2:␊ |
| 826 | ␉␉case HDA_INTEL_WCPT:␊ |
| 827 | ␉␉case HDA_INTEL_WELLS1:␊ |
| 828 | ␉␉case HDA_INTEL_WELLS2:␊ |
| 829 | ␉␉case HDA_INTEL_WCPTLP:␊ |
| 830 | ␉␉case HDA_INTEL_LPTLP1:␊ |
| 831 | ␉␉case HDA_INTEL_LPTLP2:␊ |
| 832 | ␉␉case HDA_INTEL_SRSPLP:␊ |
| 833 | ␉␉case HDA_INTEL_SRSP:␊ |
| 834 | ␊ |
| 835 | ␉␉␉/* if the key value kHDEFLayoutID as a value set that value, if not will assign a default layout */␊ |
| 836 | ␉␉␉if (getValueForKey(kHDEFLayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDEF_LEN * 2)␊ |
| 837 | ␉␉␉{␊ |
| 838 | ␉␉␉␉uint8_t new_HDEF_layout_id[HDEF_LEN];␊ |
| 839 | ␉␉␉␉if (hex2bin(value, new_HDEF_layout_id, HDEF_LEN) == 0)␊ |
| 840 | ␉␉␉␉{␊ |
| 841 | ␉␉␉␉␉memcpy(default_HDEF_layout_id, new_HDEF_layout_id, HDEF_LEN);␊ |
| 842 | ␉␉␉␉␉verbose("\tUsing user supplied HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
| 843 | ␉␉␉␉␉default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]);␊ |
| 844 | ␉␉␉␉}␊ |
| 845 | ␉␉␉}␊ |
| 846 | ␉␉␉else␊ |
| 847 | ␉␉␉{␊ |
| 848 | ␉␉␉␉verbose("\tUsing default HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
| 849 | ␉␉␉␉␉default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]);␊ |
| 850 | ␉␉␉}␊ |
| 851 | ␉␉␉devprop_add_value(device, "layout-id", default_HDEF_layout_id, HDEF_LEN);␊ |
| 852 | ␉␉␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *)"Built-in", sizeof("Built-in")); // 0x09␊ |
| 853 | ␉␉␉devprop_add_value(device, "name", (uint8_t *)"audio", 6); // 0x06␊ |
| 854 | ␉␉␉devprop_add_value(device, "device-type", (uint8_t *)"High Definition Audio Controller", sizeof("High Definition Audio Controller"));␊ |
| 855 | ␉␉␉devprop_add_value(device, "device_type", (uint8_t *)"Sound", sizeof("Sound"));␊ |
| 856 | ␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊ |
| 857 | ␉␉␉devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", sizeof("onboard-1")); // 0x0a␊ |
| 858 | ␉␉␉// "AFGLowPowerState" = <03000000>␊ |
| 859 | ␉␉␉break;␊ |
| 860 | ␊ |
| 861 | ␉/*****************************************************************************************************************␊ |
| 862 | ␉ * The above case are intended as for HDAU (NVIDIA) device onboard audio for GFX card with Audio controller HDMi *␊ |
| 863 | ␉ *****************************************************************************************************************/␊ |
| 864 | ␉␉case HDA_NVIDIA_GK107:␊ |
| 865 | ␉␉case HDA_NVIDIA_GF110_1:␊ |
| 866 | ␉␉case HDA_NVIDIA_GF110_2:␊ |
| 867 | ␉␉case HDA_NVIDIA_GK106:␊ |
| 868 | ␉␉case HDA_NVIDIA_GK104:␊ |
| 869 | ␉␉case HDA_NVIDIA_GF119:␊ |
| 870 | ␉␉case HDA_NVIDIA_GT116:␊ |
| 871 | ␉␉case HDA_NVIDIA_GT104:␊ |
| 872 | ␉␉case HDA_NVIDIA_GT108:␊ |
| 873 | ␉␉case HDA_NVIDIA_GT106:␊ |
| 874 | ␉␉case HDA_NVIDIA_GT100:␊ |
| 875 | ␉␉case HDA_NVIDIA_0BE4:␊ |
| 876 | ␉␉case HDA_NVIDIA_0BE3:␊ |
| 877 | ␉␉case HDA_NVIDIA_0BE2:␊ |
| 878 | ␉␉␉if ( do_skip_n_devprop )␊ |
| 879 | ␉␉␉{␊ |
| 880 | ␉␉␉␉verbose("Skip Nvidia audio device!\n");␊ |
| 881 | ␉␉␉}␊ |
| 882 | ␉␉␉else␊ |
| 883 | ␉␉␉{␊ |
| 884 | ␉␉␉␉/* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */␊ |
| 885 | ␉␉␉␉if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2)␊ |
| 886 | ␉␉␉␉{␊ |
| 887 | ␉␉␉␉␉uint8_t new_HDAU_layout_id[HDAU_LEN];␊ |
| 888 | ␉␉␉␉␉if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0)␊ |
| 889 | ␉␉␉␉␉{␊ |
| 890 | ␉␉␉␉␉␉memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN);␊ |
| 891 | ␉␉␉␉␉␉verbose("\tUsing user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
| 892 | ␉␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
| 893 | ␉␉␉␉␉}␊ |
| 894 | ␉␉␉␉}␊ |
| 895 | ␉␉␉␉else␊ |
| 896 | ␉␉␉␉{␊ |
| 897 | ␉␉␉␉␉verbose("\tUsing default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
| 898 | ␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
| 899 | ␉␉␉␉}␊ |
| 900 | ␊ |
| 901 | ␉␉␉␉devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/␊ |
| 902 | ␉␉␉␉devprop_add_value(device, "@0,connector-type", connector_type_value, 4);␊ |
| 903 | ␉␉␉␉devprop_add_value(device, "@1,connector-type", connector_type_value, 4);␊ |
| 904 | ␉␉␉␉devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", sizeof("onboard-2"));␊ |
| 905 | ␉␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊ |
| 906 | ␉␉␉}␊ |
| 907 | ␉␉␉break;␊ |
| 908 | ␊ |
| 909 | ␉␉/**************************************************************************************************************␊ |
| 910 | ␉␉ * The above case are intended as for HDAU (ATi) device onboard audio for GFX card with Audio controller HDMi *␊ |
| 911 | ␉␉ **************************************************************************************************************/␊ |
| 912 | ␉␉case HDA_ATI_SB450:␊ |
| 913 | ␉␉case HDA_ATI_SB600:␊ |
| 914 | ␉␉case HDA_ATI_HUDSON:␊ |
| 915 | ␉␉case HDA_ATI_RS600:␊ |
| 916 | ␉␉case HDA_ATI_RS690:␊ |
| 917 | ␉␉case HDA_ATI_RS780:␊ |
| 918 | ␉␉case HDA_ATI_R600:␊ |
| 919 | ␉␉case HDA_ATI_RV630:␊ |
| 920 | ␉␉case HDA_ATI_RV610:␊ |
| 921 | ␉␉case HDA_ATI_RV670:␊ |
| 922 | ␉␉case HDA_ATI_RV635:␊ |
| 923 | ␉␉case HDA_ATI_RV620:␊ |
| 924 | ␉␉case HDA_ATI_RV770:␊ |
| 925 | ␉␉case HDA_ATI_RV730:␊ |
| 926 | ␉␉case HDA_ATI_RV710:␊ |
| 927 | ␉␉case HDA_ATI_RV740:␊ |
| 928 | ␉␉case HDA_ATI_RV870:␊ |
| 929 | ␉␉case HDA_ATI_RV840:␊ |
| 930 | ␉␉case HDA_ATI_RV830:␊ |
| 931 | ␉␉case HDA_ATI_RV810:␊ |
| 932 | ␉␉case HDA_ATI_RV970:␊ |
| 933 | ␉␉case HDA_ATI_RV940:␊ |
| 934 | ␉␉case HDA_ATI_RV930:␊ |
| 935 | ␉␉case HDA_ATI_RV910:␊ |
| 936 | ␉␉case HDA_ATI_R1000:␊ |
| 937 | ␉␉case HDA_ATI_SI:␊ |
| 938 | ␉␉case HDA_ATI_VERDE:␊ |
| 939 | ␉␉␉if ( do_skip_a_devprop )␊ |
| 940 | ␉␉␉{␊ |
| 941 | ␉␉␉␉verbose("Skip ATi/AMD audio device!\n");␊ |
| 942 | ␉␉␉}␊ |
| 943 | ␉␉␉else␊ |
| 944 | ␉␉␉{␊ |
| 945 | ␉␉␉␉/* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */␊ |
| 946 | ␉␉␉␉if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2)␊ |
| 947 | ␉␉␉␉{␊ |
| 948 | ␉␉␉␉␉uint8_t new_HDAU_layout_id[HDAU_LEN];␊ |
| 949 | ␉␉␉␉␉if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0)␊ |
| 950 | ␉␉␉␉␉{␊ |
| 951 | ␉␉␉␉␉␉memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN);␊ |
| 952 | ␉␉␉␉␉␉verbose("\tUsing user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
| 953 | ␉␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
| 954 | ␉␉␉␉␉}␊ |
| 955 | ␉␉␉␉}␊ |
| 956 | ␉␉␉␉else␊ |
| 957 | ␉␉␉␉{␊ |
| 958 | ␉␉␉␉␉verbose("\tUsing default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
| 959 | ␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
| 960 | ␉␉␉␉}␊ |
| 961 | ␊ |
| 962 | ␉␉␉␉devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/␊ |
| 963 | ␉␉␉␉devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", 10);␊ |
| 964 | ␉␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊ |
| 965 | ␉␉␉}␊ |
| 966 | ␉␉␉break;␊ |
| 967 | ␊ |
| 968 | ␉␉default:␊ |
| 969 | ␉␉␉break;␊ |
| 970 | ␉}␊ |
| 971 | ␊ |
| 972 | ␉stringdata = malloc(sizeof(uint8_t) * string->length);␊ |
| 973 | ␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊ |
| 974 | ␉stringlength = string->length;␊ |
| 975 | ␊ |
| 976 | ␉return true;␊ |
| 977 | }␊ |
| 978 | ␊ |
| 979 | /*␊ |
| 980 | * Structure of HDA MMIO Region␊ |
| 981 | */␊ |
| 982 | struct HDARegs␊ |
| 983 | {␊ |
| 984 | ␉uint16_t gcap;␊ |
| 985 | ␉uint8_t vmin;␊ |
| 986 | ␉uint8_t vmaj;␊ |
| 987 | ␉uint16_t outpay;␊ |
| 988 | ␉uint16_t inpay;␊ |
| 989 | ␉uint32_t gctl;␊ |
| 990 | ␉uint16_t wakeen;␊ |
| 991 | ␉uint16_t statests;␊ |
| 992 | ␉uint16_t gsts;␊ |
| 993 | ␉uint8_t rsvd0[6];␊ |
| 994 | ␉uint16_t outstrmpay;␊ |
| 995 | ␉uint16_t instrmpay;␊ |
| 996 | ␉uint8_t rsvd1[4];␊ |
| 997 | ␉uint32_t intctl;␊ |
| 998 | ␉uint32_t intsts;␊ |
| 999 | ␉uint8_t rsvd2[8];␊ |
| 1000 | ␉uint32_t walclk;␊ |
| 1001 | ␉uint8_t rsvd3[4];␊ |
| 1002 | ␉uint32_t ssync;␊ |
| 1003 | ␉uint8_t rsvd4[4];␊ |
| 1004 | ␉uint32_t corblbase;␊ |
| 1005 | ␉uint32_t corbubase;␊ |
| 1006 | ␉uint16_t corbwp;␊ |
| 1007 | ␉uint16_t corbrp;␊ |
| 1008 | ␉uint8_t corbctl;␊ |
| 1009 | ␉uint8_t corbsts;␊ |
| 1010 | ␉uint8_t corbsize;␊ |
| 1011 | ␉uint8_t rsvd5;␊ |
| 1012 | ␉uint32_t rirblbase;␊ |
| 1013 | ␉uint32_t rirbubase;␊ |
| 1014 | ␉uint16_t rirbwp;␊ |
| 1015 | ␉uint16_t rintcnt;␊ |
| 1016 | ␉uint8_t rirbctl;␊ |
| 1017 | ␉uint8_t rirbsts;␊ |
| 1018 | ␉uint8_t rirbsize;␊ |
| 1019 | ␉uint8_t rsvd6;␊ |
| 1020 | ␉uint32_t icoi;␊ |
| 1021 | ␉uint32_t icii;␊ |
| 1022 | ␉uint16_t icis;␊ |
| 1023 | ␉uint8_t rsvd7[6];␊ |
| 1024 | ␉uint32_t dpiblbase;␊ |
| 1025 | ␉uint32_t dpibubase;␊ |
| 1026 | ␉uint8_t rsvd8[8];␊ |
| 1027 | /*␊ |
| 1028 | * Stream Descriptors follow␊ |
| 1029 | */␊ |
| 1030 | } __attribute__((aligned(16), packed));␊ |
| 1031 | ␊ |
| 1032 | /*␊ |
| 1033 | * Data to be discovered for HDA codecs␊ |
| 1034 | */␊ |
| 1035 | ␊ |
| 1036 | struct HDACodecInfo␊ |
| 1037 | {␊ |
| 1038 | ␉uint16_t vendor_id;␊ |
| 1039 | ␉uint16_t device_id;␊ |
| 1040 | ␉uint8_t revision_id;␊ |
| 1041 | ␉uint8_t stepping_id;␊ |
| 1042 | ␉uint8_t maj_rev;␊ |
| 1043 | ␉uint8_t min_rev;␊ |
| 1044 | ␉uint8_t num_function_groups;␊ |
| 1045 | ␉const char *name;␊ |
| 1046 | };␊ |
| 1047 | ␊ |
| 1048 | /*␊ |
| 1049 | * Timing Functions␊ |
| 1050 | */␊ |
| 1051 | ␊ |
| 1052 | static int wait_for_register_state_16(uint16_t const volatile* reg,␊ |
| 1053 | ␉␉␉␉uint16_t target_mask,␊ |
| 1054 | ␉␉␉␉uint16_t target_value,␊ |
| 1055 | ␉␉␉␉uint32_t timeout_us,␊ |
| 1056 | ␉␉␉␉uint32_t tsc_ticks_per_us)␊ |
| 1057 | {␊ |
| 1058 | ␉uint64_t deadline = rdtsc64() + MultU32x32(timeout_us, tsc_ticks_per_us);␊ |
| 1059 | ␉do␊ |
| 1060 | ␉{␊ |
| 1061 | ␉␉uint16_t value = *reg;␊ |
| 1062 | ␉␉if ((value & target_mask) == target_value)␊ |
| 1063 | ␉␉␉return 0;␊ |
| 1064 | ␉␉CpuPause();␊ |
| 1065 | ␉}␊ |
| 1066 | ␉while (rdtsc64() < deadline);␊ |
| 1067 | ␉return -1;␊ |
| 1068 | }␊ |
| 1069 | ␊ |
| 1070 | static void delay_us(uint32_t timeout_us, uint32_t tsc_ticks_per_us)␊ |
| 1071 | {␊ |
| 1072 | ␉uint64_t deadline = rdtsc64() + MultU32x32(timeout_us, tsc_ticks_per_us);␊ |
| 1073 | ␊ |
| 1074 | ␉do␊ |
| 1075 | ␉{␊ |
| 1076 | ␉␉CpuPause();␊ |
| 1077 | ␉}␊ |
| 1078 | ␉while (rdtsc64() < deadline);␊ |
| 1079 | }␊ |
| 1080 | ␊ |
| 1081 | static struct HDARegs volatile* hdaMemory = NULL;␊ |
| 1082 | static uint32_t tsc_ticks_per_us = 0U;␊ |
| 1083 | ␊ |
| 1084 | #define ICIS_ICB 1U␊ |
| 1085 | #define ICIS_IRV 2U␊ |
| 1086 | ␊ |
| 1087 | static int immediate_command(uint32_t command, uint32_t* response)␊ |
| 1088 | {␊ |
| 1089 | ␉/*␊ |
| 1090 | ␉ * Wait up to 1ms for for ICB 0␊ |
| 1091 | ␉ */␊ |
| 1092 | ␉(void) wait_for_register_state_16(&hdaMemory->icis, ICIS_ICB, 0U, 1000U, tsc_ticks_per_us);␊ |
| 1093 | ␉/*␊ |
| 1094 | ␉ * Ignore timeout and force ICB to 0␊ |
| 1095 | ␉ * Clear IRV while at it␊ |
| 1096 | ␉ */␊ |
| 1097 | ␉hdaMemory->icis = ICIS_IRV;␊ |
| 1098 | ␉/*␊ |
| 1099 | ␉ * Program command␊ |
| 1100 | ␉ */␊ |
| 1101 | ␉hdaMemory->icoi = command;␊ |
| 1102 | ␉/*␊ |
| 1103 | ␉ * Trigger command␊ |
| 1104 | ␉ * Clear IRV again just in case␊ |
| 1105 | ␉ */␊ |
| 1106 | ␉hdaMemory->icis = ICIS_ICB | ICIS_IRV;␊ |
| 1107 | ␉/*␊ |
| 1108 | ␉ * Wait up to 1ms for response␊ |
| 1109 | ␉ */␊ |
| 1110 | ␉if (wait_for_register_state_16(&hdaMemory->icis, ICIS_IRV, ICIS_IRV, 1000U, tsc_ticks_per_us) < 0)␊ |
| 1111 | ␉{␊ |
| 1112 | ␉␉/*␊ |
| 1113 | ␉␉ * response timed out␊ |
| 1114 | ␉␉ */␊ |
| 1115 | ␉␉return -1;␊ |
| 1116 | ␉}␊ |
| 1117 | ␉*response = hdaMemory->icii;␊ |
| 1118 | ␉return 0;␊ |
| 1119 | }␊ |
| 1120 | ␊ |
| 1121 | #define PACK_CID(x) ((x & 15U) << 28)␊ |
| 1122 | #define PACK_NID(x) ((x & 127U) << 20)␊ |
| 1123 | #define PACK_VERB_12BIT(x) ((x & 4095U) << 8)␊ |
| 1124 | #define PACK_PAYLOAD_8BIT(x) (x & UINT8_MAX)␊ |
| 1125 | #define VERB_GET_PARAMETER 0xF00U␊ |
| 1126 | ␊ |
| 1127 | static uint32_t get_parameter(uint8_t codec_id, uint8_t node_id, uint8_t parameter_id)␊ |
| 1128 | {␊ |
| 1129 | ␉uint32_t command, response;␊ |
| 1130 | ␊ |
| 1131 | ␉command = PACK_CID(codec_id) | PACK_NID(node_id) | PACK_VERB_12BIT(VERB_GET_PARAMETER) | PACK_PAYLOAD_8BIT(parameter_id);␊ |
| 1132 | ␉response = UINT32_MAX;␊ |
| 1133 | ␊ |
| 1134 | ␉/*␊ |
| 1135 | ␉ * Ignore timeout, return UINT32_MAX as error value␊ |
| 1136 | ␉ */␊ |
| 1137 | ␉(void) immediate_command(command, &response);␊ |
| 1138 | ␉return response;␊ |
| 1139 | }␊ |
| 1140 | ␊ |
| 1141 | #define PARAMETER_VID_DID 0U␊ |
| 1142 | #define PARAMETER_RID 2U␊ |
| 1143 | #define PARAMETER_NUM_NODES 4U␊ |
| 1144 | ␊ |
| 1145 | static void probe_hda_codec(uint8_t codec_id, struct HDACodecInfo *codec_info)␊ |
| 1146 | {␊ |
| 1147 | ␉uint32_t response;␊ |
| 1148 | ␉CDBG("\tprobing codec %d\n", codec_id);␊ |
| 1149 | ␉response = get_parameter(codec_id, 0U, PARAMETER_VID_DID);␊ |
| 1150 | ␉codec_info->vendor_id = (response >> 16) & UINT16_MAX;␊ |
| 1151 | ␉codec_info->device_id = response & UINT16_MAX;␊ |
| 1152 | ␉response = get_parameter(codec_id, 0U, PARAMETER_RID);␊ |
| 1153 | ␉codec_info->revision_id = (response >> 8) & UINT8_MAX;␊ |
| 1154 | ␉codec_info->stepping_id = response & UINT8_MAX;␊ |
| 1155 | ␉codec_info->maj_rev = (response >> 20) & 15U;␊ |
| 1156 | ␉codec_info->min_rev = (response >> 16) & 15U;␊ |
| 1157 | ␉response = get_parameter(codec_id, 0U, PARAMETER_NUM_NODES);␊ |
| 1158 | ␉codec_info->num_function_groups = response & UINT8_MAX;␊ |
| 1159 | ␉codec_info->name = get_hda_codec_name(codec_info->vendor_id, codec_info->device_id, codec_info->revision_id, codec_info->stepping_id);␊ |
| 1160 | ␊ |
| 1161 | }␊ |
| 1162 | ␊ |
| 1163 | static int getHDABar(uint32_t pci_addr, uint32_t* bar_phys_addr)␊ |
| 1164 | {␊ |
| 1165 | ␉uint32_t barlow = pci_config_read32(pci_addr, PCI_BASE_ADDRESS_0);␊ |
| 1166 | ␊ |
| 1167 | ␉if ((barlow & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY)␊ |
| 1168 | ␉{␊ |
| 1169 | ␉␉CDBG("\tBAR0 for HDA Controller 0x%x is not an MMIO space\n", pci_addr);␊ |
| 1170 | ␉␉return -1;␊ |
| 1171 | ␉}␊ |
| 1172 | ␊ |
| 1173 | ␉if ((barlow & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64)␊ |
| 1174 | ␉{␊ |
| 1175 | ␉␉uint32_t barhigh = pci_config_read32(pci_addr, PCI_BASE_ADDRESS_1);␊ |
| 1176 | ␊ |
| 1177 | ␉␉if (barhigh)␊ |
| 1178 | ␉␉{␊ |
| 1179 | ␉␉␉//verbose("\tBAR0 for HDA Controller 0x%x is located ouside 32-bit physical address space (0x%x%08x)\n",␊ |
| 1180 | ␉␉␉//pci_addr, barhigh, barlow & PCI_BASE_ADDRESS_MEM_MASK);␊ |
| 1181 | ␉␉␉return -1;␊ |
| 1182 | ␉␉}␊ |
| 1183 | ␉}␊ |
| 1184 | ␊ |
| 1185 | ␉if (bar_phys_addr)␊ |
| 1186 | ␉{␊ |
| 1187 | ␉␉*bar_phys_addr = (barlow & PCI_BASE_ADDRESS_MEM_MASK);␊ |
| 1188 | ␉}␊ |
| 1189 | ␉return 0;␊ |
| 1190 | }␊ |
| 1191 | ␊ |
| 1192 | void probe_hda_bus(uint32_t pci_addr)␊ |
| 1193 | {␊ |
| 1194 | ␉uint64_t tsc_frequency;␊ |
| 1195 | ␉uint32_t bar_phys_addr;␊ |
| 1196 | ␉uint16_t pci_cmd, statests;␊ |
| 1197 | ␉uint16_t const pci_cmd_wanted = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;␊ |
| 1198 | ␉uint8_t codec_id, original_reset_state;␊ |
| 1199 | ␉struct HDACodecInfo codec_info;␊ |
| 1200 | ␊ |
| 1201 | ␉CDBG("\tlooking for HDA bar0 on pci_addr 0x%x\n", pci_addr);␊ |
| 1202 | ␉if (getHDABar(pci_addr, &bar_phys_addr) < 0)␊ |
| 1203 | ␉{␊ |
| 1204 | ␉␉return;␊ |
| 1205 | ␉}␊ |
| 1206 | ␊ |
| 1207 | ␉CDBG("\tfound HDA memory at 0x%x\n", bar_phys_addr);␊ |
| 1208 | ␉hdaMemory = (struct HDARegs volatile*) bar_phys_addr;␊ |
| 1209 | ␊ |
| 1210 | ␉tsc_frequency = Platform.CPU.TSCFrequency;␊ |
| 1211 | ␉tsc_ticks_per_us = DivU64x32(tsc_frequency, 1000000U); // TSC ticks per microsecond␊ |
| 1212 | ␉CDBG("\ttsc_ticks_per_us %d\n", tsc_ticks_per_us);␊ |
| 1213 | ␊ |
| 1214 | ␉/*␊ |
| 1215 | ␉ * Enable Memory Space and Bus Mastering␊ |
| 1216 | ␉ */␊ |
| 1217 | ␉pci_cmd = pci_config_read16(pci_addr, PCI_COMMAND);␊ |
| 1218 | ␉if ((pci_cmd & pci_cmd_wanted) != pci_cmd_wanted)␊ |
| 1219 | ␉{␊ |
| 1220 | ␉␉pci_cmd |= pci_cmd_wanted;␊ |
| 1221 | ␉␉pci_config_write16(pci_addr, PCI_COMMAND, pci_cmd);␊ |
| 1222 | ␉}␊ |
| 1223 | ␊ |
| 1224 | ␉/*␊ |
| 1225 | ␉ * Remember entering reset state␊ |
| 1226 | ␉ */␊ |
| 1227 | ␉original_reset_state = (hdaMemory->gctl & HDAC_GCTL_CRST) ? 1U : 0U;␊ |
| 1228 | ␊ |
| 1229 | ␉/*␊ |
| 1230 | ␉ * Reset HDA Controller␊ |
| 1231 | ␉ */␊ |
| 1232 | ␉hdaMemory->wakeen = 0U;␊ |
| 1233 | ␉hdaMemory->statests = UINT16_MAX;␊ |
| 1234 | ␉hdaMemory->gsts = UINT16_MAX;␊ |
| 1235 | ␉hdaMemory->intctl = 0U;␊ |
| 1236 | ␉CDBG("\tStarting reset\n");␊ |
| 1237 | ␉hdaMemory->gctl = 0U;␊ |
| 1238 | ␊ |
| 1239 | ␉/*␊ |
| 1240 | ␉ * Wait up to 10ms to enter Reset␊ |
| 1241 | ␉ */␊ |
| 1242 | ␉if (wait_for_register_state_16((uint16_t volatile const*) &hdaMemory->gctl,␊ |
| 1243 | ␉␉␉␉HDAC_GCTL_CRST,␊ |
| 1244 | ␉␉␉␉0U,␊ |
| 1245 | ␉␉␉␉10000U,␊ |
| 1246 | ␉␉␉␉tsc_ticks_per_us) < 0)␊ |
| 1247 | ␉{␊ |
| 1248 | ␉␉CDBG("\tHDA Controller 0x%x timed out 10ms entering reset\n", pci_addr);␊ |
| 1249 | ␉␉return;␊ |
| 1250 | ␉}␊ |
| 1251 | ␉CDBG("\tReset asserted, delay 100us\n");␊ |
| 1252 | ␊ |
| 1253 | ␉/*␊ |
| 1254 | ␉ * Delay 2400 BCLK (100us)␊ |
| 1255 | ␉ */␊ |
| 1256 | ␉delay_us(100U, tsc_ticks_per_us);␊ |
| 1257 | ␉CDBG("\tDeasserting reset\n");␊ |
| 1258 | ␊ |
| 1259 | ␉/*␊ |
| 1260 | ␉ * Wait up to 10ms to exit Reset␊ |
| 1261 | ␉ */␊ |
| 1262 | ␉hdaMemory->gctl = HDAC_GCTL_CRST;␊ |
| 1263 | ␉if (wait_for_register_state_16((uint16_t volatile const*) &hdaMemory->gctl,␊ |
| 1264 | ␉␉␉␉HDAC_GCTL_CRST,␊ |
| 1265 | ␉␉␉␉HDAC_GCTL_CRST,␊ |
| 1266 | ␉␉␉␉10000U,␊ |
| 1267 | ␉␉␉␉tsc_ticks_per_us) < 0)␊ |
| 1268 | ␉{␊ |
| 1269 | ␉␉CDBG("\tHDA Controller 0x%x timed out 10ms exiting reset\n", pci_addr);␊ |
| 1270 | ␉␉return;␊ |
| 1271 | ␉}␊ |
| 1272 | ␉CDBG("\tReset complete\n");␊ |
| 1273 | ␊ |
| 1274 | ␉/*␊ |
| 1275 | ␉ * Wait 1ms for codecs to request enumeration (spec says 521us).␊ |
| 1276 | ␉ */␊ |
| 1277 | ␉delay_us(1000U, tsc_ticks_per_us);␊ |
| 1278 | ␊ |
| 1279 | ␉/*␊ |
| 1280 | ␉ * See which codecs want enumeration␊ |
| 1281 | ␉ */␊ |
| 1282 | ␉statests = hdaMemory->statests;␊ |
| 1283 | ␉hdaMemory->statests = statests; // clear statests␊ |
| 1284 | ␉CDBG("\tstatests is now 0x%x\n", statests);␊ |
| 1285 | ␉codec_id = 0U;␊ |
| 1286 | ␉while (statests)␊ |
| 1287 | ␉{␊ |
| 1288 | ␉␉if (statests & 1U)␊ |
| 1289 | ␉␉{␊ |
| 1290 | ␉␉␉probe_hda_codec(codec_id, &codec_info);␊ |
| 1291 | ␊ |
| 1292 | ␉␉␉verbose("\tFound %s (%04x%04x), rev(%04x)",␊ |
| 1293 | ␉␉␉codec_info.name,␊ |
| 1294 | ␉␉␉codec_info.vendor_id,␊ |
| 1295 | ␉␉␉codec_info.device_id,␊ |
| 1296 | ␉␉␉codec_info.revision_id);␊ |
| 1297 | #if DEBUG_CODEC␊ |
| 1298 | ␉␉␉verbose(", stepping 0x%x, major rev 0x%x, minor rev 0x%x, %d function groups",␊ |
| 1299 | ␉␉␉codec_info.stepping_id,␊ |
| 1300 | ␉␉␉codec_info.maj_rev,␊ |
| 1301 | ␉␉␉codec_info.min_rev,␊ |
| 1302 | ␉␉␉codec_info.num_function_groups);␊ |
| 1303 | #endif␊ |
| 1304 | ␉␉␉verbose("\n");␊ |
| 1305 | ␉␉}␊ |
| 1306 | ␉␉++codec_id;␊ |
| 1307 | ␉␉statests >>= 1;␊ |
| 1308 | ␉}␊ |
| 1309 | ␊ |
| 1310 | ␉/*␊ |
| 1311 | ␉ * Restore reset state entered with␊ |
| 1312 | ␉ */␊ |
| 1313 | ␉if (!original_reset_state)␊ |
| 1314 | ␉{␊ |
| 1315 | ␉␉hdaMemory->gctl = 0U;␊ |
| 1316 | ␉}␊ |
| 1317 | }␊ |
| 1318 | |
