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1/*
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>
3 * AsereBLN: 2009: cleanup and bugfix
4 */
5
6#ifndef __LIBSAIO_CPU_H
7#define __LIBSAIO_CPU_H
8
9#include "libsaio.h"
10
11extern void scan_cpu(PlatformInfo_t *);
12
13#define bit(n)(1UL << (n))
14#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
15#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
16
17#defineMSR_IA32_PERF_STATUS0x198
18#define MSR_IA32_PERF_CONTROL0x199
19#define MSR_IA32_EXT_CONFIG0x00EE
20#define MSR_FLEX_RATIO0x194
21#defineMSR_PLATFORM_INFO0xCE
22#define K8_FIDVID_STATUS0xC0010042
23#define K10_COFVID_STATUS0xC0010071
24
25#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
26
27// DFE: This constant comes from older xnu:
28#define CLKNUM1193182/* formerly 1193167 */
29
30// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM
31#define CALIBRATE_TIME_MSEC30/* 30 msecs */
32#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
33
34static inline uint64_t rdtsc64(void)
35{
36uint64_t ret;
37__asm__ volatile("rdtsc" : "=A" (ret));
38return ret;
39}
40
41static inline uint64_t rdmsr64(uint32_t msr)
42{
43 uint64_t ret;
44 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));
45 return ret;
46}
47
48static inline void wrmsr64(uint32_t msr, uint64_t val)
49{
50__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));
51}
52
53static inline void intel_waitforsts(void) {
54uint32_t inline_timeout = 100000;
55while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }
56}
57
58static inline void do_cpuid(uint32_t selector, uint32_t *data)
59{
60asm volatile ("cpuid"
61 : "=a" (data[0]),
62 "=b" (data[1]),
63 "=c" (data[2]),
64 "=d" (data[3])
65 : "a" (selector));
66}
67
68static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)
69{
70asm volatile ("cpuid"
71 : "=a" (data[0]),
72 "=b" (data[1]),
73 "=c" (data[2]),
74 "=d" (data[3])
75 : "a" (selector), "c" (selector2));
76}
77
78// DFE: enable_PIT2 and disable_PIT2 come from older xnu
79
80/*
81 * Enable or disable timer 2.
82 * Port 0x61 controls timer 2:
83 * bit 0 gates the clock,
84 * bit 1 gates output to speaker.
85 */
86static inline void enable_PIT2(void)
87{
88 /* Enable gate, disable speaker */
89 __asm__ volatile(
90 " inb $0x61,%%al \n\t"
91 " and $0xFC,%%al \n\t" /* & ~0x03 */
92 " or $1,%%al \n\t"
93 " outb %%al,$0x61 \n\t"
94 : : : "%al" );
95}
96
97static inline void disable_PIT2(void)
98{
99 /* Disable gate and output to speaker */
100 __asm__ volatile(
101 " inb $0x61,%%al \n\t"
102 " and $0xFC,%%al \n\t"/* & ~0x03 */
103 " outb %%al,$0x61 \n\t"
104 : : : "%al" );
105}
106
107// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are
108// roughly based on Linux code
109
110/* Set the 8254 channel 2 to mode 0 with the specified value.
111 In mode 0, the counter will initially set its gate low when the
112 timer expires. For this to be useful, you ought to set it high
113 before calling this function. The enable_PIT2 function does this.
114 */
115static inline void set_PIT2_mode0(uint16_t value)
116{
117 __asm__ volatile(
118 " movb $0xB0,%%al \n\t"
119 " outb%%al,$0x43\n\t"
120 " movb%%dl,%%al\n\t"
121 " outb%%al,$0x42\n\t"
122 " movb%%dh,%%al\n\t"
123 " outb%%al,$0x42"
124 : : "d"(value) /*: no clobber */ );
125}
126
127/* Returns the number of times the loop ran before the PIT2 signaled */
128static inline unsigned long poll_PIT2_gate(void)
129{
130 unsigned long count = 0;
131 unsigned char nmi_sc_val;
132 do {
133 ++count;
134 __asm__ volatile(
135 "inb$0x61,%0"
136 : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);
137 } while( (nmi_sc_val & 0x20) == 0);
138 return count;
139}
140
141#endif /* !__LIBSAIO_CPU_H */
142

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