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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12␉#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16␉#define DBG(x...)␉printf(x)␊
17#else␊
18␉#define DBG(x...)␊
19#endif␊
20␊
21#define XEON "Xeon"␊
22#define CORE_M "Core(TM) M"␊
23#define CORE_I3 "Core(TM) i3"␊
24#define CORE_I5 "Core(TM) i5"␊
25#define CORE_I7 "Core(TM) i7"␊
26␊
27bool getProcessorInformationExternalClock(returnType *value)␊
28{␊
29␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
30␉{␊
31␉␉switch (Platform.CPU.Family)␊
32␉␉{␊
33␉␉␉case 0x06:␊
34␉␉␉␉switch (Platform.CPU.Model)␊
35␉␉␉␉{␊
36␉␉␉␉␉// set external clock to 0 for SANDY␊
37␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
38␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
39␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
40␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
41␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
42␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
43␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
44␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
45␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
46␊
47␉␉␉␉␉␉value->word = 0;␊
48␉␉␉␉␉␉break;␊
49␉␉␉␉␉default:␊
50␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
51␉␉␉␉␉␉break;␊
52␉␉␉␉}␊
53␉␉␉␉break;␊
54␊
55␉␉␉default:␊
56␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
57␉␉␉␉break;␊
58␉␉}␊
59␉}␊
60␉else␊
61␉{␊
62␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
63␉}␊
64␊
65␉return true;␊
66}␊
67␊
68bool getProcessorInformationMaximumClock(returnType *value)␊
69{␊
70␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
71␉return true;␊
72}␊
73␊
74bool getSMBOemProcessorBusSpeed(returnType *value)␊
75{␊
76␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
77␉{␊
78␉␉switch (Platform.CPU.Family)␊
79␉␉{␊
80␉␉␉case 0x06:␊
81␉␉␉␉switch (Platform.CPU.Model)␊
82␉␉␉␉{␊
83␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
84␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
85␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
86␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
87␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
88␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
89␉␉␉␉␉␉return false;␊
90␊
91␉␉␉␉␉case 0x19:␊
92␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
93␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
94␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
95␉␉␉␉␉case CPUID_MODEL_DALES:␉// Intel Core i3, i5 LGA1156 (32nm)␊
96␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
97␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
98␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
99␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
100␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
101␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
102␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
103␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
104␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
105␉␉␉␉␉{␊
106␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
107␉␉␉␉␉␉int nhm_bus = 0x3F;␊
108␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
109␉␉␉␉␉␉unsigned long did, vid;␊
110␉␉␉␉␉␉unsigned int i;␊
111␉␉␉␉␉␉␊
112␉␉␉␉␉␉// Nehalem supports Scrubbing␊
113␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
114␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
115␉␉␉␉␉␉{␊
116␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
117␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
118␉␉␉␉␉␉␉vid &= 0xFFFF;␊
119␉␉␉␉␉␉␉did &= 0xFF00;␊
120␉␉␉␉␉␉␉␊
121␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
122␉␉␉␉␉␉␉{␊
123␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
124␉␉␉␉␉␉␉}␊
125␉␉␉␉␉␉}␊
126␊
127␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
128␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
129␉␉␉␉␉␉qpimult &= 0x7F;␊
130␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
131␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
132␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
133␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
134␉␉␉␉␉␉{␊
135␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
136␉␉␉␉␉␉}␊
137␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
138␉␉␉␉␉␉value->word = qpibusspeed;␊
139␉␉␉␉␉␉return true;␊
140␉␉␉␉␉}␊
141␉␉␉␉␉break;␊
142␊
143␉␉␉␉␉default:␊
144␉␉␉␉␉␉break;␊
145␉␉␉␉}␊
146␉␉␉␉break;␊
147␊
148␉␉␉default:␊
149␉␉␉␉break;␊
150␉␉}␊
151␉}␊
152␊
153␉return false; //Unsupported CPU type␊
154}␊
155␊
156//bool getSMBOemPlatformFeature(returnType *value)␊
157//{␊
158// value->word = (uint64_t)(0x0000000000000001);␊
159// return true;␊
160//}␊
161␊
162uint16_t simpleGetSMBOemProcessorType(void)␊
163{␊
164␉if (Platform.CPU.NoCores >= 4)␊
165␉{␊
166␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊
167␉}␊
168␉else if (Platform.CPU.NoCores == 1)␊
169␉{␊
170␉␉return 0x201;␉// 513 - Core Duo␊
171␉};␊
172␉␊
173␉return 0x301;␉␉// 769 - Core 2 Duo␊
174}␊
175␊
176bool getSMBOemProcessorType(returnType *value)␊
177{␊
178␉static bool done = false;␊
179␊
180␉value->word = simpleGetSMBOemProcessorType();␊
181␊
182␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
183␉{␊
184␉␉if (!done)␊
185␉␉{␊
186␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
187␉␉␉done = true;␊
188␉␉}␊
189␊
190␉␉switch (Platform.CPU.Family)␊
191␉␉{␊
192␉␉␉case 0x0F:␊
193␉␉␉case 0x06:␊
194␊
195␉␉␉␉switch (Platform.CPU.Model)␊
196␉␉␉␉{␊
197␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
198␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
199␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
200␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
201␊
202␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
203␉␉␉␉␉␉{␊
204␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
205␉␉␉␉␉␉␉return true;␊
206␉␉␉␉␉␉}␊
207␊
208␉␉␉␉␉␉return true;␊
209␊
210␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
211␉␉␉␉␉case CPUID_MODEL_CONROE:␊
212␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
213␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
214␉␉␉␉␉␉return true;␊
215␊
216␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
217␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
218␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
219␊
220␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
221␉␉␉␉␉␉{␊
222␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
223␉␉␉␉␉␉␉return true;␊
224␉␉␉␉␉␉}␊
225␊
226␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
227␉␉␉␉␉␉{␊
228␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
229␉␉␉␉␉␉␉return true;␊
230␉␉␉␉␉␉}␊
231␉␉␉␉␉␉else␊
232␉␉␉␉␉␉{␊
233␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
234␉␉␉␉␉␉␉return true;␊
235␉␉␉␉␉␉}␊
236␊
237␉␉␉␉␉␉return true;␊
238␊
239␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
240␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
241␊
242␉␉␉␉␉␉return true;␊
243␊
244␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
245␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
246␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
247␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
248␊
249␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
250␉␉␉␉␉␉{␊
251␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
252␉␉␉␉␉␉␉return true;␊
253␉␉␉␉␉␉}␊
254␊
255␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
256␉␉␉␉␉␉{␊
257␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
258␉␉␉␉␉␉␉return true;␊
259␉␉␉␉␉␉}␊
260␊
261␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
262␉␉␉␉␉␉{␊
263␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
264␉␉␉␉␉␉␉return true;␊
265␉␉␉␉␉␉}␊
266␊
267␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
268␉␉␉␉␉␉{␊
269␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
270␉␉␉␉␉␉␉return true;␊
271␉␉␉␉␉␉}␊
272␊
273␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
274␉␉␉␉␉␉{␊
275␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
276␉␉␉␉␉␉␉return true;␊
277␉␉␉␉␉␉}␊
278␊
279␉␉␉␉␉␉return true;␊
280␊
281␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
282␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
283␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
284␊
285␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
286␉␉␉␉␉␉{␊
287␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
288␉␉␉␉␉␉␉return true;␊
289␉␉␉␉␉␉}␊
290␊
291␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
292␉␉␉␉␉␉{␊
293␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
294␉␉␉␉␉␉␉return true;␊
295␉␉␉␉␉␉}␊
296␊
297␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
298␉␉␉␉␉␉{␊
299␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
300␉␉␉␉␉␉␉return true;␊
301␉␉␉␉␉␉}␊
302␊
303␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
304␉␉␉␉␉␉{␊
305␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
306␉␉␉␉␉␉␉return true;␊
307␉␉␉␉␉␉}␊
308␊
309␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
310␉␉␉␉␉␉{␊
311␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
312␉␉␉␉␉␉␉return true;␊
313␉␉␉␉␉␉}␊
314␊
315␉␉␉␉␉␉return true;␊
316␊
317␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
318␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
319␊
320␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
321␉␉␉␉␉␉{␊
322␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
323␉␉␉␉␉␉␉return true;␊
324␉␉␉␉␉␉}␊
325␊
326␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
327␉␉␉␉␉␉{␊
328␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
329␉␉␉␉␉␉␉return true;␊
330␉␉␉␉␉␉}␊
331␊
332␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
333␉␉␉␉␉␉{␊
334␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
335␉␉␉␉␉␉␉return true;␊
336␉␉␉␉␉␉}␊
337␊
338␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
339␉␉␉␉␉␉{␊
340␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
341␉␉␉␉␉␉␉return true;␊
342␉␉␉␉␉␉}␊
343␊
344␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
345␉␉␉␉␉␉{␊
346␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
347␉␉␉␉␉␉␉return true;␊
348␉␉␉␉␉␉}␊
349␊
350␉␉␉␉␉␉return true;␊
351␊
352␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
353␊
354␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
355␉␉␉␉␉␉{␊
356␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
357␉␉␉␉␉␉␉return true;␊
358␉␉␉␉␉␉}␊
359␊
360␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
361␉␉␉␉␉␉{␊
362␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
363␉␉␉␉␉␉␉return true;␊
364␉␉␉␉␉␉}␊
365␊
366␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
367␉␉␉␉␉␉{␊
368␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
369␉␉␉␉␉␉␉return true;␊
370␉␉␉␉␉␉}␊
371␊
372␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
373␉␉␉␉␉␉{␊
374␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
375␉␉␉␉␉␉␉return true;␊
376␉␉␉␉␉␉}␊
377␊
378␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
379␉␉␉␉␉␉{␊
380␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
381␉␉␉␉␉␉␉return true;␊
382␉␉␉␉␉␉}␊
383␊
384␉␉␉␉␉␉return true;␊
385␊
386␉␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␉␉// 0x3D -␊
387␉␉␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␉␉// 0x5E␊
388␊
389␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊
390␉␉␉␉␉␉{␊
391␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊
392␉␉␉␉␉␉␉return true;␊
393␉␉␉␉␉␉}␊
394␊
395␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
396␉␉␉␉␉␉{␊
397␉␉␉␉␉␉␉value->word = 0x906;␉␉// 2310 - Apple doesn't use it␊
398␉␉␉␉␉␉␉return true;␊
399␉␉␉␉␉␉}␊
400␊
401␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
402␉␉␉␉␉␉{␊
403␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊
404␉␉␉␉␉␉␉return true;␊
405␉␉␉␉␉␉}␊
406␊
407␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
408␉␉␉␉␉␉{␊
409␉␉␉␉␉␉␉value->word = 0x706;␉␉// 1798␊
410␉␉␉␉␉␉␉return true;␊
411␉␉␉␉␉␉}␊
412␊
413␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
414␉␉␉␉␉␉{␊
415␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊
416␉␉␉␉␉␉␉return true;␊
417␉␉␉␉␉␉}␊
418␊
419//␉␉␉␉␉␉value->word = 0x706;␉␉␉// 1798␊
420␉␉␉␉␉␉return true;␊
421␊
422␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
423␊
424␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
425␉␉␉␉␉␉return true;␊
426␊
427␉␉␉␉␉case CPUID_MODEL_ATOM_3700:␉␉␉// 0x37 -␊
428␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊
429␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
430␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
431␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46 -␊
432␉␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␉␉␉// 0x47␊
433␉␉␉␉␉case CPUID_MODEL_SKYLAKE:␊
434␉␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX:␊
435␊
436␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
437␉␉␉␉␉␉{␊
438␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
439␉␉␉␉␉␉␉return true;␊
440␉␉␉␉␉␉}␊
441␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
442␉␉␉␉␉␉{␊
443␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
444␉␉␉␉␉␉␉return true;␊
445␉␉␉␉␉␉}␊
446␊
447␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
448␉␉␉␉␉␉{␊
449␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
450␉␉␉␉␉␉␉return true;␊
451␉␉␉␉␉␉}␊
452␊
453␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
454␉␉␉␉␉␉{␊
455␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
456␉␉␉␉␉␉␉return true;␊
457␉␉␉␉␉␉}␊
458␊
459␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
460␉␉␉␉␉␉{␊
461␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
462␉␉␉␉␉␉␉return true;␊
463␉␉␉␉␉␉}␊
464␊
465␉␉␉␉␉␉return true;␊
466␊
467␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
468␊
469␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
470␉␉␉␉␉␉return true;␊
471␊
472␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
473␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
474␊
475␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
476␉␉␉␉␉␉return true;␊
477␊
478␉␉␉␉␉default:␊
479␊
480␉␉␉␉␉␉return true;␊
481␉␉␉␉␉␉break; // Unsupported CPU type␊
482␉␉␉␉}␊
483␉␉␉␉break;␊
484␊
485␉␉␉default:␊
486␉␉␉␉break;␊
487␉␉}␊
488␉}␊
489/*␊
490␉if (Platform.CPU.Vendor == CPUID_VENDOR_AMD) // AMD␊
491␉{␊
492␉␉value->word = simpleGetSMBOemProcessorType();␊
493␉␉return true;␊
494␉}␊
495*/␊
496␉return false;␊
497}␊
498␊
499bool getSMBMemoryDeviceMemoryType(returnType *value)␊
500{␊
501␉static int idx = -1;␊
502␉int␉map;␊
503␊
504␉idx++;␊
505␉if (idx < MAX_RAM_SLOTS)␊
506␉{␊
507␉␉map = Platform.DMI.DIMM[idx];␊
508␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
509␉␉{␊
510␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
511␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
512␉␉␉return true;␊
513␉␉}␊
514␉}␊
515␊
516␉return false;␊
517//␉value->byte = SMB_MEM_TYPE_DDR2;␊
518//␉return true;␊
519}␊
520␊
521bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
522{␊
523␉value->word = 0xFFFF;␊
524␉return true;␊
525}␊
526␊
527bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
528{␊
529␉static int idx = -1;␊
530␉int␉map;␊
531␊
532␉idx++;␊
533␉if (idx < MAX_RAM_SLOTS)␊
534␉{␊
535␉␉map = Platform.DMI.DIMM[idx];␊
536␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
537␉␉{␊
538␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
539␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
540␉␉␉return true;␊
541␉␉}␊
542␉}␊
543␊
544␉return false;␊
545//␉value->dword = 800;␊
546//␉return true;␊
547}␊
548␊
549bool getSMBMemoryDeviceManufacturer(returnType *value)␊
550{␊
551␉static int idx = -1;␊
552␉int␉map;␊
553␊
554␉idx++;␊
555␉if (idx < MAX_RAM_SLOTS)␊
556␉{␊
557␉␉map = Platform.DMI.DIMM[idx];␊
558␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
559␉␉{␊
560␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
561␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
562␉␉␉return true;␊
563␉␉}␊
564␉}␊
565␊
566␉if (!bootInfo->memDetect)␊
567␉{␊
568␉␉return false;␊
569␉}␊
570␉value->string = NOT_AVAILABLE;␊
571␉return true;␊
572}␊
573␊
574bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
575{␊
576␉static int idx = -1;␊
577␉int␉map;␊
578␊
579␉idx++;␊
580␊
581␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n", idx, MAX_RAM_SLOTS);␊
582␊
583␉if (idx < MAX_RAM_SLOTS)␊
584␉{␊
585␉␉map = Platform.DMI.DIMM[idx];␊
586␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
587␉␉{␊
588␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
589␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
590␉␉␉return true;␊
591␉␉}␊
592␉}␊
593␊
594␉if (!bootInfo->memDetect)␊
595␉{␊
596␉␉return false;␊
597␉}␊
598␉value->string = NOT_AVAILABLE;␊
599␉return true;␊
600}␊
601␊
602bool getSMBMemoryDevicePartNumber(returnType *value)␊
603{␊
604␉static int idx = -1;␊
605␉int␉map;␊
606␊
607␉idx++;␊
608␉if (idx < MAX_RAM_SLOTS)␊
609␉{␊
610␉␉map = Platform.DMI.DIMM[idx];␊
611␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
612␉␉{␊
613␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
614␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
615␉␉␉return true;␊
616␉␉}␊
617␉}␊
618␊
619␉if (!bootInfo->memDetect)␊
620␉{␊
621␉␉return false;␊
622␉}␊
623␉value->string = NOT_AVAILABLE;␊
624␉return true;␊
625}␊
626␊
627␊
628// getting smbios addr with fast compare ops, late checksum testing ...␊
629#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
630static const char * const SMTAG = "_SM_";␊
631static const char* const DMITAG = "_DMI_";␊
632␊
633SMBEntryPoint *getAddressOfSmbiosTable(void)␊
634{␊
635␉SMBEntryPoint␉*smbios;␊
636␉/*␊
637␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
638␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
639␉ */␊
640␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
641␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊
642␉{␊
643␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
644␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
645␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
646␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
647␉␉{␊
648␉␉␉return smbios;␊
649␉ }␊
650␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
651␉}␊
652␉printf("ERROR: Unable to find SMBIOS!\n");␊
653␉pause();␊
654␉return NULL;␊
655}␊
656␊
657

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