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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * Bronya: 2015 Improve AMD support, cleanup and bugfix␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "bootstruct.h"␊
11#include "boot.h"␊
12␊
13#ifndef DEBUG_CPU␊
14␉#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18␉#define DBG(x...)␉␉printf(x)␊
19#else␊
20␉#define DBG(x...)␊
21#endif␊
22␊
23␊
24#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
25␊
26clock_frequency_info_t gPEClockFrequencyInfo;␊
27␊
28static __unused uint64_t rdtsc32(void)␊
29{␊
30␉unsigned int lo,hi;␊
31␉__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));␊
32␉return ((uint64_t)hi << 32) | lo;␊
33}␊
34␊
35/*␊
36 * timeRDTSC()␊
37 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
38 * It pauses until the value is latched in the counter␊
39 * and then reads the time stamp counter to return to the caller.␊
40 */␊
41static uint64_t timeRDTSC(void)␊
42{␊
43␉int␉␉attempts = 0;␊
44␉uint32_t ␉latchTime;␊
45␉uint64_t␉saveTime,intermediate;␊
46␉unsigned int␉timerValue, lastValue;␊
47␉//boolean_t␉int_enabled;␊
48␉/*␊
49␉ * Table of correction factors to account for␊
50␉ *␉ - timer counter quantization errors, and␊
51␉ *␉ - undercounts 0..5␊
52␉ */␊
53#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
54#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
55#define SAMPLE_NSECS␉␉(2000000000LL)␊
56#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
57#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
58␉uint64_t␉scale[6] = {␊
59␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
60␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
61␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
62␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
63␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
64␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
65␉};␊
66␊
67␉//int_enabled = ml_set_interrupts_enabled(false);␊
68␊
69restart:␊
70␉if (attempts >= 3) // increase to up to 9 attempts.␊
71␉{␊
72␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
73␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
74␉}␊
75␉attempts++;␊
76␉enable_PIT2();␉␉// turn on PIT2␊
77␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
78␉latchTime = rdtsc32();␉// get the time stamp to time␊
79␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
80␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
81␉saveTime = rdtsc32();␉// now time how long a 20th a second is...␊
82␉get_PIT2(&lastValue);␊
83␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
84␉do {␊
85␉␉intermediate = get_PIT2(&timerValue);␊
86␉␉if (timerValue > lastValue)␊
87␉␉{␊
88␉␉␉// Timer wrapped␊
89␉␉␉set_PIT2(0);␊
90␉␉␉disable_PIT2();␊
91␉␉␉goto restart;␊
92␉␉}␊
93␉␉lastValue = timerValue;␊
94␉} while (timerValue > 5);␊
95␉//printf("timerValue␉ %d\n",timerValue);␊
96␉//printf("intermediate 0x%016llX\n",intermediate);␊
97␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
98 ␊
99␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
100␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
101␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
102␉intermediate += latchTime;␉␉// add on our save fudge␊
103␊
104␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
105␉disable_PIT2();␉␉␉// turn off PIT 2␊
106␊
107␉//ml_set_interrupts_enabled(int_enabled);␊
108␉return intermediate;␊
109}␊
110␊
111/*␊
112 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
113 */␊
114static uint64_t __unused measure_tsc_frequency(void)␊
115{␊
116␉uint64_t tscStart;␊
117␉uint64_t tscEnd;␊
118␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
119␉unsigned long pollCount;␊
120␉uint64_t retval = 0;␊
121␉int i;␊
122␊
123␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
124␉ * counter 2. We run this loop 3 times to make sure the cache␊
125␉ * is hot and we take the minimum delta from all of the runs.␊
126␉ * That is to say that we're biased towards measuring the minimum␊
127␉ * number of TSC ticks that occur while waiting for the timer to␊
128␉ * expire. That theoretically helps avoid inconsistencies when␊
129␉ * running under a VM if the TSC is not virtualized and the host␊
130␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
131␉ */␊
132␉for(i = 0; i < 10; ++i)␊
133␉{␊
134␉␉enable_PIT2();␊
135␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
136␉␉tscStart = rdtsc64();␊
137␉␉pollCount = poll_PIT2_gate();␊
138␉␉tscEnd = rdtsc64();␊
139␉␉/* The poll loop must have run at least a few times for accuracy */␊
140␉␉if (pollCount <= 1)␊
141␉␉{␊
142␉␉␉continue;␊
143␉␉}␊
144␉␉/* The TSC must increment at LEAST once every millisecond.␊
145␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
146␉␉ * be >= 30. Anything less and the processor is way too slow.␊
147␉␉ */␊
148␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
149␉␉{␊
150␉␉␉continue;␊
151␉␉}␊
152␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
153␉␉if ( (tscEnd - tscStart) < tscDelta )␊
154␉␉{␊
155␉␉␉tscDelta = tscEnd - tscStart;␊
156␉␉}␊
157␉}␊
158␉/* tscDelta is now the least number of TSC ticks the processor made in␊
159␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
160␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
161␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
162␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
163␉ * dividing by the milliseconds, we simply multiply by 1000.␊
164␉ */␊
165␊
166␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
167␉ * that we're going to multiply by 1000 first so we do need at least some␊
168␉ * arithmetic headroom. For now, 32-bit should be enough.␊
169␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
170␉ */␊
171␉if (tscDelta > (1ULL<<32))␊
172␉{␊
173␉␉retval = 0;␊
174␉}␊
175␉else␊
176␉{␊
177␉␉retval = tscDelta * 1000 / 30;␊
178␉}␊
179␉disable_PIT2();␊
180␉return retval;␊
181}␊
182␊
183static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
184#define RTC_FAST_DENOM␉0xFFFFFFFF␊
185␊
186inline static uint32_t␊
187create_mul_quant_GHZ(int shift, uint32_t quant)␊
188{␊
189␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
190}␊
191␊
192struct␉{␊
193␉mach_timespec_t␉␉␉calend_offset;␊
194␉boolean_t␉␉␉calend_is_set;␊
195␊
196␉int64_t␉␉␉␉calend_adjtotal;␊
197␉int32_t␉␉␉␉calend_adjdelta;␊
198␊
199␉uint32_t␉␉␉boottime;␊
200␊
201␉mach_timebase_info_data_t␉timebase_const;␊
202␊
203␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
204} rtclock;␊
205␊
206uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
207uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
208uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
209uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
210␊
211static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
212{␊
213␊
214␉if (cycles > (NSEC_PER_SEC/20))␊
215␉{␊
216␉␉// we can use just a "fast" multiply to get nanos␊
217␉␉rtc_quant_shift = 32;␊
218␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
219␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
220␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
221␉}␊
222␉else␊
223␉{␊
224␉␉rtc_quant_shift = 26;␊
225␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
226␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
227␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
228␉}␊
229␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
230␉// BUT we also want to calculate...␊
231␊
232␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
233 / UI_CPUFREQ_ROUNDING_FACTOR)␊
234␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
235␊
236␉/*␊
237␉ * Set current measured speed.␊
238␉ */␊
239␉if (cycles >= 0x100000000ULL)␊
240␉{␊
241␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
242␉}␊
243␉else␊
244␉{␊
245␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
246␉}␊
247␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
248␊
249␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
250␉return(rtc_cyc_per_sec);␊
251}␊
252␊
253// Bronya C1E fix␊
254static void post_startup_cpu_fixups(void)␊
255{␊
256␉/*␊
257␉ * Some AMD processors support C1E state. Entering this state will␊
258␉ * cause the local APIC timer to stop, which we can't deal with at␊
259␉ * this time.␊
260␉ */␊
261␊
262␉uint64_t reg;␊
263␉verbose("\tLooking to disable C1E if is already enabled by the BIOS:\n");␊
264␉reg = rdmsr64(MSR_AMD_INT_PENDING_CMP_HALT);␊
265␉/* Disable C1E state if it is enabled by the BIOS */␊
266␉if ((reg >> AMD_ACTONCMPHALT_SHIFT) & AMD_ACTONCMPHALT_MASK)␊
267␉{␊
268␉␉reg &= ~(AMD_ACTONCMPHALT_MASK << AMD_ACTONCMPHALT_SHIFT);␊
269␉␉wrmsr64(MSR_AMD_INT_PENDING_CMP_HALT, reg);␊
270␉␉verbose("\tC1E disabled!\n");␊
271␉}␊
272}␊
273␊
274/*␊
275 * Large memcpy() into MMIO space can take longer than 1 clock tick (55ms).␊
276 * The timer interrupt must remain responsive when updating VRAM so␊
277 * as not to miss timer interrupts during countdown().␊
278 *␊
279 * If interrupts are enabled, use normal memcpy.␊
280 *␊
281 * If interrupts are disabled, breaks memcpy down␊
282 * into 128K chunks, times itself and makes a bios␊
283 * real-mode call every 25 msec in order to service␊
284 * pending interrupts.␊
285 *␊
286 * -- zenith432, May 22nd, 2016␊
287 */␊
288void* memcpy_interruptible(void* dst, const void* src, size_t len)␊
289{␊
290␉uint64_t tscFreq, lastTsc;␊
291␉uint32_t eflags, threshold;␊
292␉ptrdiff_t offset;␊
293␉const size_t chunk = 131072U;␉// 128K␊
294␊
295␉if (len <= chunk)␊
296␉{␊
297␉␉/*␊
298␉␉ * Short memcpy - use normal.␊
299␉␉ */␊
300␉␉return memcpy(dst, src, len);␊
301␉}␊
302␊
303␉__asm__ volatile("pushfl; popl %0" : "=r"(eflags));␊
304␉if (eflags & 0x200U)␊
305␉{␊
306␉␉/*␊
307␉␉ * Interrupts are enabled - use normal memcpy.␊
308␉␉ */␊
309␉␉return memcpy(dst, src, len);␊
310␉}␊
311␊
312␉tscFreq = Platform.CPU.TSCFrequency;␊
313␉if ((uint32_t) (tscFreq >> 32))␊
314␉{␊
315␉␉/*␊
316␉␉ * If TSC Frequency >= 2 ** 32, use a default time threshold.␊
317␉␉ */␊
318␉␉threshold = (~0U) / 40U;␊
319␉}␊
320␉else if (!(uint32_t) tscFreq)␊
321␉{␊
322␉␉/*␊
323␉␉ * If early on and TSC Frequency hasn't been estimated yet,␊
324␉␉ * use normal memcpy.␊
325␉␉ */␊
326␉␉return memcpy(dst, src, len);␊
327␉}␊
328␉else␊
329␉{␊
330␉␉threshold = ((uint32_t) tscFreq) / 40U;␊
331␉}␊
332␊
333␉/*␊
334␉ * Do the work␊
335␉ */␊
336␉offset = 0;␊
337␉lastTsc = rdtsc64();␊
338␉do␊
339␉{␊
340␉␉(void) memcpy((char*) dst + offset, (const char*) src + offset, chunk);␊
341␉␉offset += (ptrdiff_t) chunk;␊
342␉␉len -= chunk;␊
343␉␉if ((rdtsc64() - lastTsc) < threshold)␊
344␉␉{␊
345␉␉␉continue;␊
346␉␉}␊
347␉␉(void) readKeyboardStatus();␉// visit real-mode␊
348␉␉lastTsc = rdtsc64();␊
349␉}␊
350␉while (len > chunk);␊
351␉if (len)␊
352␉{␊
353␉␉(void) memcpy((char*) dst + offset, (const char*) src + offset, len);␊
354␉}␊
355␉return dst;␊
356}␊
357␊
358/*␊
359 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
360 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
361 *␉ a max multi. (used to calculate the FSB freq.),␊
362 *␉ and a current multi. (used to calculate the CPU freq.)␊
363 * - busFrequency = tscFrequency / multi␊
364 * - cpuFrequency = busFrequency * multi␊
365 */␊
366␊
367/* Decimal powers: */␊
368#define kilo (1000ULL)␊
369#define Mega (kilo * kilo)␊
370#define Giga (kilo * Mega)␊
371#define Tera (kilo * Giga)␊
372#define Peta (kilo * Tera)␊
373␊
374#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
375␊
376void get_cpuid(PlatformInfo_t *p)␊
377{␊
378␊
379␉char␉␉str[128];␊
380␉uint32_t␉reg[4];␊
381␉char␉␉*s␉␉␉= 0;␊
382␊
383␊
384␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
385␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
386␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
387␊
388␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
389␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); // Get the max extended cpuid␊
390␊
391␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
392␉{␊
393␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
394␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
395␉}␊
396␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
397␉{␊
398␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
399␉}␊
400␊
401// ==============================================================␊
402␊
403␉/* get BrandString (if supported) */␊
404␉/* Copyright: from Apple's XNU cpuid.c */␊
405␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
406␉{␊
407␉␉bzero(str, 128);␊
408␉␉/*␊
409␉␉ * The BrandString 48 bytes (max), guaranteed to␊
410␉␉ * be NULL terminated.␊
411␉␉ */␊
412␉␉do_cpuid(0x80000002, reg);␊
413␉␉memcpy(&str[0], (char *)reg, 16);␊
414␉␉do_cpuid(0x80000003, reg);␊
415␉␉memcpy(&str[16], (char *)reg, 16);␊
416␉␉do_cpuid(0x80000004, reg);␊
417␉␉memcpy(&str[32], (char *)reg, 16);␊
418␉␉for (s = str; *s != '\0'; s++)␊
419␉␉{␊
420␉␉␉if (*s != ' ')␊
421␉␉␉{␊
422␉␉␉␉break;␊
423␉␉␉}␊
424␉␉}␊
425␉␉strlcpy(p->CPU.BrandString, s, 48);␊
426␊
427␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
428␉␉{␊
429␉␉␉/*␊
430␉␉␉ * This string means we have a firmware-programmable brand string,␊
431␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
432␉␉␉ */␊
433␉␉␉p->CPU.BrandString[0] = '\0';␊
434␉␉}␊
435␉␉p->CPU.BrandString[47] = '\0';␊
436//␉␉DBG("\tBrandstring = %s\n", p->CPU.BrandString);␊
437␉}␊
438␊
439// ==============================================================␊
440␊
441␉switch(p->CPU.BrandString[0])␊
442␉{␊
443␉␉case 'A':␊
444␉␉␉/* AMD Processors */␊
445␉␉␉// The cache information is only in ecx and edx so only save␊
446␉␉␉// those registers␊
447␊
448␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
449␊
450␉␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
451␉␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
452␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
453␊
454␉␉␉break;␊
455␊
456␉␉case 'G':␊
457␉␉␉/* Intel Processors */␊
458␉␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); // Cache Index for Inte␊
459␊
460␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
461␉␉␉{␊
462␉␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
463␉␉␉}␊
464␊
465␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
466␉␉␉{␊
467␉␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
468␉␉␉}␊
469␊
470␉␉␉break;␊
471␉}␊
472}␊
473void scan_cpu(PlatformInfo_t *p)␊
474{␊
475␉verbose("[ CPU INFO ]\n");␊
476␉get_cpuid(p);␊
477␊
478␉uint64_t␉busFCvtt2n;␊
479␉uint64_t␉tscFCvtt2n;␊
480␉uint64_t␉tscFreq␉␉␉= 0;␊
481␉uint64_t␉busFrequency␉␉= 0;␊
482␉uint64_t␉cpuFrequency␉␉= 0;␊
483␉uint64_t␉msr␉␉␉= 0;␊
484␉uint64_t␉flex_ratio␉␉= 0;␊
485␉uint64_t␉cpuid_features;␊
486␊
487␉uint32_t␉max_ratio␉␉= 0;␊
488␉uint32_t␉min_ratio␉␉= 0;␊
489␉uint32_t␉reg[4];␊
490␉uint32_t␉cores_per_package␉= 0;␊
491␉uint32_t␉logical_per_package␉= 1;␊
492␉uint32_t␉threads_per_core␉= 1;␊
493␊
494␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
495␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
496␉uint8_t␉␉currdiv␉␉␉= 0;␊
497␉uint8_t␉␉currcoef␉␉= 0;␊
498␉uint8_t␉␉maxdiv␉␉␉= 0;␊
499␉uint8_t␉␉maxcoef␉␉␉= 0;␊
500␉uint8_t␉␉pic0_mask;␊
501␉uint8_t␉␉cpuMultN2␉␉= 0;␊
502␊
503␉const char␉*newratio;␊
504␊
505␉int␉␉len␉␉␉= 0;␊
506␉int␉␉myfsb␉␉␉= 0;␊
507␉int␉␉i␉␉␉= 0;␊
508␊
509␊
510/* http://www.flounder.com/cpuid_explorer2.htm␊
511 EAX (Intel):␊
512 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
513 +--------+----------------+--------+----+----+--------+--------+--------+␊
514 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
515 +--------+----------------+--------+----+----+--------+--------+--------+␊
516␊
517 EAX (AMD):␊
518 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
519 +--------+----------------+--------+----+----+--------+--------+--------+␊
520 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
521 +--------+----------------+--------+----+----+--------+--------+--------+␊
522*/␊
523␉///////////////////-- MaxFn,Vendor --////////////////////////␊
524␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
525␊
526␉///////////////////-- Signature, stepping, features -- //////␊
527␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊
528␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
529␉{␊
530␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
531␉}␊
532␉else␊
533␉{␊
534␉␉logical_per_package = 1;␊
535␉}␊
536␊
537␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
538␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
539␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
540␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
541␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
542␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
543␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
544␊
545␉if (p->CPU.Family == 0x0f)␊
546␉{␊
547␉␉p->CPU.Family += p->CPU.ExtFamily;␊
548␉}␊
549␊
550␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
551␉{␊
552␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
553␉}␊
554␊
555␉switch (p->CPU.Vendor)␊
556␉{␊
557␉␉case CPUID_VENDOR_INTEL:␊
558␉␉{␊
559␉␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
560␉␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
561␉␉␉{␊
562␉␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
563␉␉␉␉{␊
564␉␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
565␉␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
566␉␉␉␉␉{␊
567␉␉␉␉␉␉break;␊
568␉␉␉␉␉}␊
569␉␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
570␉␉␉␉}␊
571␉␉␉}␊
572␊
573␉␉␉if (i > 0)␊
574␉␉␉{␊
575␉␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
576␉␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
577␉␉␉}␊
578␊
579␉␉␉if (cores_per_package == 0)␊
580␉␉␉{␊
581␉␉␉␉cores_per_package = 1;␊
582␉␉␉}␊
583␊
584␉␉␉switch (p->CPU.Model)␊
585␉␉␉{␊
586␉␉␉␉case CPUID_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)␊
587␉␉␉␉case CPUID_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)␊
588␉␉␉␉case CPUID_MODEL_CLARKDALE: // Intel Core i3, i5, i7 LGA1156 (32nm)␊
589␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
590␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
591␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
592␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
593␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
594␉␉␉␉case CPUID_MODEL_HASWELL:␊
595␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
596␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊
597␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
598␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
599␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊
600␉␉␉␉case CPUID_MODEL_BRODWELL_SVR:␊
601␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊
602␉␉␉␉//case CPUID_MODEL_:␊
603␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊
604␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
605␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
606␉␉␉␉␉break;␊
607␊
608␉␉␉␉case CPUID_MODEL_DALES:␊
609␉␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊
610␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
611␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
612␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
613␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
614␉␉␉␉␉break;␊
615␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
616␉␉␉␉case CPUID_MODEL_ATOM:␊
617␉␉␉␉␉p->CPU.NoCores␉␉= 2;␊
618␉␉␉␉␉p->CPU.NoThreads␉= 2;␊
619␉␉␉␉␉break;␊
620␉␉␉␉default:␊
621␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
622␉␉␉␉␉break;␊
623␉␉␉}␊
624␊
625␉␉␉if (p->CPU.NoCores == 0)␊
626␉␉␉{␊
627␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
628␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
629␉␉␉}␊
630␊
631␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊
632␉␉␉// workaround for N270. I don't know why it detected wrong␊
633␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
634␉␉␉{␊
635␉␉␉␉p->CPU.NoCores␉␉= 1;␊
636␉␉␉␉p->CPU.NoThreads␉= 2;␊
637␉␉␉}␊
638␊
639␊
640␉␉␉// workaround for Xeon Harpertown and Yorkfield␊
641␉␉␉if ((p->CPU.Model == CPUID_MODEL_PENRYN) &&␊
642␉␉␉␉(p->CPU.NoCores␉== 0))␊
643␉␉␉{␊
644␉␉␉␉if ((strstr(p->CPU.BrandString, "X54")) ||␊
645␉␉␉␉␉(strstr(p->CPU.BrandString, "E54")) ||␊
646␉␉␉␉␉(strstr(p->CPU.BrandString, "W35")) ||␊
647␉␉␉␉␉(strstr(p->CPU.BrandString, "X34")) ||␊
648␉␉␉␉␉(strstr(p->CPU.BrandString, "X33")) ||␊
649␉␉␉␉␉(strstr(p->CPU.BrandString, "L33")) ||␊
650␉␉␉␉␉(strstr(p->CPU.BrandString, "X32")) ||␊
651␉␉␉␉␉(strstr(p->CPU.BrandString, "L3426")) ||␊
652␉␉␉␉␉(strstr(p->CPU.BrandString, "L54")))␊
653␉␉␉␉{␊
654␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
655␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
656␉␉␉␉} else if (strstr(p->CPU.BrandString, "W36")) {␊
657␉␉␉␉␉p->CPU.NoCores␉␉= 6;␊
658␉␉␉␉␉p->CPU.NoThreads␉= 6;␊
659␉␉␉␉} else { //other Penryn and Wolfdale␊
660␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
661␉␉␉␉␉p->CPU.NoThreads␉= 0;␊
662␉␉␉␉}␊
663␉␉␉}␊
664␊
665␉␉␉// workaround for Quad␊
666␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
667␉␉␉{␊
668␉␉␉␉p->CPU.NoCores␉␉= 4;␊
669␉␉␉␉p->CPU.NoThreads␉= 4;␊
670␉␉␉}␊
671␉␉}␊
672␊
673␉␉break;␊
674␊
675␉␉case CPUID_VENDOR_AMD:␊
676␉␉{␊
677␉␉␉post_startup_cpu_fixups();␊
678␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
679␉␉␉threads_per_core = cores_per_package;␊
680␊
681␉␉␉if (cores_per_package == 0)␊
682␉␉␉{␊
683␉␉␉␉cores_per_package = 1;␊
684␉␉␉}␊
685␊
686␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
687␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
688␊
689␉␉␉if (p->CPU.NoCores == 0)␊
690␉␉␉{␊
691␉␉␉␉p->CPU.NoCores = 1;␊
692␉␉␉␉p->CPU.NoThreads␉= 1;␊
693␉␉␉}␊
694␉␉}␊
695␉␉break;␊
696␊
697␉␉default :␊
698␉␉␉stop("Unsupported CPU detected! System halted.");␊
699␉}␊
700␊
701␉/* setup features */␊
702␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
703␉{␊
704␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
705␉}␊
706␊
707␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
708␉{␊
709␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
710␉}␊
711␊
712␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
713␉{␊
714␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
715␉}␊
716␊
717␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
718␉{␊
719␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
720␉}␊
721␊
722␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
723␉{␊
724␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
725␉}␊
726␊
727␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
728␉{␊
729␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
730␉}␊
731␊
732␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
733␉{␊
734␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
735␉}␊
736␊
737␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
738␉{␊
739␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
740␉}␊
741␊
742␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
743␉{␊
744␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
745␉}␊
746␊
747␉pic0_mask = inb(0x21U);␊
748␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
749␊
750␉uint64_t cycles;␊
751␉cycles = timeRDTSC();␊
752␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
753␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
754␉// if usual method failed␊
755␉if ( tscFreq < 1000 )␉//TEST␊
756␉{␊
757␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
758␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
759␉}␊
760␊
761␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
762␉{␊
763␉␉int intelCPU = p->CPU.Model;␊
764␉␉if (p->CPU.Family == 0x06)␊
765␉␉{␊
766␉␉␉/* Nehalem CPU model */␊
767␉␉␉switch (p->CPU.Model)␊
768␉␉␉{␊
769␉␉␉␉case CPUID_MODEL_NEHALEM:␊
770␉␉␉␉case CPUID_MODEL_FIELDS:␊
771␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
772␉␉␉␉case CPUID_MODEL_DALES:␊
773␉␉␉␉case CPUID_MODEL_WESTMERE:␊
774␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
775␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
776/* --------------------------------------------------------- */␊
777␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
778␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
779␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
780␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
781␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
782␉␉␉␉case CPUID_MODEL_HASWELL:␊
783␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
784␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
785␊
786␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
787␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
788␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊
789␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊
790/* --------------------------------------------------------- */␊
791␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
792␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
793␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
794␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
795␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
796␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
797␉␉␉␉␉if (bitfield(msr, 16, 16))␊
798␉␉␉␉␉{␊
799␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
800␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
801␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
802␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
803␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
804␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
805␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
806␉␉␉␉␉␉// is inadvertently set to 0.␊
807␊
808␉␉␉␉␉␉if (flex_ratio == 0)␊
809␉␉␉␉␉␉{␊
810␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
811␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
812␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
813␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
814␉␉␉␉␉␉}␊
815␉␉␉␉␉␉else␊
816␉␉␉␉␉␉{␊
817␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
818␉␉␉␉␉␉␉{␊
819␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
820␉␉␉␉␉␉␉}␊
821␉␉␉␉␉␉}␊
822␉␉␉␉␉}␊
823␊
824␉␉␉␉␉if (bus_ratio_max)␊
825␉␉␉␉␉{␊
826␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
827␉␉␉␉␉}␊
828␊
829␉␉␉␉␉//valv: Turbo Ratio Limit␊
830␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
831␉␉␉␉␉{␊
832␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
833␊
834␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
835␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
836␉␉␉␉␉}␊
837␉␉␉␉␉else␊
838␉␉␉␉␉{␊
839␉␉␉␉␉␉cpuFrequency = tscFreq;␊
840␉␉␉␉␉}␊
841␊
842␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
843␉␉␉␉␉{␊
844␉␉␉␉␉␉max_ratio = atoi(newratio);␊
845␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
846␉␉␉␉␉␉if (len >= 3)␊
847␉␉␉␉␉␉{␊
848␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
849␉␉␉␉␉␉}␊
850␊
851␉␉␉␉␉␉verbose("\tBus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
852␊
853␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
854␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
855␉␉␉␉␉␉{␊
856␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
857␉␉␉␉␉␉␉if (len >= 3)␊
858␉␉␉␉␉␉␉{␊
859␉␉␉␉␉␉␉␉maxdiv = 1;␊
860␉␉␉␉␉␉␉}␊
861␉␉␉␉␉␉␉else␊
862␉␉␉␉␉␉␉{␊
863␉␉␉␉␉␉␉␉maxdiv = 0;␊
864␉␉␉␉␉␉␉}␊
865␉␉␉␉␉␉}␊
866␉␉␉␉␉␉else␊
867␉␉␉␉␉␉{␊
868␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
869␉␉␉␉␉␉}␊
870␉␉␉␉␉}␊
871␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
872␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
873␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
874␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
875␊
876␉␉␉␉myfsb = busFrequency / 1000000;␊
877␉␉␉␉verbose("\tSticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
878␉␉␉␉currcoef = bus_ratio_max;␊
879␊
880␉␉␉␉break;␊
881␊
882␉␉␉default:␊
883␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
884␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
885␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
886␉␉␉␉// Non-integer bus ratio for the max-multi␊
887␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
888␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
889␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
890␊
891␉␉␉␉// This will always be model >= 3␊
892␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
893␉␉␉␉{␊
894␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
895␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
896␉␉␉␉}␊
897␉␉␉␉else␊
898␉␉␉␉{␊
899␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
900␉␉␉␉␉// XXX␊
901␉␉␉␉␉maxcoef = currcoef;␊
902␉␉␉␉}␊
903␊
904␉␉␉␉if (!currcoef)␊
905␉␉␉␉{␊
906␉␉␉␉␉currcoef = maxcoef;␊
907␉␉␉␉}␊
908␊
909␉␉␉␉if (maxcoef)␊
910␉␉␉␉{␊
911␉␉␉␉␉if (maxdiv)␊
912␉␉␉␉␉{␊
913␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
914␉␉␉␉␉}␊
915␉␉␉␉␉else␊
916␉␉␉␉␉{␊
917␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
918␉␉␉␉␉}␊
919␊
920␉␉␉␉␉if (currdiv)␊
921␉␉␉␉␉{␊
922␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
923␉␉␉␉␉}␊
924␉␉␉␉␉else␊
925␉␉␉␉␉{␊
926␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
927␉␉␉␉␉}␊
928␊
929␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
930␉␉␉␉}␊
931␉␉␉␉break;␊
932␉␉␉}␊
933␉␉}␊
934␉␉// Mobile CPU␊
935␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
936␉␉{␊
937␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
938␉␉}␊
939␉}␊
940␊
941␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
942␉{␊
943␉␉switch(p->CPU.Family)␊
944␉␉{␊
945␉␉␉case 0xF: /* K8 */␊
946␉␉␉{␊
947␉␉␉␉uint64_t fidvid = 0;␊
948␉␉␉␉uint64_t cpuMult;␊
949␉␉␉␉uint64_t fid;␊
950␊
951␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
952␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
953␊
954␉␉␉␉cpuMult = (fid + 8) / 2;␊
955␉␉␉␉currcoef = cpuMult;␊
956␊
957␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
958␉␉␉␉currdiv = cpuMultN2;␊
959␉␉␉␉/****** Addon END ******/␊
960␉␉␉}␊
961␉␉␉␉break;␊
962␊
963␉␉␉case 0x10: /*** AMD Family 10h ***/␊
964␉␉␉{␊
965␉␉␉␉uint64_t cofvid = 0;␊
966␉␉␉␉uint64_t cpuMult;␊
967␉␉␉␉uint64_t divisor = 0;␊
968␉␉␉␉uint64_t did;␊
969␉␉␉␉uint64_t fid;␊
970␊
971␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
972␉␉␉␉did = bitfield(cofvid, 8, 6);␊
973␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
974␉␉␉␉if (did == 0) divisor = 2;␊
975␉␉␉␉else if (did == 1) divisor = 4;␊
976␉␉␉␉else if (did == 2) divisor = 8;␊
977␉␉␉␉else if (did == 3) divisor = 16;␊
978␉␉␉␉else if (did == 4) divisor = 32;␊
979␊
980␉␉␉␉cpuMult = (fid + 16) / divisor;␊
981␉␉␉␉currcoef = cpuMult;␊
982␊
983␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
984␉␉␉␉currdiv = cpuMultN2;␊
985␊
986␉␉␉␉/****** Addon END ******/␊
987␉␉␉}␊
988␉␉␉break;␊
989␊
990␉␉␉case 0x11: /*** AMD Family 11h ***/␊
991␉␉␉{␊
992␉␉␉␉uint64_t cofvid = 0;␊
993␉␉␉␉uint64_t cpuMult;␊
994␉␉␉␉uint64_t divisor = 0;␊
995␉␉␉␉uint64_t did;␊
996␉␉␉␉uint64_t fid;␊
997␊
998␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
999␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1000␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1001␉␉␉␉if (did == 0) divisor = 2;␊
1002␉␉␉␉else if (did == 1) divisor = 4;␊
1003␉␉␉␉else if (did == 2) divisor = 8;␊
1004␉␉␉␉else if (did == 3) divisor = 16;␊
1005␉␉␉␉else if (did == 4) divisor = 32;␊
1006␊
1007␉␉␉␉cpuMult = (fid + 8) / divisor;␊
1008␉␉␉␉currcoef = cpuMult;␊
1009␊
1010␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1011␉␉␉␉currdiv = cpuMultN2;␊
1012␊
1013␉␉␉␉/****** Addon END ******/␊
1014␉␉␉}␊
1015 break;␊
1016␊
1017␉␉␉case 0x12: /*** AMD Family 12h ***/␊
1018␉␉␉{␊
1019␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
1020␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
1021␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
1022␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1023␊
1024␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
1025␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
1026␉␉␉␉uint64_t divisor;␊
1027␉␉␉␉switch (CpuDid)␊
1028␉␉␉␉{␊
1029␉␉␉␉␉case 0: divisor = 1; break;␊
1030␉␉␉␉␉case 1: divisor = (3/2); break;␊
1031␉␉␉␉␉case 2: divisor = 2; break;␊
1032␉␉␉␉␉case 3: divisor = 3; break;␊
1033␉␉␉␉␉case 4: divisor = 4; break;␊
1034␉␉␉␉␉case 5: divisor = 6; break;␊
1035␉␉␉␉␉case 6: divisor = 8; break;␊
1036␉␉␉␉␉case 7: divisor = 12; break;␊
1037␉␉␉␉␉case 8: divisor = 16; break;␊
1038␉␉␉␉␉default: divisor = 1; break;␊
1039␉␉␉␉}␊
1040␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
1041␊
1042␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
1043␉␉␉␉currdiv = cpuMultN2;␊
1044␊
1045␉␉␉}␊
1046␉␉␉␉break;␊
1047␊
1048␉␉␉case 0x14: /* K14 */␊
1049␊
1050␉␉␉{␊
1051␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
1052␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
1053␉␉␉␉uint64_t prfsts;␊
1054␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1055␊
1056␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
1057␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
1058␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
1059␊
1060␉␉␉␉uint64_t frequencyId = 0x10;␊
1061␉␉␉␉currcoef = (frequencyId + 0x10) /␊
1062␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
1063␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
1064␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
1065␊
1066␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
1067␉␉␉␉currdiv = cpuMultN2;␊
1068␉␉␉}␊
1069␊
1070␉␉␉␉break;␊
1071␊
1072␉␉␉case 0x15: /*** AMD Family 15h ***/␊
1073␉␉␉case 0x06: /*** AMD Family 06h ***/␊
1074␉␉␉{␊
1075␊
1076␉␉␉␉uint64_t cofvid = 0;␊
1077␉␉␉␉uint64_t cpuMult;␊
1078␉␉␉␉uint64_t divisor = 0;␊
1079␉␉␉␉uint64_t did;␊
1080␉␉␉␉uint64_t fid;␊
1081␊
1082␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1083␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1084␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1085␉␉␉␉if (did == 0) divisor = 2;␊
1086␉␉␉␉else if (did == 1) divisor = 4;␊
1087␉␉␉␉else if (did == 2) divisor = 8;␊
1088␉␉␉␉else if (did == 3) divisor = 16;␊
1089␉␉␉␉else if (did == 4) divisor = 32;␊
1090␊
1091␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1092␉␉␉␉currcoef = cpuMult;␊
1093␊
1094␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1095␉␉␉␉currdiv = cpuMultN2;␊
1096␉␉␉}␊
1097␉␉␉␉break;␊
1098␊
1099␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
1100␉␉␉{␊
1101␉␉␉␉uint64_t cofvid = 0;␊
1102␉␉␉␉uint64_t cpuMult;␊
1103␉␉␉␉uint64_t divisor = 0;␊
1104␉␉␉␉uint64_t did;␊
1105␉␉␉␉uint64_t fid;␊
1106␊
1107␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1108␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1109␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1110␉␉␉␉if (did == 0) divisor = 1;␊
1111␉␉␉␉else if (did == 1) divisor = 2;␊
1112␉␉␉␉else if (did == 2) divisor = 4;␊
1113␉␉␉␉else if (did == 3) divisor = 8;␊
1114␉␉␉␉else if (did == 4) divisor = 16;␊
1115␊
1116␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1117␉␉␉␉currcoef = cpuMult;␊
1118␊
1119␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1120␉␉␉␉currdiv = cpuMultN2;␊
1121␉␉␉␉/****** Addon END ******/␊
1122␉␉␉}␊
1123␉␉␉␉break;␊
1124␊
1125␉␉␉default:␊
1126␉␉␉{␊
1127␉␉␉␉typedef unsigned long long vlong;␊
1128␉␉␉␉uint64_t prfsts;␊
1129␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1130␉␉␉␉uint64_t r;␊
1131␉␉␉␉vlong hz;␊
1132␉␉␉␉r = (prfsts>>6) & 0x07;␊
1133␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
1134␊
1135␉␉␉␉currcoef = hz / (200 * Mega);␊
1136␉␉␉}␊
1137␉␉}␊
1138␊
1139␉␉if (currcoef)␊
1140␉␉{␊
1141␉␉␉if (currdiv)␊
1142␉␉␉{␊
1143␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
1144␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1145␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
1146␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1147␊
1148␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
1149␉␉␉}␊
1150␉␉␉else␊
1151␉␉␉{␊
1152␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1153␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1154␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1155␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1156␉␉␉␉DBG("%d\n", currcoef);␊
1157␉␉␉}␊
1158␉␉}␊
1159␉␉else if (!cpuFrequency)␊
1160␉␉{␊
1161␉␉␉cpuFrequency = tscFreq;␊
1162␉␉}␊
1163␉}␊
1164␊
1165#if 0␊
1166␉if (!busFrequency)␊
1167␉{␊
1168␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1169␉␉DBG("\tCPU: busFrequency = 0! using the default value for FSB!\n");␊
1170␉␉cpuFrequency = tscFreq;␊
1171␉}␊
1172␊
1173␉DBG("\tcpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1174␊
1175#endif␊
1176␊
1177␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
1178␊
1179␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1180␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1181␉p->CPU.CurrCoef = currcoef;␊
1182␉p->CPU.CurrDiv = currdiv;␊
1183␉p->CPU.TSCFrequency = tscFreq;␊
1184␉p->CPU.FSBFrequency = busFrequency;␊
1185␉p->CPU.CPUFrequency = cpuFrequency;␊
1186␊
1187␉// keep formatted with spaces instead of tabs␊
1188␊
1189␉DBG("\tCPUID Raw Values:\n");␊
1190␉for (i = 0; i < CPUID_MAX; i++)␊
1191␉{␊
1192␉␉DBG("\t%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1193␉}␊
1194␉DBG("\n");␊
1195␉DBG("\tBrand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1196␉DBG("\tVendor: 0x%X\n",␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1197␉DBG("\tFamily: 0x%X\n",␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1198␉DBG("\tExtFamily: 0x%X\n",␉p->CPU.ExtFamily);␊
1199␉DBG("\tSignature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1200␉/*switch (p->CPU.Type) {␊
1201␉␉case PT_OEM:␊
1202␉␉␉DBG("\tProcessor type: Intel Original OEM Processor\n");␊
1203␉␉␉break;␊
1204␉␉case PT_OD:␊
1205␉␉␉DBG("\tProcessor type: Intel Over Drive Processor\n");␊
1206␉␉␉break;␊
1207␉␉case PT_DUAL:␊
1208␉␉␉DBG("\tProcessor type: Intel Dual Processor\n");␊
1209␉␉␉break;␊
1210␉␉case PT_RES:␊
1211␉␉␉DBG("\tProcessor type: Intel Reserved\n");␊
1212␉␉␉break;␊
1213␉␉default:␊
1214␉␉␉break;␊
1215␉}*/␊
1216␉DBG("\tModel: 0x%X\n",␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1217␉DBG("\tExtModel: 0x%X\n",␉p->CPU.ExtModel);␊
1218␉DBG("\tStepping: 0x%X\n",␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1219␉DBG("\tMaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1220␉DBG("\tCurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1221␉DBG("\tMaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1222␉DBG("\tCurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1223␉DBG("\tTSCFreq: %dMHz\n",␉p->CPU.TSCFrequency / 1000000);␊
1224␉DBG("\tFSBFreq: %dMHz\n",␉p->CPU.FSBFrequency / 1000000);␊
1225␉DBG("\tCPUFreq: %dMHz\n",␉p->CPU.CPUFrequency / 1000000);␊
1226␉DBG("\tCores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1227␉DBG("\tLogical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1228␉DBG("\tFeatures: 0x%08x\n",␉p->CPU.Features);␊
1229␊
1230␉verbose("\n");␊
1231#if DEBUG_CPU␊
1232␉pause();␊
1233#endif␊
1234}␊
1235

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