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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␉msglog(x)␊
19#endif␊
20␊
21#define XEON "Xeon"␊
22#define CORE_I3 "Core(TM) i3"␊
23#define CORE_I5 "Core(TM) i5"␊
24#define CORE_I7 "Core(TM) i7"␊
25␊
26bool getProcessorInformationExternalClock(returnType *value)␊
27{␊
28␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
29␉{␊
30␉␉switch (Platform.CPU.Family)␊
31␉␉{␊
32␉␉␉case 0x06:␊
33␉␉␉␉switch (Platform.CPU.Model)␊
34␉␉␉␉{␊
35␉␉␉␉␉// set external clock to 0 for SANDY␊
36␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
37␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
38␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
39␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊
40␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
41␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
42␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
43␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
44␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
45␊
46␉␉␉␉␉␉value->word = 0;␊
47␉␉␉␉␉␉break;␊
48␉␉␉␉␉default:␊
49␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
50␉␉␉␉␉␉break;␊
51␉␉␉␉}␊
52␉␉␉␉break;␊
53␊
54␉␉␉default:␊
55␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
56␉␉␉␉break;␊
57␉␉}␊
58␉}␊
59␉else␊
60␉{␊
61␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
62␉}␊
63␊
64␉return true;␊
65}␊
66␊
67bool getProcessorInformationMaximumClock(returnType *value)␊
68{␊
69␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
70␉return true;␊
71}␊
72␊
73bool getSMBOemProcessorBusSpeed(returnType *value)␊
74{␊
75␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
76␉{␊
77␉␉switch (Platform.CPU.Family)␊
78␉␉{␊
79␉␉␉case 0x06:␊
80␉␉␉␉switch (Platform.CPU.Model)␊
81␉␉␉␉{␊
82 /*␊
83␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
84␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
85␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
86␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
87␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
88␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
89␉␉␉␉␉␉return false;␊
90 */␊
91␉␉␉␉␉case 0x19:␊
92␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
93␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
94␉␉␉␉␉case CPUID_MODEL_DALES:␊
95␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
96␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
97␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
98␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
99␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
100␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
101␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
102␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊
103␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
104␉␉␉␉␉{␊
105␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
106␉␉␉␉␉␉int nhm_bus = 0x3F;␊
107␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
108␉␉␉␉␉␉unsigned long did, vid;␊
109␉␉␉␉␉␉unsigned int i;␊
110␉␉␉␉␉␉␊
111␉␉␉␉␉␉// Nehalem supports Scrubbing␊
112␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
113␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
114␉␉␉␉␉␉{␊
115␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
116␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
117␉␉␉␉␉␉␉vid &= 0xFFFF;␊
118␉␉␉␉␉␉␉did &= 0xFF00;␊
119␉␉␉␉␉␉␉␊
120␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
121␉␉␉␉␉␉␉{␊
122␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
123␉␉␉␉␉␉␉}␊
124␉␉␉␉␉␉}␊
125␊
126␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
127␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
128␉␉␉␉␉␉qpimult &= 0x7F;␊
129␉␉␉␉␉␉verbose("qpimult %d\n", qpimult);␊
130␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
131␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
132␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
133␉␉␉␉␉␉{␊
134␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
135␉␉␉␉␉␉}␊
136␉␉␉␉␉␉verbose("qpibusspeed %d\n", qpibusspeed);␊
137␉␉␉␉␉␉value->word = qpibusspeed;␊
138␉␉␉␉␉␉return true;␊
139␉␉␉␉␉}␊
140␉␉␉␉␉break;␊
141␊
142␉␉␉␉␉default:␊
143␉␉␉␉␉␉break;␊
144␉␉␉␉}␊
145␉␉␉␉break;␊
146␊
147␉␉␉default:␊
148␉␉␉␉break;␊
149␉␉}␊
150␉}␊
151␊
152␉return false; //Unsupported CPU type␊
153}␊
154␊
155uint16_t simpleGetSMBOemProcessorType(void)␊
156{␊
157␉if (Platform.CPU.NoCores >= 4)␊
158␉{␊
159␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊
160␉}␊
161␉else if (Platform.CPU.NoCores == 2)␊
162␉{␊
163␉␉return 0x301;␉// 513 - Core 2 Duo␊
164␉}␊
165␉␊
166␉return 0x201;␉␉// 769 - Core Duo␊
167}␊
168␊
169bool getSMBOemProcessorType(returnType *value)␊
170{␊
171␉static bool done = false;␊
172␊
173␉value->word = simpleGetSMBOemProcessorType();␊
174␊
175␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
176␉{␊
177␉␉if (!done)␊
178␉␉{␊
179␉␉␉//DBG("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
180␉␉␉done = true;␊
181␉␉}␊
182␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊
183␉␉switch (Platform.CPU.Family)␊
184␉␉{␊
185␉␉␉case 0x06:␊
186␉␉␉case 0x0F:␊
187␉␉␉␉switch (Platform.CPU.Model)␊
188␉␉␉␉{␊
189␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
190␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
191␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
192␉␉␉␉␉case CPUID_MODEL_IRWINDALE:␊
193␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
194␉␉␉␉␉␉{␊
195␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
196␉␉␉␉␉␉}␊
197␉␉␉␉␉␉return true;␊
198␊
199␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
200␉␉␉␉␉case CPUID_MODEL_CELERON:␊
201␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
202␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
203␉␉␉␉␉␉return true;␊
204␊
205␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
206␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
207␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
208␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
209␉␉␉␉␉␉{␊
210␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
211␉␉␉␉␉␉␉return true;␊
212␉␉␉␉␉␉}␊
213␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
214␉␉␉␉␉␉{␊
215␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo , Pentium Dual Core etc.␊
216␉␉␉␉␉␉}␊
217␉␉␉␉␉␉else␊
218␉␉␉␉␉␉{␊
219␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
220␉␉␉␉␉␉}␊
221␉␉␉␉␉␉return true;␊
222␊
223␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
224␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
225␉␉␉␉␉␉return true;␊
226␊
227␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
228␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
229␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
230␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
231␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
232␉␉␉␉␉␉{␊
233␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
234␉␉␉␉␉␉␉return true;␊
235␉␉␉␉␉␉}␊
236␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
237␉␉␉␉␉␉{␊
238␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
239␉␉␉␉␉␉␉return true;␊
240␉␉␉␉␉␉}␊
241␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
242␉␉␉␉␉␉{␊
243␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
244␉␉␉␉␉␉␉return true;␊
245␉␉␉␉␉␉}␊
246␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
247␉␉␉␉␉␉{␊
248␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
249␉␉␉␉␉␉␉return true;␊
250␉␉␉␉␉␉}␊
251␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
252␉␉␉␉␉␉{␊
253␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Pentium Dual Core as Core i3␊
254␉␉␉␉␉␉}␊
255␉␉␉␉␉␉return true;␊
256␊
257␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
258␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
259␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
260␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
261␉␉␉␉␉␉{␊
262␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
263␉␉␉␉␉␉␉return true;␊
264␉␉␉␉␉␉}␊
265␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
266␉␉␉␉␉␉{␊
267␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
268␉␉␉␉␉␉␉return true;␊
269␉␉␉␉␉␉}␊
270␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
271␉␉␉␉␉␉{␊
272␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
273␉␉␉␉␉␉␉return true;␊
274␉␉␉␉␉␉}␊
275␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
276␉␉␉␉␉␉{␊
277␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
278␉␉␉␉␉␉␉return true;␊
279␉␉␉␉␉␉}␊
280␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
281␉␉␉␉␉␉{␊
282␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Pentium Dual Core as Core i3␊
283␉␉␉␉␉␉}␊
284␉␉␉␉␉␉return true;␊
285␊
286␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
287␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
288␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
289␉␉␉␉␉␉{␊
290␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
291␉␉␉␉␉␉␉return true;␊
292␉␉␉␉␉␉}␊
293␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
294␉␉␉␉␉␉{␊
295␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
296␉␉␉␉␉␉␉return true;␊
297␉␉␉␉␉␉}␊
298␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
299␉␉␉␉␉␉{␊
300␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
301␉␉␉␉␉␉␉return true;␊
302␉␉␉␉␉␉}␊
303␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
304␉␉␉␉␉␉{␊
305␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
306␉␉␉␉␉␉␉return true;␊
307␉␉␉␉␉␉}␊
308␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
309␉␉␉␉␉␉{␊
310␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Pentium Dual Core as Core i3␊
311␉␉␉␉␉␉}␊
312␉␉␉␉␉␉return true;␊
313␊
314␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
315␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
316␉␉␉␉␉␉{␊
317␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
318␉␉␉␉␉␉␉return true;␊
319␉␉␉␉␉␉}␊
320␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
321␉␉␉␉␉␉{␊
322␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
323␉␉␉␉␉␉␉return true;␊
324␉␉␉␉␉␉}␊
325␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
326␉␉␉␉␉␉{␊
327␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
328␉␉␉␉␉␉␉return true;␊
329␉␉␉␉␉␉}␊
330␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
331␉␉␉␉␉␉{␊
332␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
333␉␉␉␉␉␉␉return true;␊
334␉␉␉␉␉␉}␊
335␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
336␉␉␉␉␉␉{␊
337␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Pentium Dual Core as Core i3␊
338␉␉␉␉␉␉}␊
339␉␉␉␉␉␉return true;␊
340␊
341␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␉␉// 0x3E - Mac Pro 6,1␊
342␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
343␉␉␉␉␉␉return true;␊
344␊
345␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊
346␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
347␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
348␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
349␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
350␉␉␉␉␉␉{␊
351␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
352␉␉␉␉␉␉␉return true;␊
353␉␉␉␉␉␉}␊
354␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
355␉␉␉␉␉␉{␊
356␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
357␉␉␉␉␉␉␉return true;␊
358␉␉␉␉␉␉}␊
359␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
360␉␉␉␉␉␉{␊
361␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
362␉␉␉␉␉␉␉return true;␊
363␉␉␉␉␉␉}␊
364␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
365␉␉␉␉␉␉{␊
366␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
367␉␉␉␉␉␉␉return true;␊
368␉␉␉␉␉␉}␊
369␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
370␉␉␉␉␉␉{␊
371␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Pentium Dual Core as Core i3␊
372␉␉␉␉␉␉}␊
373␉␉␉␉␉␉return true;␊
374␊
375␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
376␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
377␉␉␉␉␉␉return true;␊
378␊
379␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
380␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
381␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
382␉␉␉␉␉␉return true;␊
383␉␉␉␉␉default:␊
384␉␉␉␉␉␉break; // Unsupported CPU type␊
385␉␉␉␉}␊
386␉␉␉␉break;␊
387␊
388␉␉␉default:␊
389␉␉␉␉break;␊
390␉␉}␊
391␉}␊
392␉␊
393␉return false;␊
394}␊
395␊
396bool getSMBMemoryDeviceMemoryType(returnType *value)␊
397{␊
398␉static int idx = -1;␊
399␉int␉map;␊
400␊
401␉if (!bootInfo->memDetect)␊
402␉{␊
403␉␉return false;␊
404␉}␊
405␊
406␉idx++;␊
407␉if (idx < MAX_RAM_SLOTS)␊
408␉{␊
409␉␉map = Platform.DMI.DIMM[idx];␊
410␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
411␉␉{␊
412␉␉␉verbose("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
413␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
414␉␉␉return true;␊
415␉␉}␊
416␉}␊
417␊
418␉value->byte = 2; // means Unknown␊
419␉return true;␊
420//␉value->byte = SMB_MEM_TYPE_DDR2;␊
421//␉return true;␊
422}␊
423␊
424bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
425{␊
426␉value->word = 0xFFFF;␊
427␉return true;␊
428}␊
429␊
430bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
431{␊
432␉static int idx = -1;␊
433␉int␉map;␊
434␊
435␉if (!bootInfo->memDetect)␊
436␉{␊
437␉␉return false;␊
438␉}␊
439␊
440␉idx++;␊
441␉if (idx < MAX_RAM_SLOTS)␊
442␉{␊
443␉␉map = Platform.DMI.DIMM[idx];␊
444␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
445␉␉{␊
446␉␉␉verbose("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
447␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
448␉␉␉return true;␊
449␉␉}␊
450␉}␊
451␊
452␉value->dword = 0; // means Unknown␊
453␉return true;␊
454//␉value->dword = 800;␊
455//␉return true;␊
456}␊
457␊
458bool getSMBMemoryDeviceManufacturer(returnType *value)␊
459{␊
460␉static int idx = -1;␊
461␉int␉map;␊
462␊
463␉if (!bootInfo->memDetect)␊
464␉{␊
465␉␉return false;␊
466␉}␊
467␊
468␉idx++;␊
469␉if (idx < MAX_RAM_SLOTS)␊
470␉{␊
471␉␉map = Platform.DMI.DIMM[idx];␊
472␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
473␉␉{␊
474␉␉␉verbose("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
475␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
476␉␉␉return true;␊
477␉␉}␊
478␉}␊
479␊
480␉value->string = NOT_AVAILABLE;␊
481␉return true;␊
482}␊
483␊
484bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
485{␊
486␉static int idx = -1;␊
487␉int␉map;␊
488␊
489␉if (!bootInfo->memDetect)␊
490␉{␊
491␉␉return false;␊
492␉}␊
493␊
494␉idx++;␊
495␊
496␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
497␊
498␉if (idx < MAX_RAM_SLOTS)␊
499␉{␊
500␉␉map = Platform.DMI.DIMM[idx];␊
501␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
502␉␉{␊
503␉␉␉verbose("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
504␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
505␉␉␉return true;␊
506␉␉}␊
507␉}␊
508␊
509␉value->string = NOT_AVAILABLE;␊
510␉return true;␊
511}␊
512␊
513bool getSMBMemoryDevicePartNumber(returnType *value)␊
514{␊
515␉static int idx = -1;␊
516␉int␉map;␊
517␊
518␉if (!bootInfo->memDetect)␊
519␉{␊
520␉␉return false;␊
521␉}␊
522␊
523␉idx++;␊
524␉if (idx < MAX_RAM_SLOTS)␊
525␉{␊
526␉␉map = Platform.DMI.DIMM[idx];␊
527␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
528␉␉{␊
529␉␉␉verbose("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
530␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
531␉␉␉return true;␊
532␉␉}␊
533␉}␊
534␊
535␉value->string = NOT_AVAILABLE;␊
536␉return true;␊
537}␊
538␊
539␊
540// getting smbios addr with fast compare ops, late checksum testing ...␊
541#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
542static const char * const SMTAG = "_SM_";␊
543static const char* const DMITAG = "_DMI_";␊
544␊
545SMBEntryPoint *getAddressOfSmbiosTable(void)␊
546{␊
547␉SMBEntryPoint␉*smbios;␊
548␉/*␊
549␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
550␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
551␉ */␊
552␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
553␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊
554␉{␊
555␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
556␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
557␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
558␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
559␉␉{␊
560␉␉␉return smbios;␊
561␉ }␊
562␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
563␉}␊
564␉error("ERROR: Unable to find SMBIOS!\n");␊
565␉pause("");␊
566␉return NULL;␊
567}␊
568␊
569

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