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1/*
2 * Copyright 2008 mackerintel
3 *
4 * state_generator.h
5 * Chameleon
6 *
7 * Created by Mozodojo on 20/07/10.
8 * Copyright 2010 mozodojo. All rights reserved.
9 *
10 */
11
12#include "libsaio.h"
13#include "boot.h"
14#include "bootstruct.h"
15#include "acpi.h"
16#include "efi_tables.h"
17#include "fake_efi.h"
18#include "acpi_patcher.h"
19#include "platform.h"
20#include "cpu.h"
21#include "aml_generator.h"
22#include "state_generator.h"
23
24#ifndef DEBUG_STATE
25#define DEBUG_STATE 0
26#endif
27
28#if DEBUG_STATE==2
29#define DBG(x...) {printf(x); sleep(1);}
30#elif DEBUG_STATE==1
31#define DBG(x...) printf(x)
32#else
33#define DBG(x...) msglog(x)
34#endif
35
36uint8_t acpi_cpu_count = 0;
37uint32_t acpi_cpu_p_blk = 0;
38char *acpi_cpu_name[32];
39
40void get_acpi_cpu_names(unsigned char *dsdt, uint32_t length)
41{
42uint32_t i;
43
44verbose("ACPIpatcher: start finding cpu names. Length %d\n", length);
45
46for (i=0; i<length-7; i++)
47{
48if (dsdt[i] == 0x5B && dsdt[i+1] == 0x83) // ProcessorOP
49{
50verbose("ACPIpatcher: DSDT[%X%X]\n", dsdt[i], dsdt[i+1]);
51
52uint32_t offset = i + 3 + (dsdt[i+2] >> 6);
53
54bool add_name = true;
55
56uint8_t j;
57
58for (j=0; j<4; j++)
59{
60char c = dsdt[offset+j];
61
62if (!aml_isvalidchar(c))
63{
64add_name = false;
65verbose("ACPIpatcher: invalid character found in ProcessorOP '0x%X'!\n", c);
66break;
67}
68}
69
70if (add_name)
71{
72acpi_cpu_name[acpi_cpu_count] = malloc(4);
73memcpy(acpi_cpu_name[acpi_cpu_count], dsdt+offset, 4);
74i = offset + 5;
75
76if (acpi_cpu_count == 0)
77acpi_cpu_p_blk = dsdt[i] | (dsdt[i+1] << 8);
78
79verbose("ACPIpatcher: found ACPI CPU [%c%c%c%c]\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);
80
81if (++acpi_cpu_count == 32) {
82return;
83}
84}
85}
86}
87
88verbose("ACPIpatcher: finished finding cpu names. Found: %d.\n", acpi_cpu_count);
89}
90
91static char const pss_ssdt_header[] =
92{
930x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */
940x01, 0x6A, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x00, /* ..PmRef. */
950x43, 0x70, 0x75, 0x50, 0x6D, 0x00, 0x00, 0x00, /* CpuPm... */
960x00, 0x30, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* .0..INTL */
970x31, 0x03, 0x10, 0x20,/* 1.._*/
98};
99
100static char const cst_ssdt_header[] =
101{
1020x53, 0x53, 0x44, 0x54, 0xE7, 0x00, 0x00, 0x00, /* SSDT.... */
1030x01, 0x17, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x41, /* ..PmRefA */
1040x43, 0x70, 0x75, 0x43, 0x73, 0x74, 0x00, 0x00, /* CpuCst.. */
1050x00, 0x10, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* ....INTL */
1060x31, 0x03, 0x10, 0x20/* 1.._*/
107};
108
109char resource_template_register_fixedhw[] =
110{
1110x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F,
1120x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1130x00, 0x00, 0x01, 0x79, 0x00
114};
115
116char resource_template_register_systemio[] =
117{
1180x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x01,
1190x08, 0x00, 0x00, 0x15, 0x04, 0x00, 0x00, 0x00,
1200x00, 0x00, 0x00, 0x79, 0x00,
121};
122
123struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt *dsdt)
124{
125
126if (Platform.CPU.Vendor != CPUID_VENDOR_INTEL) // 0x756E6547
127{
128DBG("Not an Intel platform: P-States will not be generated !!!\n");
129return NULL;
130}
131
132if (!(Platform.CPU.Features & CPU_FEATURE_MSR))
133{
134DBG("Unsupported CPU: P-States will not be generated !!! No MSR support\n");
135return NULL;
136}
137
138if (acpi_cpu_count == 0)
139{
140get_acpi_cpu_names((void*)dsdt, dsdt->Length);
141}
142
143if (acpi_cpu_count > 0)
144{
145struct p_state initial, maximum, minimum, p_states[32];
146uint8_t p_states_count = 0;
147
148// Retrieving P-States, ported from code by superhai (c)
149switch (Platform.CPU.Family)
150{
151case 0x06:
152{
153switch (Platform.CPU.Model)
154{
155case CPUID_MODEL_DOTHAN:// Intel Pentium M
156case CPUID_MODEL_YONAH:// Intel Mobile Core Solo, Duo
157case CPUID_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
158case CPUID_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
159case CPUID_MODEL_ATOM:// Intel Atom (45nm)
160{
161bool cpu_dynamic_fsb = false;
162
163if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))
164{
165wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));
166delay(1);
167cpu_dynamic_fsb = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);
168}
169
170bool cpu_noninteger_bus_ratio = (rdmsr64(MSR_IA32_PERF_STATUS) & (1ULL << 46));
171
172initial.Control = rdmsr64(MSR_IA32_PERF_STATUS);
173
174maximum.Control = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 32) & 0x1F3F) | (0x4000 * cpu_noninteger_bus_ratio);
175maximum.CID = ((maximum.FID & 0x1F) << 1) | cpu_noninteger_bus_ratio;
176
177minimum.FID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 24) & 0x1F) | (0x80 * cpu_dynamic_fsb);
178minimum.VID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 48) & 0x3F);
179
180if (minimum.FID == 0)
181{
182uint64_t msr;
183uint8_t i;
184// Probe for lowest fid
185for (i = maximum.FID; i >= 0x6; i--)
186{
187msr = rdmsr64(MSR_IA32_PERF_CONTROL);
188wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (i << 8) | minimum.VID);
189intel_waitforsts();
190minimum.FID = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0x1F;
191delay(1);
192}
193
194msr = rdmsr64(MSR_IA32_PERF_CONTROL);
195wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);
196intel_waitforsts();
197}
198
199if (minimum.VID == maximum.VID)
200{
201uint64_t msr;
202uint8_t i;
203// Probe for lowest vid
204for (i = maximum.VID; i > 0xA; i--)
205{
206msr = rdmsr64(MSR_IA32_PERF_CONTROL);
207wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (minimum.FID << 8) | i);
208intel_waitforsts();
209minimum.VID = rdmsr64(MSR_IA32_PERF_STATUS) & 0x3F;
210delay(1);
211}
212
213msr = rdmsr64(MSR_IA32_PERF_CONTROL);
214wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);
215intel_waitforsts();
216}
217
218minimum.CID = ((minimum.FID & 0x1F) << 1) >> cpu_dynamic_fsb;
219
220// Sanity check
221if (maximum.CID < minimum.CID)
222{
223DBG("P-States: Insane FID values!");
224p_states_count = 0;
225}
226else
227{
228uint8_t vidstep;
229uint8_t u, invalid = 0;
230// Finalize P-States
231// Find how many P-States machine supports
232p_states_count = (uint8_t)(maximum.CID - minimum.CID + 1);
233
234if (p_states_count > 32)
235{
236p_states_count = 32;
237}
238
239vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1);
240
241for (u = 0; u < p_states_count; u++)
242{
243uint8_t i = u - invalid;
244
245p_states[i].CID = maximum.CID - u;
246p_states[i].FID = (uint8_t)(p_states[i].CID >> 1);
247
248if (p_states[i].FID < 0x6)
249{
250if (cpu_dynamic_fsb)
251{
252p_states[i].FID = (p_states[i].FID << 1) | 0x80;
253}
254}
255else if (cpu_noninteger_bus_ratio)
256{
257p_states[i].FID = p_states[i].FID | (0x40 * (p_states[i].CID & 0x1));
258}
259
260if (i && p_states[i].FID == p_states[i-1].FID)
261{
262invalid++;
263}
264p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2;
265uint32_t multiplier = p_states[i].FID & 0x1f;// = 0x08
266bool half = p_states[i].FID & 0x40;// = 0x01
267bool dfsb = p_states[i].FID & 0x80;// = 0x00
268uint32_t fsb = (uint32_t)(Platform.CPU.FSBFrequency / 1000000); // = 400
269uint32_t halffsb = (fsb + 1) >> 1;// = 200
270uint32_t frequency = (multiplier * fsb);// = 3200
271
272p_states[i].Frequency = (uint32_t)(frequency + (half * halffsb)) >> dfsb;// = 3200 + 200 = 3400
273}
274
275p_states_count -= invalid;
276}
277
278break;
279}
280case CPUID_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
281case CPUID_MODEL_DALES://
282case CPUID_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
283case CPUID_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
284case CPUID_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx
285case CPUID_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
286case CPUID_MODEL_WESTMERE_EX:// Intel Xeon E7
287case CPUID_MODEL_SANDYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
288case CPUID_MODEL_JAKETOWN:// Intel Core i7, Xeon E5 LGA2011 (32nm)
289case CPUID_MODEL_IVYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (22nm)
290case CPUID_MODEL_HASWELL://
291case CPUID_MODEL_IVYBRIDGE_EP://
292//case CPUID_MODEL_HASWELL_H://
293case CPUID_MODEL_HASWELL_SVR://
294case CPUID_MODEL_HASWELL_ULT://
295case CPUID_MODEL_CRYSTALWELL://
296
297{
298if ( (Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE) ||
299(Platform.CPU.Model == CPUID_MODEL_JAKETOWN) ||
300(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE) ||
301(Platform.CPU.Model == CPUID_MODEL_HASWELL) ||
302(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE_EP) ||
303(Platform.CPU.Model == CPUID_MODEL_HASWELL_SVR) ||
304(Platform.CPU.Model == CPUID_MODEL_HASWELL_ULT) ||
305(Platform.CPU.Model == CPUID_MODEL_CRYSTALWELL) )
306{
307maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;
308}
309else
310{
311maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff;
312}
313
314minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
315
316DBG("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);
317
318// Sanity check
319if (maximum.Control < minimum.Control)
320{
321DBG("Insane control values!");
322p_states_count = 0;
323}
324else
325{
326uint8_t i;
327p_states_count = 0;
328
329for (i = maximum.Control; i >= minimum.Control; i--)
330{
331p_states[p_states_count].Control = i;
332p_states[p_states_count].CID = p_states[p_states_count].Control << 1;
333p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i;
334p_states_count++;
335}
336}
337
338break;
339}
340default:
341DBG("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);
342break;
343}
344}
345}
346
347// Generating SSDT
348if (p_states_count > 0)
349{
350
351int i;
352
353AML_CHUNK* root = aml_create_node(NULL);
354aml_add_buffer(root, pss_ssdt_header, sizeof(pss_ssdt_header)); // SSDT header
355
356AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");
357AML_CHUNK* name = aml_add_name(scop, "PSS_");
358AML_CHUNK* pack = aml_add_package(name);
359
360for (i = 0; i < p_states_count; i++)
361{
362AML_CHUNK* pstt = aml_add_package(pack);
363
364aml_add_dword(pstt, p_states[i].Frequency);
365aml_add_dword(pstt, 0x00000000); // Power
366aml_add_dword(pstt, 0x0000000A); // Latency
367aml_add_dword(pstt, 0x0000000A); // Latency
368aml_add_dword(pstt, p_states[i].Control);
369aml_add_dword(pstt, i+1); // Status
370}
371
372// Add aliaces
373for (i = 0; i < acpi_cpu_count; i++)
374{
375char name[9];
376sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);
377
378scop = aml_add_scope(root, name);
379aml_add_alias(scop, "PSS_", "_PSS");
380}
381
382aml_calculate_size(root);
383
384struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);
385
386aml_write_node(root, (void*)ssdt, 0);
387
388ssdt->Length = root->Size;
389ssdt->Checksum = 0;
390ssdt->Checksum = (uint8_t)(256 - checksum8(ssdt, ssdt->Length));
391
392aml_destroy_node(root);
393
394//dumpPhysAddr("P-States SSDT content: ", ssdt, ssdt->Length);
395
396DBG("SSDT with CPU P-States generated successfully\n");
397
398return ssdt;
399}
400}
401else
402{
403DBG("ACPI CPUs not found: P-States not generated !!!\n");
404}
405
406return NULL;
407}
408
409struct acpi_2_ssdt *generate_cst_ssdt(struct acpi_2_fadt *fadt)
410{
411
412if (Platform.CPU.Vendor != CPUID_VENDOR_INTEL) // 0x756E6547
413{
414DBG("Not an Intel platform: C-States will not be generated !!!\n");
415return NULL;
416}
417
418if (fadt == NULL)
419{
420DBG("FACP not exists: C-States will not be generated !!!\n");
421return NULL;
422}
423
424struct acpi_2_dsdt *dsdt = (void *)fadt->DSDT;
425
426if (dsdt == NULL)
427{
428DBG("DSDT not found: C-States will not be generated !!!\n");
429return NULL;
430}
431
432if (acpi_cpu_count == 0)
433get_acpi_cpu_names((void*)dsdt, dsdt->Length);
434
435if (acpi_cpu_count > 0)
436{
437bool c2_enabled = false;
438bool c3_enabled = false;
439bool c4_enabled = false;
440bool c6_enabled = false;
441bool c7_enabled = false;
442bool cst_using_systemio = false;
443
444getBoolForKey(kEnableC2State, &c2_enabled, &bootInfo->chameleonConfig);
445getBoolForKey(kEnableC3State, &c3_enabled, &bootInfo->chameleonConfig);
446getBoolForKey(kEnableC4State, &c4_enabled, &bootInfo->chameleonConfig);
447getBoolForKey(kEnableC6State, &c6_enabled, &bootInfo->chameleonConfig);
448getBoolForKey(kEnableC7State, &c7_enabled, &bootInfo->chameleonConfig);
449getBoolForKey(kCSTUsingSystemIO, &cst_using_systemio, &bootInfo->chameleonConfig);
450
451c2_enabled = c2_enabled | (fadt->C2_Latency < 100);
452c3_enabled = c3_enabled | (fadt->C3_Latency < 1000);
453
454unsigned char cstates_count = 1 + (c2_enabled ? 1 : 0) + ((c3_enabled || c4_enabled)? 1 : 0) + (c6_enabled ? 1 : 0) + (c7_enabled ? 1 : 0);
455
456AML_CHUNK* root = aml_create_node(NULL);
457aml_add_buffer(root, cst_ssdt_header, sizeof(cst_ssdt_header)); // SSDT header
458AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");
459AML_CHUNK* name = aml_add_name(scop, "CST_");
460AML_CHUNK* pack = aml_add_package(name);
461aml_add_byte(pack, cstates_count);
462
463AML_CHUNK* tmpl = aml_add_package(pack);
464if (cst_using_systemio)
465{
466// C1
467resource_template_register_fixedhw[8] = 0x00;
468resource_template_register_fixedhw[9] = 0x00;
469resource_template_register_fixedhw[18] = 0x00;
470aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
471aml_add_byte(tmpl, 0x01);// C1
472aml_add_word(tmpl, 0x0001);// Latency
473aml_add_dword(tmpl, 0x000003e8);// Power
474
475uint8_t p_blk_lo, p_blk_hi;
476
477if (c2_enabled) // C2
478{
479p_blk_lo = acpi_cpu_p_blk + 4;
480p_blk_hi = (acpi_cpu_p_blk + 4) >> 8;
481
482tmpl = aml_add_package(pack);
483resource_template_register_systemio[11] = p_blk_lo; // C2
484resource_template_register_systemio[12] = p_blk_hi; // C2
485aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
486aml_add_byte(tmpl, 0x02);// C2
487aml_add_word(tmpl, 0x0040);// Latency
488aml_add_dword(tmpl, 0x000001f4);// Power
489}
490
491if (c4_enabled) // C4
492{
493p_blk_lo = acpi_cpu_p_blk + 5;
494p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;
495
496tmpl = aml_add_package(pack);
497resource_template_register_systemio[11] = p_blk_lo; // C4
498resource_template_register_systemio[12] = p_blk_hi; // C4
499aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
500aml_add_byte(tmpl, 0x04);// C4
501aml_add_word(tmpl, 0x0080);// Latency
502aml_add_dword(tmpl, 0x000000C8);// Power
503}
504else if (c3_enabled) // C3
505{
506p_blk_lo = acpi_cpu_p_blk + 5;
507p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;
508
509tmpl = aml_add_package(pack);
510resource_template_register_systemio[11] = p_blk_lo; // C3
511resource_template_register_systemio[12] = p_blk_hi; // C3
512aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
513aml_add_byte(tmpl, 0x03);// C3
514aml_add_word(tmpl, 0x0043);// Latency
515aml_add_dword(tmpl, 0x000001F4);// Power
516}
517if (c6_enabled) // C6
518{
519p_blk_lo = acpi_cpu_p_blk + 5;
520p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;
521
522tmpl = aml_add_package(pack);
523resource_template_register_systemio[11] = p_blk_lo; // C6
524resource_template_register_systemio[12] = p_blk_hi; // C6
525aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
526aml_add_byte(tmpl, 0x06);// C6
527aml_add_word(tmpl, 0x0046);// Latency
528aml_add_dword(tmpl, 0x0000015E);// Power
529}
530if (c7_enabled) //C7
531{
532p_blk_lo = (acpi_cpu_p_blk + 6) & 0xff;
533p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;
534
535tmpl = aml_add_package(pack);
536resource_template_register_systemio[11] = p_blk_lo; // C4 or C7
537resource_template_register_systemio[12] = p_blk_hi;
538aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
539aml_add_byte(tmpl, 0x07);// C7
540aml_add_word(tmpl, 0xF5);// Latency as in iMac14,1
541aml_add_dword(tmpl, 0xC8);// Power
542}
543}
544else
545{
546// C1
547resource_template_register_fixedhw[8] = 0x01;
548resource_template_register_fixedhw[9] = 0x02;
549resource_template_register_fixedhw[18] = 0x01;
550
551resource_template_register_fixedhw[11] = 0x00; // C1
552aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
553aml_add_byte(tmpl, 0x01);// C1
554aml_add_word(tmpl, 0x0001);// Latency
555aml_add_dword(tmpl, 0x000003e8);// Power
556
557resource_template_register_fixedhw[18] = 0x03;
558
559if (c2_enabled) // C2
560{
561tmpl = aml_add_package(pack);
562resource_template_register_fixedhw[11] = 0x10; // C2
563aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
564aml_add_byte(tmpl, 0x02);// C2
565aml_add_word(tmpl, 0x0040);// Latency
566aml_add_dword(tmpl, 0x000001f4);// Power
567}
568
569if (c4_enabled) // C4
570{
571tmpl = aml_add_package(pack);
572resource_template_register_fixedhw[11] = 0x30; // C4
573aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
574aml_add_byte(tmpl, 0x04);// C4
575aml_add_word(tmpl, 0x0080);// Latency
576aml_add_dword(tmpl, 0x000000C8);// Power
577}
578else if (c3_enabled)
579{
580tmpl = aml_add_package(pack);
581resource_template_register_fixedhw[11] = 0x20; // C3
582aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
583aml_add_byte(tmpl, 0x03);// C3
584aml_add_word(tmpl, 0x0043);// Latency
585aml_add_dword(tmpl, 0x000001F4);// Power
586}
587if (c6_enabled) // C6
588{
589tmpl = aml_add_package(pack);
590resource_template_register_fixedhw[11] = 0x20; // C6
591aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
592aml_add_byte(tmpl, 0x06);// C6
593aml_add_word(tmpl, 0x0046);// Latency as in MacPro6,1
594aml_add_dword(tmpl, 0x0000015E);// Power
595}
596if (c7_enabled) // C7
597{
598tmpl = aml_add_package(pack);
599resource_template_register_fixedhw[11] = 0x30; // C4 or C7
600aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
601aml_add_byte(tmpl, 0x07);// C7
602aml_add_word(tmpl, 0xF5);// Latency as in iMac14,1
603aml_add_dword(tmpl, 0xC8);// Power
604}
605}
606
607// Aliaces
608int i;
609for (i = 0; i < acpi_cpu_count; i++)
610{
611char name[9];
612sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);
613
614scop = aml_add_scope(root, name);
615aml_add_alias(scop, "CST_", "_CST");
616}
617
618aml_calculate_size(root);
619
620struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);
621
622aml_write_node(root, (void*)ssdt, 0);
623
624ssdt->Length = root->Size;
625ssdt->Checksum = 0;
626ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);
627
628aml_destroy_node(root);
629
630// dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length);
631
632DBG("SSDT with CPU C-States generated successfully\n");
633
634return ssdt;
635}
636else
637{
638DBG("ACPI CPUs not found: C-States not generated !!!\n");
639}
640
641return NULL;
642}
643

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