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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * Bronya: 2015 Improve AMD support, cleanup and bugfix␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "bootstruct.h"␊
11#include "boot.h"␊
12␊
13#ifndef DEBUG_CPU␊
14␉#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18␉#define DBG(x...)␉␉printf(x)␊
19#else␊
20␉#define DBG(x...)␊
21#endif␊
22␊
23#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
24␊
25clock_frequency_info_t gPEClockFrequencyInfo;␊
26␊
27static __unused uint64_t rdtsc32(void)␊
28{␊
29␉unsigned int lo,hi;␊
30␉__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));␊
31␉return ((uint64_t)hi << 32) | lo;␊
32}␊
33␊
34/*␊
35 * timeRDTSC()␊
36 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
37 * It pauses until the value is latched in the counter␊
38 * and then reads the time stamp counter to return to the caller.␊
39 */␊
40static uint64_t timeRDTSC(void)␊
41{␊
42␉int␉␉attempts = 0;␊
43␉uint32_t ␉latchTime;␊
44␉uint64_t␉saveTime,intermediate;␊
45␉unsigned int␉timerValue, lastValue;␊
46␉//boolean_t␉int_enabled;␊
47␉/*␊
48␉ * Table of correction factors to account for␊
49␉ *␉ - timer counter quantization errors, and␊
50␉ *␉ - undercounts 0..5␊
51␉ */␊
52#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
53#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
54#define SAMPLE_NSECS␉␉(2000000000LL)␊
55#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
56#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
57␉uint64_t␉scale[6] = {␊
58␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
59␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
60␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
61␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
62␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
63␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
64␉};␊
65␊
66␉//int_enabled = ml_set_interrupts_enabled(false);␊
67␊
68restart:␊
69␉if (attempts >= 3) // increase to up to 9 attempts.␊
70␉{␊
71␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
72␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
73␉}␊
74␉attempts++;␊
75␉enable_PIT2();␉␉// turn on PIT2␊
76␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
77␉latchTime = rdtsc32();␉// get the time stamp to time␊
78␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
79␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
80␉saveTime = rdtsc32();␉// now time how long a 20th a second is...␊
81␉get_PIT2(&lastValue);␊
82␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
83␉do {␊
84␉␉intermediate = get_PIT2(&timerValue);␊
85␉␉if (timerValue > lastValue)␊
86␉␉{␊
87␉␉␉// Timer wrapped␊
88␉␉␉set_PIT2(0);␊
89␉␉␉disable_PIT2();␊
90␉␉␉goto restart;␊
91␉␉}␊
92␉␉lastValue = timerValue;␊
93␉} while (timerValue > 5);␊
94␉//printf("timerValue␉ %d\n",timerValue);␊
95␉//printf("intermediate 0x%016llX\n",intermediate);␊
96␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
97 ␊
98␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
99␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
100␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
101␉intermediate += latchTime;␉␉// add on our save fudge␊
102␊
103␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
104␉disable_PIT2();␉␉␉// turn off PIT 2␊
105␊
106␉//ml_set_interrupts_enabled(int_enabled);␊
107␉return intermediate;␊
108}␊
109␊
110/*␊
111 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
112 */␊
113static uint64_t __unused measure_tsc_frequency(void)␊
114{␊
115␉uint64_t tscStart;␊
116␉uint64_t tscEnd;␊
117␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
118␉unsigned long pollCount;␊
119␉uint64_t retval = 0;␊
120␉int i;␊
121␊
122␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
123␉ * counter 2. We run this loop 3 times to make sure the cache␊
124␉ * is hot and we take the minimum delta from all of the runs.␊
125␉ * That is to say that we're biased towards measuring the minimum␊
126␉ * number of TSC ticks that occur while waiting for the timer to␊
127␉ * expire. That theoretically helps avoid inconsistencies when␊
128␉ * running under a VM if the TSC is not virtualized and the host␊
129␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
130␉ */␊
131␉for(i = 0; i < 10; ++i)␊
132␉{␊
133␉␉enable_PIT2();␊
134␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
135␉␉tscStart = rdtsc64();␊
136␉␉pollCount = poll_PIT2_gate();␊
137␉␉tscEnd = rdtsc64();␊
138␉␉/* The poll loop must have run at least a few times for accuracy */␊
139␉␉if (pollCount <= 1)␊
140␉␉{␊
141␉␉␉continue;␊
142␉␉}␊
143␉␉/* The TSC must increment at LEAST once every millisecond.␊
144␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
145␉␉ * be >= 30. Anything less and the processor is way too slow.␊
146␉␉ */␊
147␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
148␉␉{␊
149␉␉␉continue;␊
150␉␉}␊
151␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
152␉␉if ( (tscEnd - tscStart) < tscDelta )␊
153␉␉{␊
154␉␉␉tscDelta = tscEnd - tscStart;␊
155␉␉}␊
156␉}␊
157␉/* tscDelta is now the least number of TSC ticks the processor made in␊
158␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
159␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
160␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
161␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
162␉ * dividing by the milliseconds, we simply multiply by 1000.␊
163␉ */␊
164␊
165␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
166␉ * that we're going to multiply by 1000 first so we do need at least some␊
167␉ * arithmetic headroom. For now, 32-bit should be enough.␊
168␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
169␉ */␊
170␉if (tscDelta > (1ULL<<32))␊
171␉{␊
172␉␉retval = 0;␊
173␉}␊
174␉else␊
175␉{␊
176␉␉retval = tscDelta * 1000 / 30;␊
177␉}␊
178␉disable_PIT2();␊
179␉return retval;␊
180}␊
181␊
182static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
183#define RTC_FAST_DENOM␉0xFFFFFFFF␊
184␊
185inline static uint32_t␊
186create_mul_quant_GHZ(int shift, uint32_t quant)␊
187{␊
188␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
189}␊
190␊
191struct␉{␊
192␉mach_timespec_t␉␉␉calend_offset;␊
193␉boolean_t␉␉␉calend_is_set;␊
194␊
195␉int64_t␉␉␉␉calend_adjtotal;␊
196␉int32_t␉␉␉␉calend_adjdelta;␊
197␊
198␉uint32_t␉␉␉boottime;␊
199␊
200␉mach_timebase_info_data_t␉timebase_const;␊
201␊
202␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
203} rtclock;␊
204␊
205uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
206uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
207uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
208uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
209␊
210static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
211{␊
212␊
213␉if (cycles > (NSEC_PER_SEC/20))␊
214␉{␊
215␉␉// we can use just a "fast" multiply to get nanos␊
216␉␉rtc_quant_shift = 32;␊
217␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
218␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
219␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
220␉}␊
221␉else␊
222␉{␊
223␉␉rtc_quant_shift = 26;␊
224␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
225␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
226␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
227␉}␊
228␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
229␉// BUT we also want to calculate...␊
230␊
231␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
232 / UI_CPUFREQ_ROUNDING_FACTOR)␊
233␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
234␊
235␉/*␊
236␉ * Set current measured speed.␊
237␉ */␊
238␉if (cycles >= 0x100000000ULL)␊
239␉{␊
240␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
241␉}␊
242␉else␊
243␉{␊
244␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
245␉}␊
246␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
247␊
248␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
249␉return(rtc_cyc_per_sec);␊
250}␊
251␊
252// Bronya C1E fix␊
253static void post_startup_cpu_fixups(void)␊
254{␊
255␉/*␊
256␉ * Some AMD processors support C1E state. Entering this state will␊
257␉ * cause the local APIC timer to stop, which we can't deal with at␊
258␉ * this time.␊
259␉ */␊
260␊
261␉uint64_t reg;␊
262␉verbose("\tLooking to disable C1E if is already enabled by the BIOS:\n");␊
263␉reg = rdmsr64(MSR_AMD_INT_PENDING_CMP_HALT);␊
264␉/* Disable C1E state if it is enabled by the BIOS */␊
265␉if ((reg >> AMD_ACTONCMPHALT_SHIFT) & AMD_ACTONCMPHALT_MASK)␊
266␉{␊
267␉␉reg &= ~(AMD_ACTONCMPHALT_MASK << AMD_ACTONCMPHALT_SHIFT);␊
268␉␉wrmsr64(MSR_AMD_INT_PENDING_CMP_HALT, reg);␊
269␉␉verbose("\tC1E disabled!\n");␊
270␉}␊
271}␊
272␊
273/*␊
274 * Large memcpy() into MMIO space can take longer than 1 clock tick (55ms).␊
275 * The timer interrupt must remain responsive when updating VRAM so␊
276 * as not to miss timer interrupts during countdown().␊
277 *␊
278 * If interrupts are enabled, use normal memcpy.␊
279 *␊
280 * If interrupts are disabled, breaks memcpy down␊
281 * into 128K chunks, times itself and makes a bios␊
282 * real-mode call every 25 msec in order to service␊
283 * pending interrupts.␊
284 *␊
285 * -- zenith432, May 22nd, 2016␊
286 */␊
287void* memcpy_interruptible(void* dst, const void* src, size_t len)␊
288{␊
289␉uint64_t tscFreq, lastTsc;␊
290␉uint32_t eflags, threshold;␊
291␉ptrdiff_t offset;␊
292␉const size_t chunk = 131072U;␉// 128K␊
293␊
294␉if (len <= chunk)␊
295␉{␊
296␉␉/*␊
297␉␉ * Short memcpy - use normal.␊
298␉␉ */␊
299␉␉return memcpy(dst, src, len);␊
300␉}␊
301␊
302␉__asm__ volatile("pushfl; popl %0" : "=r"(eflags));␊
303␉if (eflags & 0x200U)␊
304␉{␊
305␉␉/*␊
306␉␉ * Interrupts are enabled - use normal memcpy.␊
307␉␉ */␊
308␉␉return memcpy(dst, src, len);␊
309␉}␊
310␊
311␉tscFreq = Platform.CPU.TSCFrequency;␊
312␉if ((uint32_t) (tscFreq >> 32))␊
313␉{␊
314␉␉/*␊
315␉␉ * If TSC Frequency >= 2 ** 32, use a default time threshold.␊
316␉␉ */␊
317␉␉threshold = (~0U) / 40U;␊
318␉}␊
319␉else if (!(uint32_t) tscFreq)␊
320␉{␊
321␉␉/*␊
322␉␉ * If early on and TSC Frequency hasn't been estimated yet,␊
323␉␉ * use normal memcpy.␊
324␉␉ */␊
325␉␉return memcpy(dst, src, len);␊
326␉}␊
327␉else␊
328␉{␊
329␉␉threshold = ((uint32_t) tscFreq) / 40U;␊
330␉}␊
331␊
332␉/*␊
333␉ * Do the work␊
334␉ */␊
335␉offset = 0;␊
336␉lastTsc = rdtsc64();␊
337␉do␊
338␉{␊
339␉␉(void) memcpy((char*) dst + offset, (const char*) src + offset, chunk);␊
340␉␉offset += (ptrdiff_t) chunk;␊
341␉␉len -= chunk;␊
342␉␉if ((rdtsc64() - lastTsc) < threshold)␊
343␉␉{␊
344␉␉␉continue;␊
345␉␉}␊
346␉␉(void) readKeyboardStatus();␉// visit real-mode␊
347␉␉lastTsc = rdtsc64();␊
348␉}␊
349␉while (len > chunk);␊
350␉if (len)␊
351␉{␊
352␉␉(void) memcpy((char*) dst + offset, (const char*) src + offset, len);␊
353␉}␊
354␉return dst;␊
355}␊
356␊
357/*␊
358 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
359 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
360 *␉ a max multi. (used to calculate the FSB freq.),␊
361 *␉ and a current multi. (used to calculate the CPU freq.)␊
362 * - busFrequency = tscFrequency / multi␊
363 * - cpuFrequency = busFrequency * multi␊
364 */␊
365␊
366/* Decimal powers: */␊
367#define kilo (1000ULL)␊
368#define Mega (kilo * kilo)␊
369#define Giga (kilo * Mega)␊
370#define Tera (kilo * Giga)␊
371#define Peta (kilo * Tera)␊
372␊
373#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
374␊
375void get_cpuid(PlatformInfo_t *p)␊
376{␊
377␊
378␉char␉␉str[128];␊
379␉uint32_t␉reg[4];␊
380␉char␉␉*s␉␉␉= 0;␊
381␊
382␊
383␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
384␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
385␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
386␊
387␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
388␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); // Get the max extended cpuid␊
389␊
390␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
391␉{␊
392␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
393␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
394␉}␊
395␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
396␉{␊
397␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
398␉}␊
399␊
400// ==============================================================␊
401␊
402␉/* get BrandString (if supported) */␊
403␉/* Copyright: from Apple's XNU cpuid.c */␊
404␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
405␉{␊
406␉␉bzero(str, 128);␊
407␉␉/*␊
408␉␉ * The BrandString 48 bytes (max), guaranteed to␊
409␉␉ * be NULL terminated.␊
410␉␉ */␊
411␉␉do_cpuid(0x80000002, reg);␊
412␉␉memcpy(&str[0], (char *)reg, 16);␊
413␉␉do_cpuid(0x80000003, reg);␊
414␉␉memcpy(&str[16], (char *)reg, 16);␊
415␉␉do_cpuid(0x80000004, reg);␊
416␉␉memcpy(&str[32], (char *)reg, 16);␊
417␉␉for (s = str; *s != '\0'; s++)␊
418␉␉{␊
419␉␉␉if (*s != ' ')␊
420␉␉␉{␊
421␉␉␉␉break;␊
422␉␉␉}␊
423␉␉}␊
424␉␉strlcpy(p->CPU.BrandString, s, 48);␊
425␊
426␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
427␉␉{␊
428␉␉␉/*␊
429␉␉␉ * This string means we have a firmware-programmable brand string,␊
430␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
431␉␉␉ */␊
432␉␉␉p->CPU.BrandString[0] = '\0';␊
433␉␉}␊
434␉␉p->CPU.BrandString[47] = '\0';␊
435//␉␉DBG("\tBrandstring = %s\n", p->CPU.BrandString);␊
436␉}␊
437␊
438// ==============================================================␊
439␊
440␉switch(p->CPU.BrandString[0])␊
441␉{␊
442␉␉case 'A':␊
443␉␉␉/* AMD Processors */␊
444␉␉␉// The cache information is only in ecx and edx so only save␊
445␉␉␉// those registers␊
446␊
447␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
448␊
449␉␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
450␉␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
451␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
452␊
453␉␉␉break;␊
454␊
455␉␉case 'G':␊
456␉␉␉/* Intel Processors */␊
457␉␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); // Cache Index for Inte␊
458␊
459␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
460␉␉␉{␊
461␉␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
462␉␉␉}␊
463␊
464␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
465␉␉␉{␊
466␉␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
467␉␉␉}␊
468␊
469␉␉␉break;␊
470␉}␊
471}␊
472void scan_cpu(PlatformInfo_t *p)␊
473{␊
474␉verbose("[ CPU INFO ]\n");␊
475␉get_cpuid(p);␊
476␊
477␉uint64_t␉busFCvtt2n;␊
478␉uint64_t␉tscFCvtt2n;␊
479␉uint64_t␉tscFreq␉␉␉= 0;␊
480␉uint64_t␉busFrequency␉␉= 0;␊
481␉uint64_t␉cpuFrequency␉␉= 0;␊
482␉uint64_t␉msr␉␉␉= 0;␊
483␉uint64_t␉flex_ratio␉␉= 0;␊
484␉uint64_t␉cpuid_features;␊
485␊
486␉uint32_t␉max_ratio␉␉= 0;␊
487␉uint32_t␉min_ratio␉␉= 0;␊
488␉uint32_t␉reg[4];␊
489␉uint32_t␉cores_per_package␉= 0;␊
490␉uint32_t␉logical_per_package␉= 1;␊
491␉uint32_t␉threads_per_core␉= 1;␊
492␊
493␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
494␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
495␉uint8_t␉␉currdiv␉␉␉= 0;␊
496␉uint8_t␉␉currcoef␉␉= 0;␊
497␉uint8_t␉␉maxdiv␉␉␉= 0;␊
498␉uint8_t␉␉maxcoef␉␉␉= 0;␊
499␉uint8_t␉␉pic0_mask;␊
500␉uint8_t␉␉cpuMultN2␉␉= 0;␊
501␊
502␉const char␉*newratio;␊
503␊
504␉int␉␉len␉␉␉= 0;␊
505␉int␉␉myfsb␉␉␉= 0;␊
506␉int␉␉i␉␉␉= 0;␊
507␊
508␊
509/* http://www.flounder.com/cpuid_explorer2.htm␊
510 EAX (Intel):␊
511 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
512 +--------+----------------+--------+----+----+--------+--------+--------+␊
513 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
514 +--------+----------------+--------+----+----+--------+--------+--------+␊
515␊
516 EAX (AMD):␊
517 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
518 +--------+----------------+--------+----+----+--------+--------+--------+␊
519 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
520 +--------+----------------+--------+----+----+--------+--------+--------+␊
521*/␊
522␉///////////////////-- MaxFn,Vendor --////////////////////////␊
523␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
524␊
525␉///////////////////-- Signature, stepping, features -- //////␊
526␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊
527␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
528␉{␊
529␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
530␉}␊
531␉else␊
532␉{␊
533␉␉logical_per_package = 1;␊
534␉}␊
535␊
536␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
537␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
538␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
539␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
540␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
541␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
542␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
543␊
544␉if (p->CPU.Family == 0x0f)␊
545␉{␊
546␉␉p->CPU.Family += p->CPU.ExtFamily;␊
547␉}␊
548␊
549␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
550␉{␊
551␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
552␉}␊
553␊
554␉switch (p->CPU.Vendor)␊
555␉{␊
556␉␉case CPUID_VENDOR_INTEL:␊
557␉␉{␊
558␉␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
559␉␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
560␉␉␉{␊
561␉␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
562␉␉␉␉{␊
563␉␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
564␉␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
565␉␉␉␉␉{␊
566␉␉␉␉␉␉break;␊
567␉␉␉␉␉}␊
568␉␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
569␉␉␉␉}␊
570␉␉␉}␊
571␊
572␉␉␉if (i > 0)␊
573␉␉␉{␊
574␉␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
575␉␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
576␉␉␉}␊
577␊
578␉␉␉if (cores_per_package == 0)␊
579␉␉␉{␊
580␉␉␉␉cores_per_package = 1;␊
581␉␉␉}␊
582␊
583␉␉␉switch (p->CPU.Model)␊
584␉␉␉{␊
585␉␉␉␉case CPUID_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)␊
586␉␉␉␉case CPUID_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)␊
587␉␉␉␉case CPUID_MODEL_CLARKDALE: // Intel Core i3, i5, i7 LGA1156 (32nm)␊
588␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
589␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
590␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
591␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
592␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
593␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
594␉␉␉␉case CPUID_MODEL_HASWELL:␊
595␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
596␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
597␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
598␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊
599␉␉␉␉case CPUID_MODEL_BRASWELL:␊
600␉␉␉␉case CPUID_MODEL_AVOTON:␊
601␉␉␉␉case CPUID_MODEL_SKYLAKE:␊
602␉␉␉␉case CPUID_MODEL_BRODWELL_SVR:␊
603␉␉␉␉case CPUID_MODEL_BRODWELL_MSVR:␊
604␉␉␉␉case CPUID_MODEL_KNIGHT:␊
605␉␉␉␉case CPUID_MODEL_ANNIDALE:␊
606␉␉␉␉case CPUID_MODEL_GOLDMONT:␊
607␉␉␉␉case CPUID_MODEL_VALLEYVIEW:␊
608␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊
609␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX:␊
610␉␉␉␉case CPUID_MODEL_CANNONLAKE:␊
611␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊
612␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
613␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
614␉␉␉␉␉break;␊
615␊
616␉␉␉␉case CPUID_MODEL_DALES:␊
617␉␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊
618␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
619␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
620␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
621␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
622␉␉␉␉␉break;␊
623␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
624␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
625␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
626␉␉␉␉␉break;␊
627␉␉␉␉case CPUID_MODEL_ATOM:␊
628␉␉␉␉␉p->CPU.NoCores␉␉= 2;␊
629␉␉␉␉␉p->CPU.NoThreads␉= 2;␊
630␉␉␉␉␉break;␊
631␉␉␉␉default:␊
632␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
633␉␉␉␉␉break;␊
634␉␉␉}␊
635␊
636␉␉␉// workaround for Xeon Harpertown and Yorkfield␊
637␉␉␉if ((p->CPU.Model == CPUID_MODEL_PENRYN) &&␊
638␉␉␉␉(p->CPU.NoCores␉== 0))␊
639␉␉␉{␊
640␉␉␉␉if ((strstr(p->CPU.BrandString, "X54")) ||␊
641␉␉␉␉␉(strstr(p->CPU.BrandString, "E54")) ||␊
642␉␉␉␉␉(strstr(p->CPU.BrandString, "W35")) ||␊
643␉␉␉␉␉(strstr(p->CPU.BrandString, "X34")) ||␊
644␉␉␉␉␉(strstr(p->CPU.BrandString, "X33")) ||␊
645␉␉␉␉␉(strstr(p->CPU.BrandString, "L33")) ||␊
646␉␉␉␉␉(strstr(p->CPU.BrandString, "X32")) ||␊
647␉␉␉␉␉(strstr(p->CPU.BrandString, "L3426")) ||␊
648␉␉␉␉␉(strstr(p->CPU.BrandString, "L54")))␊
649␉␉␉␉{␊
650␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
651␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
652␉␉␉␉} else if (strstr(p->CPU.BrandString, "W36")) {␊
653␉␉␉␉␉p->CPU.NoCores␉␉= 6;␊
654␉␉␉␉␉p->CPU.NoThreads␉= 6;␊
655␉␉␉␉} else { //other Penryn and Wolfdale␊
656␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
657␉␉␉␉␉p->CPU.NoThreads␉= 0;␊
658␉␉␉␉}␊
659␉␉␉}␊
660␊
661␉␉␉if (p->CPU.NoCores == 0)␊
662␉␉␉{␊
663␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
664␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
665␉␉␉}␊
666␊
667␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊
668␉␉␉// workaround for N270. I don't know why it detected wrong␊
669␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
670␉␉␉{␊
671␉␉␉␉p->CPU.NoCores␉␉= 1;␊
672␉␉␉␉p->CPU.NoThreads␉= 2;␊
673␉␉␉}␊
674␊
675␉␉␉// workaround for Quad␊
676␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
677␉␉␉{␊
678␉␉␉␉p->CPU.NoCores␉␉= 4;␊
679␉␉␉␉p->CPU.NoThreads␉= 4;␊
680␉␉␉}␊
681␉␉}␊
682␊
683␉␉break;␊
684␊
685␉␉case CPUID_VENDOR_AMD:␊
686␉␉{␊
687␉␉␉post_startup_cpu_fixups();␊
688␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
689␉␉␉threads_per_core = cores_per_package;␊
690␊
691␉␉␉if (cores_per_package == 0)␊
692␉␉␉{␊
693␉␉␉␉cores_per_package = 1;␊
694␉␉␉}␊
695␊
696␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
697␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
698␊
699␉␉␉if (p->CPU.NoCores == 0)␊
700␉␉␉{␊
701␉␉␉␉p->CPU.NoCores = 1;␊
702␉␉␉␉p->CPU.NoThreads␉= 1;␊
703␉␉␉}␊
704␉␉}␊
705␉␉break;␊
706␊
707␉␉default :␊
708␉␉␉stop("Unsupported CPU detected! System halted.");␊
709␉}␊
710␊
711␉/* setup features */␊
712␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
713␉{␊
714␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
715␉}␊
716␊
717␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
718␉{␊
719␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
720␉}␊
721␊
722␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
723␉{␊
724␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
725␉}␊
726␊
727␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
728␉{␊
729␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
730␉}␊
731␊
732␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
733␉{␊
734␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
735␉}␊
736␊
737␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
738␉{␊
739␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
740␉}␊
741␊
742␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
743␉{␊
744␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
745␉}␊
746␊
747␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
748␉{␊
749␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
750␉}␊
751␊
752␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
753␉{␊
754␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
755␉}␊
756␊
757␉pic0_mask = inb(0x21U);␊
758␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
759␊
760␉uint64_t cycles;␊
761␉cycles = timeRDTSC();␊
762␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
763␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
764␉// if usual method failed␊
765␉if ( tscFreq < 1000 )␉//TEST␊
766␉{␊
767␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
768␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
769␉}␊
770␊
771␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
772␉{␊
773␉␉int intelCPU = p->CPU.Model;␊
774␉␉if (p->CPU.Family == 0x06)␊
775␉␉{␊
776␉␉␉/* Nehalem CPU model */␊
777␉␉␉switch (p->CPU.Model)␊
778␉␉␉{␊
779␉␉␉␉case CPUID_MODEL_NEHALEM:␊
780␉␉␉␉case CPUID_MODEL_FIELDS:␊
781␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
782␉␉␉␉case CPUID_MODEL_DALES:␊
783␉␉␉␉case CPUID_MODEL_WESTMERE:␊
784␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
785␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
786/* --------------------------------------------------------- */␊
787␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
788␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
789␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
790␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
791␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
792␉␉␉␉case CPUID_MODEL_HASWELL:␊
793␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
794␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
795␊
796␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
797␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
798␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊
799␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊
800/* --------------------------------------------------------- */␊
801␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
802␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
803␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
804␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
805␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
806␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
807␉␉␉␉␉if (bitfield(msr, 16, 16))␊
808␉␉␉␉␉{␊
809␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
810␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
811␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
812␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
813␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
814␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
815␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
816␉␉␉␉␉␉// is inadvertently set to 0.␊
817␊
818␉␉␉␉␉␉if (flex_ratio == 0)␊
819␉␉␉␉␉␉{␊
820␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
821␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
822␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
823␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
824␉␉␉␉␉␉}␊
825␉␉␉␉␉␉else␊
826␉␉␉␉␉␉{␊
827␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
828␉␉␉␉␉␉␉{␊
829␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
830␉␉␉␉␉␉␉}␊
831␉␉␉␉␉␉}␊
832␉␉␉␉␉}␊
833␊
834␉␉␉␉␉if (bus_ratio_max)␊
835␉␉␉␉␉{␊
836␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
837␉␉␉␉␉}␊
838␊
839␉␉␉␉␉//valv: Turbo Ratio Limit␊
840␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
841␉␉␉␉␉{␊
842␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
843␊
844␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
845␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
846␉␉␉␉␉}␊
847␉␉␉␉␉else␊
848␉␉␉␉␉{␊
849␉␉␉␉␉␉cpuFrequency = tscFreq;␊
850␉␉␉␉␉}␊
851␊
852␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
853␉␉␉␉␉{␊
854␉␉␉␉␉␉max_ratio = atoi(newratio);␊
855␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
856␉␉␉␉␉␉if (len >= 3)␊
857␉␉␉␉␉␉{␊
858␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
859␉␉␉␉␉␉}␊
860␊
861␉␉␉␉␉␉verbose("\tBus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
862␊
863␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
864␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
865␉␉␉␉␉␉{␊
866␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
867␉␉␉␉␉␉␉if (len >= 3)␊
868␉␉␉␉␉␉␉{␊
869␉␉␉␉␉␉␉␉maxdiv = 1;␊
870␉␉␉␉␉␉␉}␊
871␉␉␉␉␉␉␉else␊
872␉␉␉␉␉␉␉{␊
873␉␉␉␉␉␉␉␉maxdiv = 0;␊
874␉␉␉␉␉␉␉}␊
875␉␉␉␉␉␉}␊
876␉␉␉␉␉␉else␊
877␉␉␉␉␉␉{␊
878␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
879␉␉␉␉␉␉}␊
880␉␉␉␉␉}␊
881␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
882␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
883␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
884␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
885␊
886␉␉␉␉myfsb = busFrequency / 1000000;␊
887␉␉␉␉verbose("\tSticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
888␉␉␉␉currcoef = bus_ratio_max;␊
889␊
890␉␉␉␉break;␊
891␊
892␉␉␉default:␊
893␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
894␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
895␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
896␉␉␉␉// Non-integer bus ratio for the max-multi␊
897␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
898␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
899␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
900␊
901␉␉␉␉// This will always be model >= 3␊
902␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
903␉␉␉␉{␊
904␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
905␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
906␉␉␉␉}␊
907␉␉␉␉else␊
908␉␉␉␉{␊
909␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
910␉␉␉␉␉// XXX␊
911␉␉␉␉␉maxcoef = currcoef;␊
912␉␉␉␉}␊
913␊
914␉␉␉␉if (!currcoef)␊
915␉␉␉␉{␊
916␉␉␉␉␉currcoef = maxcoef;␊
917␉␉␉␉}␊
918␊
919␉␉␉␉if (maxcoef)␊
920␉␉␉␉{␊
921␉␉␉␉␉if (maxdiv)␊
922␉␉␉␉␉{␊
923␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
924␉␉␉␉␉}␊
925␉␉␉␉␉else␊
926␉␉␉␉␉{␊
927␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
928␉␉␉␉␉}␊
929␊
930␉␉␉␉␉if (currdiv)␊
931␉␉␉␉␉{␊
932␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
933␉␉␉␉␉}␊
934␉␉␉␉␉else␊
935␉␉␉␉␉{␊
936␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
937␉␉␉␉␉}␊
938␊
939␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
940␉␉␉␉}␊
941␉␉␉␉break;␊
942␉␉␉}␊
943␉␉}␊
944␉␉// Mobile CPU␊
945␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
946␉␉{␊
947␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
948␉␉}␊
949␉}␊
950␊
951␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
952␉{␊
953␉␉switch(p->CPU.Family)␊
954␉␉{␊
955␉␉␉case 0xF: /* K8 */␊
956␉␉␉{␊
957␉␉␉␉uint64_t fidvid = 0;␊
958␉␉␉␉uint64_t cpuMult;␊
959␉␉␉␉uint64_t fid;␊
960␊
961␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
962␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
963␊
964␉␉␉␉cpuMult = (fid + 8) / 2;␊
965␉␉␉␉currcoef = cpuMult;␊
966␊
967␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
968␉␉␉␉currdiv = cpuMultN2;␊
969␉␉␉␉/****** Addon END ******/␊
970␉␉␉}␊
971␉␉␉␉break;␊
972␊
973␉␉␉case 0x10: /*** AMD Family 10h ***/␊
974␉␉␉{␊
975␉␉␉␉uint64_t cofvid = 0;␊
976␉␉␉␉uint64_t cpuMult;␊
977␉␉␉␉uint64_t divisor = 0;␊
978␉␉␉␉uint64_t did;␊
979␉␉␉␉uint64_t fid;␊
980␊
981␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
982␉␉␉␉did = bitfield(cofvid, 8, 6);␊
983␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
984␉␉␉␉if (did == 0) divisor = 2;␊
985␉␉␉␉else if (did == 1) divisor = 4;␊
986␉␉␉␉else if (did == 2) divisor = 8;␊
987␉␉␉␉else if (did == 3) divisor = 16;␊
988␉␉␉␉else if (did == 4) divisor = 32;␊
989␊
990␉␉␉␉cpuMult = (fid + 16) / divisor;␊
991␉␉␉␉currcoef = cpuMult;␊
992␊
993␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
994␉␉␉␉currdiv = cpuMultN2;␊
995␊
996␉␉␉␉/****** Addon END ******/␊
997␉␉␉}␊
998␉␉␉break;␊
999␊
1000␉␉␉case 0x11: /*** AMD Family 11h ***/␊
1001␉␉␉{␊
1002␉␉␉␉uint64_t cofvid = 0;␊
1003␉␉␉␉uint64_t cpuMult;␊
1004␉␉␉␉uint64_t divisor = 0;␊
1005␉␉␉␉uint64_t did;␊
1006␉␉␉␉uint64_t fid;␊
1007␊
1008␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1009␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1010␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1011␉␉␉␉if (did == 0) divisor = 2;␊
1012␉␉␉␉else if (did == 1) divisor = 4;␊
1013␉␉␉␉else if (did == 2) divisor = 8;␊
1014␉␉␉␉else if (did == 3) divisor = 16;␊
1015␉␉␉␉else if (did == 4) divisor = 32;␊
1016␊
1017␉␉␉␉cpuMult = (fid + 8) / divisor;␊
1018␉␉␉␉currcoef = cpuMult;␊
1019␊
1020␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1021␉␉␉␉currdiv = cpuMultN2;␊
1022␊
1023␉␉␉␉/****** Addon END ******/␊
1024␉␉␉}␊
1025 break;␊
1026␊
1027␉␉␉case 0x12: /*** AMD Family 12h ***/␊
1028␉␉␉{␊
1029␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
1030␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
1031␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
1032␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1033␊
1034␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
1035␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
1036␉␉␉␉uint64_t divisor;␊
1037␉␉␉␉switch (CpuDid)␊
1038␉␉␉␉{␊
1039␉␉␉␉␉case 0: divisor = 1; break;␊
1040␉␉␉␉␉case 1: divisor = (3/2); break;␊
1041␉␉␉␉␉case 2: divisor = 2; break;␊
1042␉␉␉␉␉case 3: divisor = 3; break;␊
1043␉␉␉␉␉case 4: divisor = 4; break;␊
1044␉␉␉␉␉case 5: divisor = 6; break;␊
1045␉␉␉␉␉case 6: divisor = 8; break;␊
1046␉␉␉␉␉case 7: divisor = 12; break;␊
1047␉␉␉␉␉case 8: divisor = 16; break;␊
1048␉␉␉␉␉default: divisor = 1; break;␊
1049␉␉␉␉}␊
1050␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
1051␊
1052␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
1053␉␉␉␉currdiv = cpuMultN2;␊
1054␊
1055␉␉␉}␊
1056␉␉␉␉break;␊
1057␊
1058␉␉␉case 0x14: /* K14 */␊
1059␊
1060␉␉␉{␊
1061␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
1062␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
1063␉␉␉␉uint64_t prfsts;␊
1064␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1065␊
1066␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
1067␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
1068␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
1069␊
1070␉␉␉␉uint64_t frequencyId = 0x10;␊
1071␉␉␉␉currcoef = (frequencyId + 0x10) /␊
1072␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
1073␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
1074␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
1075␊
1076␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
1077␉␉␉␉currdiv = cpuMultN2;␊
1078␉␉␉}␊
1079␊
1080␉␉␉␉break;␊
1081␊
1082␉␉␉case 0x15: /*** AMD Family 15h ***/␊
1083␉␉␉case 0x06: /*** AMD Family 06h ***/␊
1084␉␉␉{␊
1085␊
1086␉␉␉␉uint64_t cofvid = 0;␊
1087␉␉␉␉uint64_t cpuMult;␊
1088␉␉␉␉uint64_t divisor = 0;␊
1089␉␉␉␉uint64_t did;␊
1090␉␉␉␉uint64_t fid;␊
1091␊
1092␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1093␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1094␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1095␉␉␉␉if (did == 0) divisor = 2;␊
1096␉␉␉␉else if (did == 1) divisor = 4;␊
1097␉␉␉␉else if (did == 2) divisor = 8;␊
1098␉␉␉␉else if (did == 3) divisor = 16;␊
1099␉␉␉␉else if (did == 4) divisor = 32;␊
1100␊
1101␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1102␉␉␉␉currcoef = cpuMult;␊
1103␊
1104␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1105␉␉␉␉currdiv = cpuMultN2;␊
1106␉␉␉}␊
1107␉␉␉␉break;␊
1108␊
1109␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
1110␉␉␉{␊
1111␉␉␉␉uint64_t cofvid = 0;␊
1112␉␉␉␉uint64_t cpuMult;␊
1113␉␉␉␉uint64_t divisor = 0;␊
1114␉␉␉␉uint64_t did;␊
1115␉␉␉␉uint64_t fid;␊
1116␊
1117␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1118␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1119␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1120␉␉␉␉if (did == 0) divisor = 1;␊
1121␉␉␉␉else if (did == 1) divisor = 2;␊
1122␉␉␉␉else if (did == 2) divisor = 4;␊
1123␉␉␉␉else if (did == 3) divisor = 8;␊
1124␉␉␉␉else if (did == 4) divisor = 16;␊
1125␊
1126␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1127␉␉␉␉currcoef = cpuMult;␊
1128␊
1129␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1130␉␉␉␉currdiv = cpuMultN2;␊
1131␉␉␉␉/****** Addon END ******/␊
1132␉␉␉}␊
1133␉␉␉␉break;␊
1134␊
1135␉␉␉default:␊
1136␉␉␉{␊
1137␉␉␉␉typedef unsigned long long vlong;␊
1138␉␉␉␉uint64_t prfsts;␊
1139␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1140␉␉␉␉uint64_t r;␊
1141␉␉␉␉vlong hz;␊
1142␉␉␉␉r = (prfsts>>6) & 0x07;␊
1143␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
1144␊
1145␉␉␉␉currcoef = hz / (200 * Mega);␊
1146␉␉␉}␊
1147␉␉}␊
1148␊
1149␉␉if (currcoef)␊
1150␉␉{␊
1151␉␉␉if (currdiv)␊
1152␉␉␉{␊
1153␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
1154␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1155␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
1156␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1157␊
1158␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
1159␉␉␉}␊
1160␉␉␉else␊
1161␉␉␉{␊
1162␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1163␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1164␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1165␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1166␉␉␉␉DBG("%d\n", currcoef);␊
1167␉␉␉}␊
1168␉␉}␊
1169␉␉else if (!cpuFrequency)␊
1170␉␉{␊
1171␉␉␉cpuFrequency = tscFreq;␊
1172␉␉}␊
1173␉}␊
1174␊
1175#if 0␊
1176␉if (!busFrequency)␊
1177␉{␊
1178␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1179␉␉DBG("\tCPU: busFrequency = 0! using the default value for FSB!\n");␊
1180␉␉cpuFrequency = tscFreq;␊
1181␉}␊
1182␊
1183␉DBG("\tcpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1184␊
1185#endif␊
1186␊
1187␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
1188␊
1189␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1190␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1191␉p->CPU.CurrCoef = currcoef;␊
1192␉p->CPU.CurrDiv = currdiv;␊
1193␉p->CPU.TSCFrequency = tscFreq;␊
1194␉p->CPU.FSBFrequency = busFrequency;␊
1195␉p->CPU.CPUFrequency = cpuFrequency;␊
1196␊
1197␉// keep formatted with spaces instead of tabs␊
1198␊
1199␉DBG("\tCPUID Raw Values:\n");␊
1200␉for (i = 0; i < CPUID_MAX; i++)␊
1201␉{␊
1202␉␉DBG("\t%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1203␉}␊
1204␉DBG("\n");␊
1205␉DBG("\tBrand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1206␉DBG("\tVendor: 0x%X\n",␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1207␉DBG("\tFamily: 0x%X\n",␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1208␉DBG("\tExtFamily: 0x%X\n",␉p->CPU.ExtFamily);␊
1209␉DBG("\tSignature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1210␉/*switch (p->CPU.Type) {␊
1211␉␉case PT_OEM:␊
1212␉␉␉DBG("\tProcessor type: Intel Original OEM Processor\n");␊
1213␉␉␉break;␊
1214␉␉case PT_OD:␊
1215␉␉␉DBG("\tProcessor type: Intel Over Drive Processor\n");␊
1216␉␉␉break;␊
1217␉␉case PT_DUAL:␊
1218␉␉␉DBG("\tProcessor type: Intel Dual Processor\n");␊
1219␉␉␉break;␊
1220␉␉case PT_RES:␊
1221␉␉␉DBG("\tProcessor type: Intel Reserved\n");␊
1222␉␉␉break;␊
1223␉␉default:␊
1224␉␉␉break;␊
1225␉}*/␊
1226␉DBG("\tModel: 0x%X\n",␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1227␉DBG("\tExtModel: 0x%X\n",␉p->CPU.ExtModel);␊
1228␉DBG("\tStepping: 0x%X\n",␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1229␉DBG("\tMaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1230␉DBG("\tCurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1231␉DBG("\tMaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1232␉DBG("\tCurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1233␉DBG("\tTSCFreq: %dMHz\n",␉p->CPU.TSCFrequency / 1000000);␊
1234␉DBG("\tFSBFreq: %dMHz\n",␉p->CPU.FSBFrequency / 1000000);␊
1235␉DBG("\tCPUFreq: %dMHz\n",␉p->CPU.CPUFrequency / 1000000);␊
1236␉DBG("\tCores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1237␉DBG("\tLogical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1238␉DBG("\tFeatures: 0x%08x\n",␉p->CPU.Features);␊
1239␊
1240␉verbose("\n");␊
1241#if DEBUG_CPU␊
1242␉pause();␊
1243#endif␊
1244}␊
1245

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