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Root/trunk/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12␉#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16␉#define DBG(x...)␉printf(x)␊
17#else␊
18␉#define DBG(x...)␊
19#endif␊
20␊
21#define XEON "Xeon"␊
22#define CORE_M "Core(TM) M"␊
23#define CORE_M3 "Core(TM) m3"␊
24#define CORE_M5 "Core(TM) m5"␊
25#define CORE_M7 "Core(TM) m7"␊
26#define CORE_I3 "Core(TM) i3"␊
27#define CORE_I5 "Core(TM) i5"␊
28#define CORE_I7 "Core(TM) i7"␊
29␊
30bool getProcessorInformationExternalClock(returnType *value)␊
31{␊
32␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
33␉{␊
34␉␉switch (Platform.CPU.Family)␊
35␉␉{␊
36␉␉␉case 0x06:␊
37␉␉␉␉switch (Platform.CPU.Model)␊
38␉␉␉␉{␊
39␉␉␉␉␉// set external clock to 0 for SANDY␊
40␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
41␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
42␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
43␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
44␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
45␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
46␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
47␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
48␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
49␊
50␉␉␉␉␉␉value->word = 0;␊
51␉␉␉␉␉␉break;␊
52␉␉␉␉␉default:␊
53␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
54␉␉␉␉␉␉break;␊
55␉␉␉␉}␊
56␉␉␉␉break;␊
57␊
58␉␉␉default:␊
59␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
60␉␉␉␉break;␊
61␉␉}␊
62␉}␊
63␉else␊
64␉{␊
65␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
66␉}␊
67␊
68␉return true;␊
69}␊
70␊
71bool getProcessorInformationMaximumClock(returnType *value)␊
72{␊
73␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
74␉return true;␊
75}␊
76␊
77bool getSMBOemProcessorBusSpeed(returnType *value)␊
78{␊
79␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
80␉{␊
81␉␉switch (Platform.CPU.Family)␊
82␉␉{␊
83␉␉␉case 0x06:␊
84␉␉␉␉switch (Platform.CPU.Model)␊
85␉␉␉␉{␊
86␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
87␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
88␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
89␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
90␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
91␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
92␉␉␉␉␉␉return false;␊
93␊
94␉␉␉␉␉case 0x19:␊
95␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
96␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
97␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
98␉␉␉␉␉case CPUID_MODEL_DALES:␉// Intel Core i3, i5 LGA1156 (32nm)␊
99␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
100␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
101␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
102␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
103␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
104␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
105␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
106␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
107␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
108␉␉␉␉␉{␊
109␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
110␉␉␉␉␉␉int nhm_bus = 0x3F;␊
111␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
112␉␉␉␉␉␉unsigned long did, vid;␊
113␉␉␉␉␉␉unsigned int i;␊
114␉␉␉␉␉␉␊
115␉␉␉␉␉␉// Nehalem supports Scrubbing␊
116␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
117␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
118␉␉␉␉␉␉{␊
119␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
120␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
121␉␉␉␉␉␉␉vid &= 0xFFFF;␊
122␉␉␉␉␉␉␉did &= 0xFF00;␊
123␉␉␉␉␉␉␉␊
124␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
125␉␉␉␉␉␉␉{␊
126␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
127␉␉␉␉␉␉␉}␊
128␉␉␉␉␉␉}␊
129␊
130␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
131␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
132␉␉␉␉␉␉qpimult &= 0x7F;␊
133␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
134␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
135␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
136␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
137␉␉␉␉␉␉{␊
138␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
139␉␉␉␉␉␉}␊
140␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
141␉␉␉␉␉␉value->word = qpibusspeed;␊
142␉␉␉␉␉␉return true;␊
143␉␉␉␉␉}␊
144␉␉␉␉␉break;␊
145␊
146␉␉␉␉␉default:␊
147␉␉␉␉␉␉break;␊
148␉␉␉␉}␊
149␉␉␉␉break;␊
150␊
151␉␉␉default:␊
152␉␉␉␉break;␊
153␉␉}␊
154␉}␊
155␊
156␉return false; //Unsupported CPU type␊
157}␊
158␊
159//bool getSMBOemPlatformFeature(returnType *value)␊
160//{␊
161// value->word = (uint64_t)(0x0000000000000001);␊
162// return true;␊
163//}␊
164␊
165uint16_t simpleGetSMBOemProcessorType(void)␊
166{␊
167␉if (Platform.CPU.NoCores >= 4)␊
168␉{␊
169␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊
170␉}␊
171␉else if (Platform.CPU.NoCores == 1)␊
172␉{␊
173␉␉return 0x201;␉// 513 - Core Duo␊
174␉};␊
175␉␊
176␉return 0x301;␉␉// 769 - Core 2 Duo␊
177}␊
178␊
179bool getSMBOemProcessorType(returnType *value)␊
180{␊
181␉static bool done = false;␊
182␊
183␉value->word = simpleGetSMBOemProcessorType();␊
184␊
185␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
186␉{␊
187␉␉if (!done)␊
188␉␉{␊
189␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
190␉␉␉done = true;␊
191␉␉}␊
192␊
193␉␉switch (Platform.CPU.Family)␊
194␉␉{␊
195␉␉␉case 0x0F:␊
196␉␉␉case 0x06:␊
197␊
198␉␉␉␉switch (Platform.CPU.Model)␊
199␉␉␉␉{␊
200␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
201␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
202␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
203␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
204␊
205␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
206␉␉␉␉␉␉{␊
207␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
208␉␉␉␉␉␉␉return true;␊
209␉␉␉␉␉␉}␊
210␊
211␉␉␉␉␉␉return true;␊
212␊
213␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
214␉␉␉␉␉case CPUID_MODEL_CONROE:␊
215␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
216␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
217␉␉␉␉␉␉return true;␊
218␊
219␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
220␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
221␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
222␊
223␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
224␉␉␉␉␉␉{␊
225␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
226␉␉␉␉␉␉␉return true;␊
227␉␉␉␉␉␉}␊
228␊
229␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
230␉␉␉␉␉␉{␊
231␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
232␉␉␉␉␉␉␉return true;␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉else␊
235␉␉␉␉␉␉{␊
236␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
237␉␉␉␉␉␉␉return true;␊
238␉␉␉␉␉␉}␊
239␊
240␉␉␉␉␉␉return true;␊
241␊
242␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
243␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
244␊
245␉␉␉␉␉␉return true;␊
246␊
247␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
248␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
249␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
250␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
251␊
252␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
253␉␉␉␉␉␉{␊
254␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
255␉␉␉␉␉␉␉return true;␊
256␉␉␉␉␉␉}␊
257␊
258␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
259␉␉␉␉␉␉{␊
260␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
261␉␉␉␉␉␉␉return true;␊
262␉␉␉␉␉␉}␊
263␊
264␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
265␉␉␉␉␉␉{␊
266␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
267␉␉␉␉␉␉␉return true;␊
268␉␉␉␉␉␉}␊
269␊
270␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
271␉␉␉␉␉␉{␊
272␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
273␉␉␉␉␉␉␉return true;␊
274␉␉␉␉␉␉}␊
275␊
276␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
277␉␉␉␉␉␉{␊
278␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
279␉␉␉␉␉␉␉return true;␊
280␉␉␉␉␉␉}␊
281␊
282␉␉␉␉␉␉return true;␊
283␊
284␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
285␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
286␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
287␊
288␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
289␉␉␉␉␉␉{␊
290␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
291␉␉␉␉␉␉␉return true;␊
292␉␉␉␉␉␉}␊
293␊
294␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
295␉␉␉␉␉␉{␊
296␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
297␉␉␉␉␉␉␉return true;␊
298␉␉␉␉␉␉}␊
299␊
300␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
301␉␉␉␉␉␉{␊
302␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
303␉␉␉␉␉␉␉return true;␊
304␉␉␉␉␉␉}␊
305␊
306␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
307␉␉␉␉␉␉{␊
308␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
309␉␉␉␉␉␉␉return true;␊
310␉␉␉␉␉␉}␊
311␊
312␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
313␉␉␉␉␉␉{␊
314␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
315␉␉␉␉␉␉␉return true;␊
316␉␉␉␉␉␉}␊
317␊
318␉␉␉␉␉␉return true;␊
319␊
320␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
321␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
322␊
323␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
324␉␉␉␉␉␉{␊
325␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
326␉␉␉␉␉␉␉return true;␊
327␉␉␉␉␉␉}␊
328␊
329␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
330␉␉␉␉␉␉{␊
331␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
332␉␉␉␉␉␉␉return true;␊
333␉␉␉␉␉␉}␊
334␊
335␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
336␉␉␉␉␉␉{␊
337␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
338␉␉␉␉␉␉␉return true;␊
339␉␉␉␉␉␉}␊
340␊
341␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
342␉␉␉␉␉␉{␊
343␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
344␉␉␉␉␉␉␉return true;␊
345␉␉␉␉␉␉}␊
346␊
347␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
348␉␉␉␉␉␉{␊
349␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
350␉␉␉␉␉␉␉return true;␊
351␉␉␉␉␉␉}␊
352␊
353␉␉␉␉␉␉return true;␊
354␊
355␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
356␊
357␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
358␉␉␉␉␉␉{␊
359␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
360␉␉␉␉␉␉␉return true;␊
361␉␉␉␉␉␉}␊
362␊
363␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
364␉␉␉␉␉␉{␊
365␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
366␉␉␉␉␉␉␉return true;␊
367␉␉␉␉␉␉}␊
368␊
369␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
370␉␉␉␉␉␉{␊
371␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
372␉␉␉␉␉␉␉return true;␊
373␉␉␉␉␉␉}␊
374␊
375␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
376␉␉␉␉␉␉{␊
377␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
378␉␉␉␉␉␉␉return true;␊
379␉␉␉␉␉␉}␊
380␊
381␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
382␉␉␉␉␉␉{␊
383␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
384␉␉␉␉␉␉␉return true;␊
385␉␉␉␉␉␉}␊
386␊
387␉␉␉␉␉␉return true;␊
388␊
389␉␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␉␉// 0x3D -␊
390␊
391␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊
392␉␉␉␉␉␉{␊
393␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊
394␉␉␉␉␉␉␉return true;␊
395␉␉␉␉␉␉}␊
396␊
397␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
398␉␉␉␉␉␉{␊
399␉␉␉␉␉␉␉value->word = 0x906;␉␉// 2310 - Apple doesn't use it␊
400␉␉␉␉␉␉␉return true;␊
401␉␉␉␉␉␉}␊
402␊
403␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
404␉␉␉␉␉␉{␊
405␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊
406␉␉␉␉␉␉␉return true;␊
407␉␉␉␉␉␉}␊
408␊
409␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
410␉␉␉␉␉␉{␊
411␉␉␉␉␉␉␉value->word = 0x706;␉␉// 1798␊
412␉␉␉␉␉␉␉return true;␊
413␉␉␉␉␉␉}␊
414␊
415␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
416␉␉␉␉␉␉{␊
417␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊
418␉␉␉␉␉␉␉return true;␊
419␉␉␉␉␉␉}␊
420␊
421//␉␉␉␉␉␉value->word = 0x706;␉␉␉// 1798␊
422␉␉␉␉␉␉return true;␊
423␊
424␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
425␊
426␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
427␉␉␉␉␉␉return true;␊
428␊
429␉␉␉␉␉case CPUID_MODEL_ATOM_3700:␉␉␉// 0x37␊
430␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C␊
431␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F␊
432␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45␊
433␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46␊
434␉␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␉␉␉// 0x47␊
435␉␉␉␉␉case CPUID_MODEL_SKYLAKE:␉␉␉// 0x4E␊
436␉␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX:␉␉␉// 0x55␊
437␉␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␉␉␉// 0x5E␊
438␊
439␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
440␉␉␉␉␉␉{␊
441␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
442␉␉␉␉␉␉␉return true;␊
443␉␉␉␉␉␉}␊
444␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
445␉␉␉␉␉␉{␊
446␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
447␉␉␉␉␉␉␉return true;␊
448␉␉␉␉␉␉}␊
449␊
450␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
451␉␉␉␉␉␉{␊
452␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
453␉␉␉␉␉␉␉return true;␊
454␉␉␉␉␉␉}␊
455␊
456␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
457␉␉␉␉␉␉{␊
458␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
459␉␉␉␉␉␉␉return true;␊
460␉␉␉␉␉␉}␊
461␊
462␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊
463␉␉␉␉␉␉{␊
464␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊
465␉␉␉␉␉␉␉return true;␊
466␉␉␉␉␉␉}␊
467␊
468␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M3))␊
469␉␉␉␉␉␉{␊
470␉␉␉␉␉␉␉value->word = 0xC05;␊
471␉␉␉␉␉␉␉return true;␊
472␉␉␉␉␉␉}␊
473␊
474␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M5))␊
475␉␉␉␉␉␉{␊
476␉␉␉␉␉␉␉value->word = 0xD05;␊
477␉␉␉␉␉␉␉return true;␊
478␉␉␉␉␉␉}␊
479␊
480␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M7))␊
481␉␉␉␉␉␉{␊
482␉␉␉␉␉␉␉value->word = 0xE05;␊
483␉␉␉␉␉␉␉return true;␊
484␉␉␉␉␉␉}␊
485␊
486␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
487␉␉␉␉␉␉{␊
488␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
489␉␉␉␉␉␉␉return true;␊
490␉␉␉␉␉␉}␊
491␊
492␉␉␉␉␉␉return true;␊
493␊
494␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
495␊
496␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
497␉␉␉␉␉␉return true;␊
498␊
499␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
500␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
501␊
502␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
503␉␉␉␉␉␉return true;␊
504␊
505␉␉␉␉␉default:␊
506␊
507␉␉␉␉␉␉return true;␊
508␉␉␉␉␉␉break; // Unsupported CPU type␊
509␉␉␉␉}␊
510␉␉␉␉break;␊
511␊
512␉␉␉default:␊
513␉␉␉␉break;␊
514␉␉}␊
515␉}␊
516/*␊
517␉if (Platform.CPU.Vendor == CPUID_VENDOR_AMD) // AMD␊
518␉{␊
519␉␉value->word = simpleGetSMBOemProcessorType();␊
520␉␉return true;␊
521␉}␊
522*/␊
523␉return false;␊
524}␊
525␊
526bool getSMBMemoryDeviceMemoryType(returnType *value)␊
527{␊
528␉static int idx = -1;␊
529␉int␉map;␊
530␊
531␉idx++;␊
532␉if (idx < MAX_RAM_SLOTS)␊
533␉{␊
534␉␉map = Platform.DMI.DIMM[idx];␊
535␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
536␉␉{␊
537␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
538␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
539␉␉␉return true;␊
540␉␉}␊
541␉}␊
542␊
543␉return false;␊
544//␉value->byte = SMB_MEM_TYPE_DDR2;␊
545//␉return true;␊
546}␊
547␊
548bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
549{␊
550␉value->word = 0xFFFF;␊
551␉return true;␊
552}␊
553␊
554bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
555{␊
556␉static int idx = -1;␊
557␉int␉map;␊
558␊
559␉idx++;␊
560␉if (idx < MAX_RAM_SLOTS)␊
561␉{␊
562␉␉map = Platform.DMI.DIMM[idx];␊
563␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
564␉␉{␊
565␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
566␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
567␉␉␉return true;␊
568␉␉}␊
569␉}␊
570␊
571␉return false;␊
572//␉value->dword = 800;␊
573//␉return true;␊
574}␊
575␊
576bool getSMBMemoryDeviceManufacturer(returnType *value)␊
577{␊
578␉static int idx = -1;␊
579␉int␉map;␊
580␊
581␉idx++;␊
582␉if (idx < MAX_RAM_SLOTS)␊
583␉{␊
584␉␉map = Platform.DMI.DIMM[idx];␊
585␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
586␉␉{␊
587␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
588␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
589␉␉␉return true;␊
590␉␉}␊
591␉}␊
592␊
593␉if (!bootInfo->memDetect)␊
594␉{␊
595␉␉return false;␊
596␉}␊
597␉value->string = NOT_AVAILABLE;␊
598␉return true;␊
599}␊
600␊
601bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
602{␊
603␉static int idx = -1;␊
604␉int␉map;␊
605␊
606␉idx++;␊
607␊
608␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n", idx, MAX_RAM_SLOTS);␊
609␊
610␉if (idx < MAX_RAM_SLOTS)␊
611␉{␊
612␉␉map = Platform.DMI.DIMM[idx];␊
613␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
614␉␉{␊
615␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
616␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
617␉␉␉return true;␊
618␉␉}␊
619␉}␊
620␊
621␉if (!bootInfo->memDetect)␊
622␉{␊
623␉␉return false;␊
624␉}␊
625␉value->string = NOT_AVAILABLE;␊
626␉return true;␊
627}␊
628␊
629bool getSMBMemoryDevicePartNumber(returnType *value)␊
630{␊
631␉static int idx = -1;␊
632␉int␉map;␊
633␊
634␉idx++;␊
635␉if (idx < MAX_RAM_SLOTS)␊
636␉{␊
637␉␉map = Platform.DMI.DIMM[idx];␊
638␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
639␉␉{␊
640␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
641␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
642␉␉␉return true;␊
643␉␉}␊
644␉}␊
645␊
646␉if (!bootInfo->memDetect)␊
647␉{␊
648␉␉return false;␊
649␉}␊
650␉value->string = NOT_AVAILABLE;␊
651␉return true;␊
652}␊
653␊
654␊
655// getting smbios addr with fast compare ops, late checksum testing ...␊
656#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
657static const char * const SMTAG = "_SM_";␊
658static const char* const DMITAG = "_DMI_";␊
659␊
660SMBEntryPoint *getAddressOfSmbiosTable(void)␊
661{␊
662␉SMBEntryPoint␉*smbios;␊
663␉/*␊
664␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
665␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
666␉ */␊
667␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
668␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊
669␉{␊
670␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
671␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
672␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
673␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
674␉␉{␊
675␉␉␉return smbios;␊
676␉ }␊
677␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
678␉}␊
679␉printf("ERROR: Unable to find SMBIOS!\n");␊
680␉pause();␊
681␉return NULL;␊
682}␊
683␊
684

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