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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * Bronya: 2015 Improve AMD support, cleanup and bugfix␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "bootstruct.h"␊
11#include "boot.h"␊
12␊
13#ifndef DEBUG_CPU␊
14␉#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18␉#define DBG(x...)␉␉printf(x)␊
19#else␊
20␉#define DBG(x...)␊
21#endif␊
22␊
23#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
24␊
25clock_frequency_info_t gPEClockFrequencyInfo;␊
26␊
27static __unused uint64_t rdtsc32(void)␊
28{␊
29␉unsigned int lo,hi;␊
30␉__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));␊
31␉return ((uint64_t)hi << 32) | lo;␊
32}␊
33␊
34/*␊
35 * timeRDTSC()␊
36 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
37 * It pauses until the value is latched in the counter␊
38 * and then reads the time stamp counter to return to the caller.␊
39 */␊
40static uint64_t timeRDTSC(void)␊
41{␊
42␉int␉␉attempts = 0;␊
43␉uint32_t ␉latchTime;␊
44␉uint64_t␉saveTime,intermediate;␊
45␉unsigned int␉timerValue, lastValue;␊
46␉//boolean_t␉int_enabled;␊
47␉/*␊
48␉ * Table of correction factors to account for␊
49␉ *␉ - timer counter quantization errors, and␊
50␉ *␉ - undercounts 0..5␊
51␉ */␊
52#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
53#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
54#define SAMPLE_NSECS␉␉(2000000000LL)␊
55#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
56#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
57␉uint64_t␉scale[6] = {␊
58␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
59␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
60␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
61␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
62␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
63␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
64␉};␊
65␊
66␉//int_enabled = ml_set_interrupts_enabled(false);␊
67␊
68restart:␊
69␉if (attempts >= 3) // increase to up to 9 attempts.␊
70␉{␊
71␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
72␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
73␉}␊
74␉attempts++;␊
75␉enable_PIT2();␉␉// turn on PIT2␊
76␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
77␉latchTime = rdtsc32();␉// get the time stamp to time␊
78␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
79␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
80␉saveTime = rdtsc32();␉// now time how long a 20th a second is...␊
81␉get_PIT2(&lastValue);␊
82␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
83␉do {␊
84␉␉intermediate = get_PIT2(&timerValue);␊
85␉␉if (timerValue > lastValue)␊
86␉␉{␊
87␉␉␉// Timer wrapped␊
88␉␉␉set_PIT2(0);␊
89␉␉␉disable_PIT2();␊
90␉␉␉goto restart;␊
91␉␉}␊
92␉␉lastValue = timerValue;␊
93␉} while (timerValue > 5);␊
94␉//printf("timerValue␉ %d\n",timerValue);␊
95␉//printf("intermediate 0x%016llX\n",intermediate);␊
96␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
97 ␊
98␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
99␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
100␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
101␉intermediate += latchTime;␉␉// add on our save fudge␊
102␊
103␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
104␉disable_PIT2();␉␉␉// turn off PIT 2␊
105␊
106␉//ml_set_interrupts_enabled(int_enabled);␊
107␉return intermediate;␊
108}␊
109␊
110/*␊
111 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
112 */␊
113static uint64_t __unused measure_tsc_frequency(void)␊
114{␊
115␉uint64_t tscStart;␊
116␉uint64_t tscEnd;␊
117␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
118␉unsigned long pollCount;␊
119␉uint64_t retval = 0;␊
120␉int i;␊
121␊
122␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
123␉ * counter 2. We run this loop 3 times to make sure the cache␊
124␉ * is hot and we take the minimum delta from all of the runs.␊
125␉ * That is to say that we're biased towards measuring the minimum␊
126␉ * number of TSC ticks that occur while waiting for the timer to␊
127␉ * expire. That theoretically helps avoid inconsistencies when␊
128␉ * running under a VM if the TSC is not virtualized and the host␊
129␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
130␉ */␊
131␉for(i = 0; i < 10; ++i)␊
132␉{␊
133␉␉enable_PIT2();␊
134␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
135␉␉tscStart = rdtsc64();␊
136␉␉pollCount = poll_PIT2_gate();␊
137␉␉tscEnd = rdtsc64();␊
138␉␉/* The poll loop must have run at least a few times for accuracy */␊
139␉␉if (pollCount <= 1)␊
140␉␉{␊
141␉␉␉continue;␊
142␉␉}␊
143␉␉/* The TSC must increment at LEAST once every millisecond.␊
144␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
145␉␉ * be >= 30. Anything less and the processor is way too slow.␊
146␉␉ */␊
147␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
148␉␉{␊
149␉␉␉continue;␊
150␉␉}␊
151␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
152␉␉if ( (tscEnd - tscStart) < tscDelta )␊
153␉␉{␊
154␉␉␉tscDelta = tscEnd - tscStart;␊
155␉␉}␊
156␉}␊
157␉/* tscDelta is now the least number of TSC ticks the processor made in␊
158␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
159␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
160␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
161␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
162␉ * dividing by the milliseconds, we simply multiply by 1000.␊
163␉ */␊
164␊
165␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
166␉ * that we're going to multiply by 1000 first so we do need at least some␊
167␉ * arithmetic headroom. For now, 32-bit should be enough.␊
168␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
169␉ */␊
170␉if (tscDelta > (1ULL<<32))␊
171␉{␊
172␉␉retval = 0;␊
173␉}␊
174␉else␊
175␉{␊
176␉␉retval = tscDelta * 1000 / 30;␊
177␉}␊
178␉disable_PIT2();␊
179␉return retval;␊
180}␊
181␊
182static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
183#define RTC_FAST_DENOM␉0xFFFFFFFF␊
184␊
185inline static uint32_t␊
186create_mul_quant_GHZ(int shift, uint32_t quant)␊
187{␊
188␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
189}␊
190␊
191struct␉{␊
192␉mach_timespec_t␉␉␉calend_offset;␊
193␉boolean_t␉␉␉calend_is_set;␊
194␊
195␉int64_t␉␉␉␉calend_adjtotal;␊
196␉int32_t␉␉␉␉calend_adjdelta;␊
197␊
198␉uint32_t␉␉␉boottime;␊
199␊
200␉mach_timebase_info_data_t␉timebase_const;␊
201␊
202␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
203} rtclock;␊
204␊
205uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
206uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
207uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
208uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
209␊
210static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
211{␊
212␊
213␉if (cycles > (NSEC_PER_SEC/20))␊
214␉{␊
215␉␉// we can use just a "fast" multiply to get nanos␊
216␉␉rtc_quant_shift = 32;␊
217␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
218␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
219␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
220␉}␊
221␉else␊
222␉{␊
223␉␉rtc_quant_shift = 26;␊
224␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
225␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
226␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
227␉}␊
228␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
229␉// BUT we also want to calculate...␊
230␊
231␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
232 / UI_CPUFREQ_ROUNDING_FACTOR)␊
233␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
234␊
235␉/*␊
236␉ * Set current measured speed.␊
237␉ */␊
238␉if (cycles >= 0x100000000ULL)␊
239␉{␊
240␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
241␉}␊
242␉else␊
243␉{␊
244␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
245␉}␊
246␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
247␊
248␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
249␉return(rtc_cyc_per_sec);␊
250}␊
251␊
252// Bronya C1E fix␊
253static void post_startup_cpu_fixups(void)␊
254{␊
255␉/*␊
256␉ * Some AMD processors support C1E state. Entering this state will␊
257␉ * cause the local APIC timer to stop, which we can't deal with at␊
258␉ * this time.␊
259␉ */␊
260␊
261␉uint64_t reg;␊
262␉verbose("\tLooking to disable C1E if is already enabled by the BIOS:\n");␊
263␉reg = rdmsr64(MSR_AMD_INT_PENDING_CMP_HALT);␊
264␉/* Disable C1E state if it is enabled by the BIOS */␊
265␉if ((reg >> AMD_ACTONCMPHALT_SHIFT) & AMD_ACTONCMPHALT_MASK)␊
266␉{␊
267␉␉reg &= ~(AMD_ACTONCMPHALT_MASK << AMD_ACTONCMPHALT_SHIFT);␊
268␉␉wrmsr64(MSR_AMD_INT_PENDING_CMP_HALT, reg);␊
269␉␉verbose("\tC1E disabled!\n");␊
270␉}␊
271}␊
272␊
273/*␊
274 * Large memcpy() into MMIO space can take longer than 1 clock tick (55ms).␊
275 * The timer interrupt must remain responsive when updating VRAM so␊
276 * as not to miss timer interrupts during countdown().␊
277 *␊
278 * If interrupts are enabled, use normal memcpy.␊
279 *␊
280 * If interrupts are disabled, breaks memcpy down␊
281 * into 128K chunks, times itself and makes a bios␊
282 * real-mode call every 25 msec in order to service␊
283 * pending interrupts.␊
284 *␊
285 * -- zenith432, May 22nd, 2016␊
286 */␊
287void *memcpy_interruptible(void *dst, const void *src, size_t len)␊
288{␊
289␉uint64_t tscFreq, lastTsc;␊
290␉uint32_t eflags, threshold;␊
291␉ptrdiff_t offset;␊
292␉const size_t chunk = 131072U;␉// 128K␊
293␊
294␉if (len <= chunk)␊
295␉{␊
296␉␉/*␊
297␉␉ * Short memcpy - use normal.␊
298␉␉ */␊
299␉␉return memcpy(dst, src, len);␊
300␉}␊
301␊
302␉__asm__ volatile("pushfl; popl %0" : "=r"(eflags));␊
303␉if (eflags & 0x200U)␊
304␉{␊
305␉␉/*␊
306␉␉ * Interrupts are enabled - use normal memcpy.␊
307␉␉ */␊
308␉␉return memcpy(dst, src, len);␊
309␉}␊
310␊
311␉tscFreq = Platform.CPU.TSCFrequency;␊
312␉if ((uint32_t) (tscFreq >> 32))␊
313␉{␊
314␉␉/*␊
315␉␉ * If TSC Frequency >= 2 ** 32, use a default time threshold.␊
316␉␉ */␊
317␉␉threshold = (~0U) / 40U;␊
318␉}␊
319␉else if (!(uint32_t) tscFreq)␊
320␉{␊
321␉␉/*␊
322␉␉ * If early on and TSC Frequency hasn't been estimated yet,␊
323␉␉ * use normal memcpy.␊
324␉␉ */␊
325␉␉return memcpy(dst, src, len);␊
326␉}␊
327␉else␊
328␉{␊
329␉␉threshold = ((uint32_t) tscFreq) / 40U;␊
330␉}␊
331␊
332␉/*␊
333␉ * Do the work␊
334␉ */␊
335␉offset = 0;␊
336␉lastTsc = rdtsc64();␊
337␉do␊
338␉{␊
339␉␉(void) memcpy((char*) dst + offset, (const char*) src + offset, chunk);␊
340␉␉offset += (ptrdiff_t) chunk;␊
341␉␉len -= chunk;␊
342␉␉if ((rdtsc64() - lastTsc) < threshold)␊
343␉␉{␊
344␉␉␉continue;␊
345␉␉}␊
346␉␉(void) readKeyboardStatus();␉// visit real-mode␊
347␉␉lastTsc = rdtsc64();␊
348␉}␊
349␉while (len > chunk);␊
350␉if (len)␊
351␉{␊
352␉␉(void) memcpy((char*) dst + offset, (const char*) src + offset, len);␊
353␉}␊
354␉return dst;␊
355}␊
356␊
357/*␊
358 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
359 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
360 *␉ a max multi. (used to calculate the FSB freq.),␊
361 *␉ and a current multi. (used to calculate the CPU freq.)␊
362 * - busFrequency = tscFrequency / multi␊
363 * - cpuFrequency = busFrequency * multi␊
364 */␊
365␊
366/* Decimal powers: */␊
367#define kilo (1000ULL)␊
368#define Mega (kilo * kilo)␊
369#define Giga (kilo * Mega)␊
370#define Tera (kilo * Giga)␊
371#define Peta (kilo * Tera)␊
372␊
373#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
374␊
375void get_cpuid(PlatformInfo_t *p)␊
376{␊
377␊
378␉char␉␉str[128];␊
379␉uint32_t␉reg[4];␊
380␉char␉␉*s␉␉␉= 0;␊
381␊
382␊
383␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
384␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
385␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
386␊
387␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
388␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); // Get the max extended cpuid␊
389␊
390␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
391␉{␊
392␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
393␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
394␉}␊
395␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
396␉{␊
397␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
398␉}␊
399␊
400// ==============================================================␊
401␊
402␉/* get BrandString (if supported) */␊
403␉/* Copyright: from Apple's XNU cpuid.c */␊
404␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
405␉{␊
406␉␉bzero(str, 128);␊
407␉␉/*␊
408␉␉ * The BrandString 48 bytes (max), guaranteed to␊
409␉␉ * be NULL terminated.␊
410␉␉ */␊
411␉␉do_cpuid(0x80000002, reg); // Processor Brand String␊
412␉␉memcpy(&str[0], (char *)reg, 16);␊
413␊
414␊
415␉␉do_cpuid(0x80000003, reg); // Processor Brand String␊
416␉␉memcpy(&str[16], (char *)reg, 16);␊
417␉␉do_cpuid(0x80000004, reg); // Processor Brand String␊
418␉␉memcpy(&str[32], (char *)reg, 16);␊
419␉␉for (s = str; *s != '\0'; s++)␊
420␉␉{␊
421␉␉␉if (*s != ' ')␊
422␉␉␉{␊
423␉␉␉␉break;␊
424␉␉␉}␊
425␉␉}␊
426␉␉strlcpy(p->CPU.BrandString, s, 48);␊
427␊
428␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
429␉␉{␊
430␉␉␉/*␊
431␉␉␉ * This string means we have a firmware-programmable brand string,␊
432␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
433␉␉␉ */␊
434␉␉␉p->CPU.BrandString[0] = '\0';␊
435␉␉}␊
436␉␉p->CPU.BrandString[47] = '\0';␊
437//␉␉DBG("\tBrandstring = %s\n", p->CPU.BrandString);␊
438␉}␊
439␊
440// ==============================================================␊
441␊
442␉switch(p->CPU.BrandString[0])␊
443␉{␊
444␉␉case 'A':␊
445␉␉␉/* AMD Processors */␊
446␉␉␉// The cache information is only in ecx and edx so only save␊
447␉␉␉// those registers␊
448␊
449␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
450␊
451␉␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
452␉␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
453␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
454␊
455␉␉␉break;␊
456␊
457␉␉case 'G':␊
458␉␉␉/* Intel Processors */␊
459␉␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); // Cache Index for Inte␊
460␊
461␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
462␉␉␉{␊
463␉␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
464␉␉␉}␊
465␊
466␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
467␉␉␉{␊
468␉␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
469␉␉␉}␊
470␊
471␉␉␉break;␊
472␉}␊
473}␊
474␊
475void scan_cpu(PlatformInfo_t *p)␊
476{␊
477␉verbose("[ CPU INFO ]\n");␊
478␉get_cpuid(p);␊
479␊
480␉uint64_t␉busFCvtt2n;␊
481␉uint64_t␉tscFCvtt2n;␊
482␉uint64_t␉tscFreq␉␉␉= 0;␊
483␉uint64_t␉busFrequency␉␉= 0;␊
484␉uint64_t␉cpuFrequency␉␉= 0;␊
485␉uint64_t␉msr␉␉␉= 0;␊
486␉uint64_t␉flex_ratio␉␉= 0;␊
487␉uint64_t␉cpuid_features;␊
488␊
489␉uint32_t␉max_ratio␉␉= 0;␊
490␉uint32_t␉min_ratio␉␉= 0;␊
491␉uint32_t␉reg[4];␊
492␉uint32_t␉cores_per_package␉= 0;␊
493␉uint32_t␉logical_per_package␉= 1;␊
494␉uint32_t␉threads_per_core␉= 1;␊
495␊
496␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
497␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
498␉uint8_t␉␉currdiv␉␉␉= 0;␊
499␉uint8_t␉␉currcoef␉␉= 0;␊
500␉uint8_t␉␉maxdiv␉␉␉= 0;␊
501␉uint8_t␉␉maxcoef␉␉␉= 0;␊
502␉uint8_t␉␉pic0_mask;␊
503␉uint8_t␉␉cpuMultN2␉␉= 0;␊
504␊
505␉const char␉*newratio;␊
506␊
507␉int␉␉len␉␉␉= 0;␊
508␉int␉␉myfsb␉␉␉= 0;␊
509␉int␉␉i␉␉␉= 0;␊
510␊
511␊
512/* http://www.flounder.com/cpuid_explorer2.htm␊
513 EAX (Intel):␊
514 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
515 +--------+----------------+--------+----+----+--------+--------+--------+␊
516 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
517 +--------+----------------+--------+----+----+--------+--------+--------+␊
518␊
519 EAX (AMD):␊
520 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
521 +--------+----------------+--------+----+----+--------+--------+--------+␊
522 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
523 +--------+----------------+--------+----+----+--------+--------+--------+␊
524*/␊
525␉///////////////////-- MaxFn,Vendor --////////////////////////␊
526␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
527␊
528␉///////////////////-- Signature, stepping, features -- //////␊
529␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊
530␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
531␉{␊
532␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
533␉}␊
534␉else␊
535␉{␊
536␉␉logical_per_package = 1;␊
537␉}␊
538␊
539␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
540␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
541␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
542␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
543␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
544␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
545␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
546␊
547␉if (p->CPU.Family == 0x0f)␊
548␉{␊
549␉␉p->CPU.Family += p->CPU.ExtFamily;␊
550␉}␊
551␊
552␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
553␉{␊
554␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
555␉}␊
556␊
557␉switch (p->CPU.Vendor)␊
558␉{␊
559␉␉case CPUID_VENDOR_INTEL:␊
560␉␉{␊
561␉␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
562␉␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
563␉␉␉{␊
564␉␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
565␉␉␉␉{␊
566␉␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
567␉␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
568␉␉␉␉␉{␊
569␉␉␉␉␉␉break;␊
570␉␉␉␉␉}␊
571␉␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
572␉␉␉␉}␊
573␉␉␉}␊
574␊
575␉␉␉if (i > 0)␊
576␉␉␉{␊
577␉␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
578␉␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
579␉␉␉}␊
580␊
581␉␉␉if (cores_per_package == 0)␊
582␉␉␉{␊
583␉␉␉␉cores_per_package = 1;␊
584␉␉␉}␊
585␊
586␉␉␉switch (p->CPU.Model)␊
587␉␉␉{␊
588␉␉␉␉case CPUID_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)␊
589␉␉␉␉case CPUID_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)␊
590␉␉␉␉case CPUID_MODEL_CLARKDALE: // Intel Core i3, i5, i7 LGA1156 (32nm)␊
591␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
592␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
593␉␉␉␉case CPUID_MODEL_SANDYBRIDGE: // 0x2A␊
594␉␉␉␉case CPUID_MODEL_IVYBRIDGE: // 0x3A␊
595␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:// 0x3E␊
596␉␉␉␉case CPUID_MODEL_HASWELL_U5: // 0x3D␊
597␉␉␉␉case CPUID_MODEL_HASWELL: // 0x3C␊
598␉␉␉␉case CPUID_MODEL_HASWELL_SVR: // 0x3F␊
599␉␉␉␉case CPUID_MODEL_HASWELL_ULT: // 0x45␊
600␉␉␉␉case CPUID_MODEL_HASWELL_ULX: // 0x46␊
601␉␉␉␉case CPUID_MODEL_BROADWELL_HQ: // 0x47␊
602␉␉␉␉case CPUID_MODEL_BRASWELL:␉// 0x4C␊
603␉␉␉␉case CPUID_MODEL_AVOTON: // 0x4D␊
604␉␉␉␉case CPUID_MODEL_SKYLAKE: // 0x4E␊
605␉␉␉␉case CPUID_MODEL_BRODWELL_SVR: // 0x4F␊
606␉␉␉␉case CPUID_MODEL_BRODWELL_MSVR: // 0x56␊
607␉␉␉␉case CPUID_MODEL_KNIGHT: // 0x57␊
608␉␉␉␉case CPUID_MODEL_ANNIDALE: // 0x5A␊
609␉␉␉␉case CPUID_MODEL_GOLDMONT: // 0x5C␊
610␉␉␉␉case CPUID_MODEL_VALLEYVIEW: // 0x5D␊
611␉␉␉␉case CPUID_MODEL_SKYLAKE_S: // 0x5E␊
612␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX: // 0x55␊
613␉␉␉␉case CPUID_MODEL_CANNONLAKE: // 0x66␊
614␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊
615␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
616␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
617␉␉␉␉␉break;␊
618␊
619␉␉␉␉case CPUID_MODEL_DALES:␊
620␉␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊
621␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
622␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
623␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
624␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
625␉␉␉␉␉break;␊
626␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
627␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
628␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
629␉␉␉␉␉break;␊
630␉␉␉␉case CPUID_MODEL_ATOM:␊
631␉␉␉␉␉p->CPU.NoCores␉␉= 2;␊
632␉␉␉␉␉p->CPU.NoThreads␉= 2;␊
633␉␉␉␉␉break;␊
634␉␉␉␉default:␊
635␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
636␉␉␉␉␉break;␊
637␉␉␉}␊
638␊
639␉␉␉// workaround for Xeon Harpertown and Yorkfield␊
640␉␉␉if ((p->CPU.Model == CPUID_MODEL_PENRYN) &&␊
641␉␉␉␉(p->CPU.NoCores␉== 0))␊
642␉␉␉{␊
643␉␉␉␉if ((strstr(p->CPU.BrandString, "X54")) ||␊
644␉␉␉␉␉(strstr(p->CPU.BrandString, "E54")) ||␊
645␉␉␉␉␉(strstr(p->CPU.BrandString, "W35")) ||␊
646␉␉␉␉␉(strstr(p->CPU.BrandString, "X34")) ||␊
647␉␉␉␉␉(strstr(p->CPU.BrandString, "X33")) ||␊
648␉␉␉␉␉(strstr(p->CPU.BrandString, "L33")) ||␊
649␉␉␉␉␉(strstr(p->CPU.BrandString, "X32")) ||␊
650␉␉␉␉␉(strstr(p->CPU.BrandString, "L3426")) ||␊
651␉␉␉␉␉(strstr(p->CPU.BrandString, "L54")))␊
652␉␉␉␉{␊
653␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
654␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
655␉␉␉␉} else if (strstr(p->CPU.BrandString, "W36")) {␊
656␉␉␉␉␉p->CPU.NoCores␉␉= 6;␊
657␉␉␉␉␉p->CPU.NoThreads␉= 6;␊
658␉␉␉␉} else { //other Penryn and Wolfdale␊
659␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
660␉␉␉␉␉p->CPU.NoThreads␉= 0;␊
661␉␉␉␉}␊
662␉␉␉}␊
663␊
664␉␉␉if (p->CPU.NoCores == 0)␊
665␉␉␉{␊
666␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
667␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
668␉␉␉}␊
669␊
670␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊
671␉␉␉// workaround for N270. I don't know why it detected wrong␊
672␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
673␉␉␉{␊
674␉␉␉␉p->CPU.NoCores␉␉= 1;␊
675␉␉␉␉p->CPU.NoThreads␉= 2;␊
676␉␉␉}␊
677␊
678␉␉␉// workaround for Quad␊
679␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
680␉␉␉{␊
681␉␉␉␉p->CPU.NoCores␉␉= 4;␊
682␉␉␉␉p->CPU.NoThreads␉= 4;␊
683␉␉␉}␊
684␉␉}␊
685␊
686␉␉break;␊
687␊
688␉␉case CPUID_VENDOR_AMD:␊
689␉␉{␊
690␉␉␉post_startup_cpu_fixups();␊
691␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
692␉␉␉threads_per_core = cores_per_package;␊
693␊
694␉␉␉if (cores_per_package == 0)␊
695␉␉␉{␊
696␉␉␉␉cores_per_package = 1;␊
697␉␉␉}␊
698␊
699␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
700␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
701␊
702␉␉␉if (p->CPU.NoCores == 0)␊
703␉␉␉{␊
704␉␉␉␉p->CPU.NoCores = 1;␊
705␉␉␉␉p->CPU.NoThreads␉= 1;␊
706␉␉␉}␊
707␉␉}␊
708␉␉break;␊
709␊
710␉␉default :␊
711␉␉␉stop("Unsupported CPU detected! System halted.");␊
712␉}␊
713␊
714␉/* setup features */␊
715␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
716␉{␊
717␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
718␉}␊
719␊
720␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
721␉{␊
722␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
723␉}␊
724␊
725␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
726␉{␊
727␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
728␉}␊
729␊
730␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
731␉{␊
732␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
733␉}␊
734␊
735␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
736␉{␊
737␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
738␉}␊
739␊
740␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
741␉{␊
742␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
743␉}␊
744␊
745␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
746␉{␊
747␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
748␉}␊
749␊
750␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
751␉{␊
752␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
753␉}␊
754␊
755␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
756␉{␊
757␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
758␉}␊
759␊
760␉pic0_mask = inb(0x21U);␊
761␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
762␊
763␉uint64_t cycles;␊
764␉cycles = timeRDTSC();␊
765␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
766␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
767␉// if usual method failed␊
768␉if ( tscFreq < 1000 )␉//TEST␊
769␉{␊
770␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
771␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
772␉}␊
773␊
774␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
775␉{␊
776␉␉int intelCPU = p->CPU.Model;␊
777␉␉if (p->CPU.Family == 0x06)␊
778␉␉{␊
779␉␉␉/* Nehalem CPU model */␊
780␉␉␉switch (p->CPU.Model)␊
781␉␉␉{␊
782␉␉␉␉case CPUID_MODEL_NEHALEM:␊
783␉␉␉␉case CPUID_MODEL_FIELDS:␊
784␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
785␉␉␉␉case CPUID_MODEL_DALES:␊
786␉␉␉␉case CPUID_MODEL_WESTMERE:␊
787␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
788␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
789/* --------------------------------------------------------- */␊
790␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
791␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
792␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
793␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
794␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
795␉␉␉␉case CPUID_MODEL_HASWELL:␊
796␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
797␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
798␊
799␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
800␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
801␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊
802␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊
803/* --------------------------------------------------------- */␊
804␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
805␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
806␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
807␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
808␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
809␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
810␉␉␉␉␉if (bitfield(msr, 16, 16))␊
811␉␉␉␉␉{␊
812␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
813␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
814␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
815␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
816␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
817␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
818␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
819␉␉␉␉␉␉// is inadvertently set to 0.␊
820␊
821␉␉␉␉␉␉if (flex_ratio == 0)␊
822␉␉␉␉␉␉{␊
823␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
824␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
825␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
826␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
827␉␉␉␉␉␉}␊
828␉␉␉␉␉␉else␊
829␉␉␉␉␉␉{␊
830␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
831␉␉␉␉␉␉␉{␊
832␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
833␉␉␉␉␉␉␉}␊
834␉␉␉␉␉␉}␊
835␉␉␉␉␉}␊
836␊
837␉␉␉␉␉if (bus_ratio_max)␊
838␉␉␉␉␉{␊
839␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
840␉␉␉␉␉}␊
841␊
842␉␉␉␉␉//valv: Turbo Ratio Limit␊
843␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
844␉␉␉␉␉{␊
845␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
846␊
847␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
848␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
849␉␉␉␉␉}␊
850␉␉␉␉␉else␊
851␉␉␉␉␉{␊
852␉␉␉␉␉␉cpuFrequency = tscFreq;␊
853␉␉␉␉␉}␊
854␊
855␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
856␉␉␉␉␉{␊
857␉␉␉␉␉␉max_ratio = atoi(newratio);␊
858␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
859␉␉␉␉␉␉if (len >= 3)␊
860␉␉␉␉␉␉{␊
861␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
862␉␉␉␉␉␉}␊
863␊
864␉␉␉␉␉␉verbose("\tBus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
865␊
866␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
867␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
868␉␉␉␉␉␉{␊
869␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
870␉␉␉␉␉␉␉if (len >= 3)␊
871␉␉␉␉␉␉␉{␊
872␉␉␉␉␉␉␉␉maxdiv = 1;␊
873␉␉␉␉␉␉␉}␊
874␉␉␉␉␉␉␉else␊
875␉␉␉␉␉␉␉{␊
876␉␉␉␉␉␉␉␉maxdiv = 0;␊
877␉␉␉␉␉␉␉}␊
878␉␉␉␉␉␉}␊
879␉␉␉␉␉␉else␊
880␉␉␉␉␉␉{␊
881␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
882␉␉␉␉␉␉}␊
883␉␉␉␉␉}␊
884␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
885␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
886␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
887␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
888␊
889␉␉␉␉myfsb = busFrequency / 1000000;␊
890␉␉␉␉verbose("\tSticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
891␉␉␉␉currcoef = bus_ratio_max;␊
892␊
893␉␉␉␉break;␊
894␊
895␉␉␉default:␊
896␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
897␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
898␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
899␉␉␉␉// Non-integer bus ratio for the max-multi␊
900␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
901␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
902␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
903␊
904␉␉␉␉// This will always be model >= 3␊
905␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
906␉␉␉␉{␊
907␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
908␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
909␉␉␉␉}␊
910␉␉␉␉else␊
911␉␉␉␉{␊
912␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
913␉␉␉␉␉// XXX␊
914␉␉␉␉␉maxcoef = currcoef;␊
915␉␉␉␉}␊
916␊
917␉␉␉␉if (!currcoef)␊
918␉␉␉␉{␊
919␉␉␉␉␉currcoef = maxcoef;␊
920␉␉␉␉}␊
921␊
922␉␉␉␉if (maxcoef)␊
923␉␉␉␉{␊
924␉␉␉␉␉if (maxdiv)␊
925␉␉␉␉␉{␊
926␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
927␉␉␉␉␉}␊
928␉␉␉␉␉else␊
929␉␉␉␉␉{␊
930␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
931␉␉␉␉␉}␊
932␊
933␉␉␉␉␉if (currdiv)␊
934␉␉␉␉␉{␊
935␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
936␉␉␉␉␉}␊
937␉␉␉␉␉else␊
938␉␉␉␉␉{␊
939␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
940␉␉␉␉␉}␊
941␊
942␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
943␉␉␉␉}␊
944␉␉␉␉break;␊
945␉␉␉}␊
946␉␉}␊
947␉␉// Mobile CPU␊
948␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
949␉␉{␊
950␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
951␉␉}␊
952␉}␊
953␊
954␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
955␉{␊
956␉␉switch(p->CPU.Family)␊
957␉␉{␊
958␉␉␉case 0xF: /* K8 */␊
959␉␉␉{␊
960␉␉␉␉uint64_t fidvid = 0;␊
961␉␉␉␉uint64_t cpuMult;␊
962␉␉␉␉uint64_t fid;␊
963␊
964␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
965␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
966␊
967␉␉␉␉cpuMult = (fid + 8) / 2;␊
968␉␉␉␉currcoef = cpuMult;␊
969␊
970␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
971␉␉␉␉currdiv = cpuMultN2;␊
972␉␉␉␉/****** Addon END ******/␊
973␉␉␉}␊
974␉␉␉␉break;␊
975␊
976␉␉␉case 0x10: /*** AMD Family 10h ***/␊
977␉␉␉{␊
978␉␉␉␉uint64_t cofvid = 0;␊
979␉␉␉␉uint64_t cpuMult;␊
980␉␉␉␉uint64_t divisor = 0;␊
981␉␉␉␉uint64_t did;␊
982␉␉␉␉uint64_t fid;␊
983␊
984␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
985␉␉␉␉did = bitfield(cofvid, 8, 6);␊
986␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
987␉␉␉␉if (did == 0) divisor = 2;␊
988␉␉␉␉else if (did == 1) divisor = 4;␊
989␉␉␉␉else if (did == 2) divisor = 8;␊
990␉␉␉␉else if (did == 3) divisor = 16;␊
991␉␉␉␉else if (did == 4) divisor = 32;␊
992␊
993␉␉␉␉cpuMult = (fid + 16) / divisor;␊
994␉␉␉␉currcoef = cpuMult;␊
995␊
996␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
997␉␉␉␉currdiv = cpuMultN2;␊
998␊
999␉␉␉␉/****** Addon END ******/␊
1000␉␉␉}␊
1001␉␉␉break;␊
1002␊
1003␉␉␉case 0x11: /*** AMD Family 11h ***/␊
1004␉␉␉{␊
1005␉␉␉␉uint64_t cofvid = 0;␊
1006␉␉␉␉uint64_t cpuMult;␊
1007␉␉␉␉uint64_t divisor = 0;␊
1008␉␉␉␉uint64_t did;␊
1009␉␉␉␉uint64_t fid;␊
1010␊
1011␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1012␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1013␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1014␉␉␉␉if (did == 0) divisor = 2;␊
1015␉␉␉␉else if (did == 1) divisor = 4;␊
1016␉␉␉␉else if (did == 2) divisor = 8;␊
1017␉␉␉␉else if (did == 3) divisor = 16;␊
1018␉␉␉␉else if (did == 4) divisor = 32;␊
1019␊
1020␉␉␉␉cpuMult = (fid + 8) / divisor;␊
1021␉␉␉␉currcoef = cpuMult;␊
1022␊
1023␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1024␉␉␉␉currdiv = cpuMultN2;␊
1025␊
1026␉␉␉␉/****** Addon END ******/␊
1027␉␉␉}␊
1028 break;␊
1029␊
1030␉␉␉case 0x12: /*** AMD Family 12h ***/␊
1031␉␉␉{␊
1032␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
1033␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
1034␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
1035␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1036␊
1037␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
1038␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
1039␉␉␉␉uint64_t divisor;␊
1040␉␉␉␉switch (CpuDid)␊
1041␉␉␉␉{␊
1042␉␉␉␉␉case 0: divisor = 1; break;␊
1043␉␉␉␉␉case 1: divisor = (3/2); break;␊
1044␉␉␉␉␉case 2: divisor = 2; break;␊
1045␉␉␉␉␉case 3: divisor = 3; break;␊
1046␉␉␉␉␉case 4: divisor = 4; break;␊
1047␉␉␉␉␉case 5: divisor = 6; break;␊
1048␉␉␉␉␉case 6: divisor = 8; break;␊
1049␉␉␉␉␉case 7: divisor = 12; break;␊
1050␉␉␉␉␉case 8: divisor = 16; break;␊
1051␉␉␉␉␉default: divisor = 1; break;␊
1052␉␉␉␉}␊
1053␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
1054␊
1055␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
1056␉␉␉␉currdiv = cpuMultN2;␊
1057␊
1058␉␉␉}␊
1059␉␉␉␉break;␊
1060␊
1061␉␉␉case 0x14: /* K14 */␊
1062␊
1063␉␉␉{␊
1064␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
1065␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
1066␉␉␉␉uint64_t prfsts;␊
1067␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1068␊
1069␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
1070␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
1071␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
1072␊
1073␉␉␉␉uint64_t frequencyId = 0x10;␊
1074␉␉␉␉currcoef = (frequencyId + 0x10) /␊
1075␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
1076␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
1077␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
1078␊
1079␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
1080␉␉␉␉currdiv = cpuMultN2;␊
1081␉␉␉}␊
1082␊
1083␉␉␉␉break;␊
1084␊
1085␉␉␉case 0x15: /*** AMD Family 15h ***/␊
1086␉␉␉case 0x06: /*** AMD Family 06h ***/␊
1087␉␉␉{␊
1088␊
1089␉␉␉␉uint64_t cofvid = 0;␊
1090␉␉␉␉uint64_t cpuMult;␊
1091␉␉␉␉uint64_t divisor = 0;␊
1092␉␉␉␉uint64_t did;␊
1093␉␉␉␉uint64_t fid;␊
1094␊
1095␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1096␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1097␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1098␉␉␉␉if (did == 0) divisor = 2;␊
1099␉␉␉␉else if (did == 1) divisor = 4;␊
1100␉␉␉␉else if (did == 2) divisor = 8;␊
1101␉␉␉␉else if (did == 3) divisor = 16;␊
1102␉␉␉␉else if (did == 4) divisor = 32;␊
1103␊
1104␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1105␉␉␉␉currcoef = cpuMult;␊
1106␊
1107␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1108␉␉␉␉currdiv = cpuMultN2;␊
1109␉␉␉}␊
1110␉␉␉␉break;␊
1111␊
1112␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
1113␉␉␉{␊
1114␉␉␉␉uint64_t cofvid = 0;␊
1115␉␉␉␉uint64_t cpuMult;␊
1116␉␉␉␉uint64_t divisor = 0;␊
1117␉␉␉␉uint64_t did;␊
1118␉␉␉␉uint64_t fid;␊
1119␊
1120␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
1121␉␉␉␉did = bitfield(cofvid, 8, 6);␊
1122␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
1123␉␉␉␉if (did == 0) divisor = 1;␊
1124␉␉␉␉else if (did == 1) divisor = 2;␊
1125␉␉␉␉else if (did == 2) divisor = 4;␊
1126␉␉␉␉else if (did == 3) divisor = 8;␊
1127␉␉␉␉else if (did == 4) divisor = 16;␊
1128␊
1129␉␉␉␉cpuMult = (fid + 16) / divisor;␊
1130␉␉␉␉currcoef = cpuMult;␊
1131␊
1132␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
1133␉␉␉␉currdiv = cpuMultN2;␊
1134␉␉␉␉/****** Addon END ******/␊
1135␉␉␉}␊
1136␉␉␉␉break;␊
1137␊
1138␉␉␉default:␊
1139␉␉␉{␊
1140␉␉␉␉typedef unsigned long long vlong;␊
1141␉␉␉␉uint64_t prfsts;␊
1142␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
1143␉␉␉␉uint64_t r;␊
1144␉␉␉␉vlong hz;␊
1145␉␉␉␉r = (prfsts>>6) & 0x07;␊
1146␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
1147␊
1148␉␉␉␉currcoef = hz / (200 * Mega);␊
1149␉␉␉}␊
1150␉␉}␊
1151␊
1152␉␉if (currcoef)␊
1153␉␉{␊
1154␉␉␉if (currdiv)␊
1155␉␉␉{␊
1156␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
1157␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1158␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
1159␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1160␊
1161␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
1162␉␉␉}␊
1163␉␉␉else␊
1164␉␉␉{␊
1165␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1166␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1167␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1168␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1169␉␉␉␉DBG("%d\n", currcoef);␊
1170␉␉␉}␊
1171␉␉}␊
1172␉␉else if (!cpuFrequency)␊
1173␉␉{␊
1174␉␉␉cpuFrequency = tscFreq;␊
1175␉␉}␊
1176␉}␊
1177␊
1178#if 0␊
1179␉if (!busFrequency)␊
1180␉{␊
1181␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1182␉␉DBG("\tCPU: busFrequency = 0! using the default value for FSB!\n");␊
1183␉␉cpuFrequency = tscFreq;␊
1184␉}␊
1185␊
1186␉DBG("\tcpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1187␊
1188#endif␊
1189␊
1190␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
1191␊
1192␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1193␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1194␉p->CPU.CurrCoef = currcoef;␊
1195␉p->CPU.CurrDiv = currdiv;␊
1196␉p->CPU.TSCFrequency = tscFreq;␊
1197␉p->CPU.FSBFrequency = busFrequency;␊
1198␉p->CPU.CPUFrequency = cpuFrequency;␊
1199␊
1200␉// keep formatted with spaces instead of tabs␊
1201␊
1202␉DBG("\tCPUID Raw Values:\n");␊
1203␉for (i = 0; i < CPUID_MAX; i++)␊
1204␉{␊
1205␉␉DBG("\t%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1206␉}␊
1207␉DBG("\n");␊
1208␉DBG("\tBrand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1209␉DBG("\tVendor: 0x%X\n",␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1210␉DBG("\tFamily: 0x%X\n",␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1211␉DBG("\tExtFamily: 0x%X\n",␉p->CPU.ExtFamily);␊
1212␉DBG("\tSignature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1213␉/*switch (p->CPU.Type) {␊
1214␉␉case PT_OEM:␊
1215␉␉␉DBG("\tProcessor type: Intel Original OEM Processor\n");␊
1216␉␉␉break;␊
1217␉␉case PT_OD:␊
1218␉␉␉DBG("\tProcessor type: Intel Over Drive Processor\n");␊
1219␉␉␉break;␊
1220␉␉case PT_DUAL:␊
1221␉␉␉DBG("\tProcessor type: Intel Dual Processor\n");␊
1222␉␉␉break;␊
1223␉␉case PT_RES:␊
1224␉␉␉DBG("\tProcessor type: Intel Reserved\n");␊
1225␉␉␉break;␊
1226␉␉default:␊
1227␉␉␉break;␊
1228␉}*/␊
1229␉DBG("\tModel: 0x%X\n",␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1230␉DBG("\tExtModel: 0x%X\n",␉p->CPU.ExtModel);␊
1231␉DBG("\tStepping: 0x%X\n",␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1232␉DBG("\tMaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1233␉DBG("\tCurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1234␉DBG("\tMaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1235␉DBG("\tCurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1236␉DBG("\tTSCFreq: %dMHz\n",␉p->CPU.TSCFrequency / 1000000);␊
1237␉DBG("\tFSBFreq: %dMHz\n",␉(p->CPU.FSBFrequency + 500000) / 1000000);␊
1238␉DBG("\tCPUFreq: %dMHz\n",␉p->CPU.CPUFrequency / 1000000);␊
1239␉DBG("\tCores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1240␉DBG("\tLogical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1241␉DBG("\tFeatures: 0x%08x\n",␉p->CPU.Features);␊
1242//␉DBG("\tMicrocode version: %d\n",␉␉p->CPU.MCodeVersion);␉␉// CPU microcode version␊
1243␊
1244␉verbose("\n");␊
1245#if DEBUG_CPU␊
1246␉pause();␊
1247#endif␊
1248}␊
1249

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