Chameleon

Chameleon Svn Source Tree

Root/branches/ErmaC/Enoch/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12␉#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16␉#define DBG(x...)␉printf(x)␊
17#else␊
18␉#define DBG(x...)␊
19#endif␊
20␊
21#define XEON "Xeon"␊
22#define CORE_M "Core(TM) M"␊
23#define CORE_M3 "Core(TM) m3"␊
24#define CORE_M5 "Core(TM) m5"␊
25#define CORE_M7 "Core(TM) m7"␊
26#define CORE_I3 "Core(TM) i3"␊
27#define CORE_I5 "Core(TM) i5"␊
28#define CORE_I7 "Core(TM) i7"␊
29␊
30bool getProcessorInformationExternalClock(returnType *value)␊
31{␊
32␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
33␉{␊
34␉␉switch (Platform.CPU.Family)␊
35␉␉{␊
36␉␉␉case 0x06:␊
37␉␉␉␉switch (Platform.CPU.Model)␊
38␉␉␉␉{␊
39␉␉␉␉␉// set external clock to 0 for SANDY␊
40␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
41␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
42␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
43␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
44␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
45␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
46␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
47␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
48␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
49␊
50␉␉␉␉␉␉value->word = 0;␊
51␉␉␉␉␉␉break;␊
52␉␉␉␉␉default:␊
53␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
54␉␉␉␉␉␉break;␊
55␉␉␉␉}␊
56␉␉␉␉break;␊
57␊
58␉␉␉default:␊
59␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
60␉␉␉␉break;␊
61␉␉}␊
62␉}␊
63␉else␊
64␉{␊
65␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
66␉}␊
67␊
68␉return true;␊
69}␊
70␊
71bool getProcessorInformationMaximumClock(returnType *value)␊
72{␊
73␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
74␉return true;␊
75}␊
76␊
77bool getSMBOemProcessorBusSpeed(returnType *value)␊
78{␊
79␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
80␉{␊
81␉␉switch (Platform.CPU.Family)␊
82␉␉{␊
83␉␉␉case 0x06:␊
84␉␉␉␉switch (Platform.CPU.Model)␊
85␉␉␉␉{␊
86␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
87␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
88␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
89␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
90␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
91␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
92␉␉␉␉␉␉return false;␊
93␊
94␉␉␉␉␉case 0x19:␊
95␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
96␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
97␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
98␉␉␉␉␉case CPUID_MODEL_DALES:␉// Intel Core i3, i5 LGA1156 (32nm)␊
99␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
100␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
101␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
102␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
103␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
104␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
105␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
106␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
107␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
108␉␉␉␉␉{␊
109␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
110␉␉␉␉␉␉int nhm_bus = 0x3F;␊
111␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
112␉␉␉␉␉␉unsigned long did, vid;␊
113␉␉␉␉␉␉unsigned long qpimult, qpibusspeed = 0;␊
114␉␉␉␉␉␉int i;␊
115␉␉␉␉␉␉␊
116␉␉␉␉␉␉// Nehalem supports Scrubbing␊
117␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
118␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
119␉␉␉␉␉␉{␊
120␉␉␉␉␉␉␉vid = (pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00) & 0xFFFF);␊
121␉␉␉␉␉␉␉did = (pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02) & 0xFF00);␊
122␉␉␉␉␉␉␉␊
123␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
124␉␉␉␉␉␉␉{␊
125␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
126␉␉␉␉␉␉␉}␊
127␉␉␉␉␉␉}␊
128␊
129␉␉␉␉␉␉qpimult = (pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50) & 0x7F);␊
130␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
131␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
132␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
133␉␉␉␉␉␉if (qpibusspeed % 100 != 0)␊
134␉␉␉␉␉␉{␊
135␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed + 50) / 100) * 100;␊
136␉␉␉␉␉␉}␊
137␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
138␉␉␉␉␉␉value->word = qpibusspeed;␊
139␉␉␉␉␉␉return true;␊
140␉␉␉␉␉}␊
141␉␉␉␉␉break;␊
142␊
143␉␉␉␉␉default:␊
144␉␉␉␉␉␉break;␊
145␉␉␉␉}␊
146␉␉␉␉break;␊
147␊
148␉␉␉default:␊
149␉␉␉␉break;␊
150␉␉}␊
151␉}␊
152␊
153␉return false; //Unsupported CPU type␊
154}␊
155␊
156//bool getSMBOemPlatformFeature(returnType *value)␊
157//{␊
158// value->word = (uint64_t)(0x0000000000000001);␊
159// return true;␊
160//}␊
161␊
162uint16_t simpleGetSMBOemProcessorType(void)␊
163{␊
164␉if (Platform.CPU.NoCores >= 4)␊
165␉{␊
166␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊
167␉}␊
168␉else if (Platform.CPU.NoCores == 1)␊
169␉{␊
170␉␉return 0x201;␉// 513 - Core Duo␊
171␉};␊
172␉␊
173␉return 0x301;␉␉// 769 - Core 2 Duo␊
174}␊
175␊
176bool getSMBOemProcessorType(returnType *value)␊
177{␊
178␉static bool done = false;␊
179␊
180␉value->word = simpleGetSMBOemProcessorType();␊
181␊
182␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
183␉{␊
184␉␉if (!done)␊
185␉␉{␊
186␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
187␉␉␉done = true;␊
188␉␉}␊
189␊
190␉␉switch (Platform.CPU.Family)␊
191␉␉{␊
192␉␉␉case 0x0F:␊
193␉␉␉case 0x06:␊
194␊
195␉␉␉␉switch (Platform.CPU.Model)␊
196␉␉␉␉{␊
197␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
198␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
199␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
200␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
201␊
202␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
203␉␉␉␉␉␉{␊
204␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
205␉␉␉␉␉␉␉return true;␊
206␉␉␉␉␉␉}␊
207␊
208␉␉␉␉␉␉return true;␊
209␊
210␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
211␉␉␉␉␉case CPUID_MODEL_CONROE:␊
212␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
213␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
214␉␉␉␉␉␉return true;␊
215␊
216␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
217␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
218␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
219␊
220␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
221␉␉␉␉␉␉{␊
222␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
223␉␉␉␉␉␉␉return true;␊
224␉␉␉␉␉␉}␊
225␊
226␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
227␉␉␉␉␉␉{␊
228␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
229␉␉␉␉␉␉␉return true;␊
230␉␉␉␉␉␉}␊
231␉␉␉␉␉␉else␊
232␉␉␉␉␉␉{␊
233␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
234␉␉␉␉␉␉␉return true;␊
235␉␉␉␉␉␉}␊
236␊
237␉␉␉␉␉␉return true;␊
238␊
239␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
240␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
241␊
242␉␉␉␉␉␉return true;␊
243␊
244␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
245␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
246␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
247␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
248␊
249␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
250␉␉␉␉␉␉{␊
251␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
252␉␉␉␉␉␉␉return true;␊
253␉␉␉␉␉␉}␊
254␊
255␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
256␉␉␉␉␉␉{␊
257␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
258␉␉␉␉␉␉␉return true;␊
259␉␉␉␉␉␉}␊
260␊
261␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
262␉␉␉␉␉␉{␊
263␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
264␉␉␉␉␉␉␉return true;␊
265␉␉␉␉␉␉}␊
266␊
267␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
268␉␉␉␉␉␉{␊
269␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
270␉␉␉␉␉␉␉return true;␊
271␉␉␉␉␉␉}␊
272␊
273␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
274␉␉␉␉␉␉{␊
275␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
276␉␉␉␉␉␉␉return true;␊
277␉␉␉␉␉␉}␊
278␊
279␉␉␉␉␉␉return true;␊
280␊
281␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
282␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
283␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
284␊
285␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
286␉␉␉␉␉␉{␊
287␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
288␉␉␉␉␉␉␉return true;␊
289␉␉␉␉␉␉}␊
290␊
291␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
292␉␉␉␉␉␉{␊
293␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
294␉␉␉␉␉␉␉return true;␊
295␉␉␉␉␉␉}␊
296␊
297␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
298␉␉␉␉␉␉{␊
299␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
300␉␉␉␉␉␉␉return true;␊
301␉␉␉␉␉␉}␊
302␊
303␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
304␉␉␉␉␉␉{␊
305␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
306␉␉␉␉␉␉␉return true;␊
307␉␉␉␉␉␉}␊
308␊
309␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
310␉␉␉␉␉␉{␊
311␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
312␉␉␉␉␉␉␉return true;␊
313␉␉␉␉␉␉}␊
314␊
315␉␉␉␉␉␉return true;␊
316␊
317␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
318␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
319␊
320␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
321␉␉␉␉␉␉{␊
322␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
323␉␉␉␉␉␉␉return true;␊
324␉␉␉␉␉␉}␊
325␊
326␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
327␉␉␉␉␉␉{␊
328␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
329␉␉␉␉␉␉␉return true;␊
330␉␉␉␉␉␉}␊
331␊
332␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
333␉␉␉␉␉␉{␊
334␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
335␉␉␉␉␉␉␉return true;␊
336␉␉␉␉␉␉}␊
337␊
338␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
339␉␉␉␉␉␉{␊
340␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
341␉␉␉␉␉␉␉return true;␊
342␉␉␉␉␉␉}␊
343␊
344␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
345␉␉␉␉␉␉{␊
346␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
347␉␉␉␉␉␉␉return true;␊
348␉␉␉␉␉␉}␊
349␊
350␉␉␉␉␉␉return true;␊
351␊
352␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
353␊
354␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
355␉␉␉␉␉␉{␊
356␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
357␉␉␉␉␉␉␉return true;␊
358␉␉␉␉␉␉}␊
359␊
360␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
361␉␉␉␉␉␉{␊
362␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
363␉␉␉␉␉␉␉return true;␊
364␉␉␉␉␉␉}␊
365␊
366␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
367␉␉␉␉␉␉{␊
368␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
369␉␉␉␉␉␉␉return true;␊
370␉␉␉␉␉␉}␊
371␊
372␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
373␉␉␉␉␉␉{␊
374␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
375␉␉␉␉␉␉␉return true;␊
376␉␉␉␉␉␉}␊
377␊
378␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
379␉␉␉␉␉␉{␊
380␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
381␉␉␉␉␉␉␉return true;␊
382␉␉␉␉␉␉}␊
383␊
384␉␉␉␉␉␉return true;␊
385␊
386␉␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␉␉// 0x3D -␊
387␊
388␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊
389␉␉␉␉␉␉{␊
390␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊
391␉␉␉␉␉␉␉return true;␊
392␉␉␉␉␉␉}␊
393␊
394␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
395␉␉␉␉␉␉{␊
396␉␉␉␉␉␉␉value->word = 0x906;␉␉// 2310 - Apple doesn't use it␊
397␉␉␉␉␉␉␉return true;␊
398␉␉␉␉␉␉}␊
399␊
400␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
401␉␉␉␉␉␉{␊
402␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊
403␉␉␉␉␉␉␉return true;␊
404␉␉␉␉␉␉}␊
405␊
406␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
407␉␉␉␉␉␉{␊
408␉␉␉␉␉␉␉value->word = 0x706;␉␉// 1798␊
409␉␉␉␉␉␉␉return true;␊
410␉␉␉␉␉␉}␊
411␊
412␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
413␉␉␉␉␉␉{␊
414␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊
415␉␉␉␉␉␉␉return true;␊
416␉␉␉␉␉␉}␊
417␊
418//␉␉␉␉␉␉value->word = 0x706;␉␉␉// 1798␊
419␉␉␉␉␉␉return true;␊
420␊
421␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
422␊
423␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
424␉␉␉␉␉␉return true;␊
425␊
426␉␉␉␉␉case CPUID_MODEL_ATOM_3700:␉␉␉// 0x37␊
427␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C␊
428␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F␊
429␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45␊
430␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46␊
431␉␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␉␉␉// 0x47␊
432␉␉␉␉␉case CPUID_MODEL_SKYLAKE:␉␉␉// 0x4E␊
433␉␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX:␉␉␉// 0x55␊
434␉␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␉␉␉// 0x5E␊
435␊
436␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
437␉␉␉␉␉␉{␊
438␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
439␉␉␉␉␉␉␉return true;␊
440␉␉␉␉␉␉}␊
441␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
442␉␉␉␉␉␉{␊
443␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
444␉␉␉␉␉␉␉return true;␊
445␉␉␉␉␉␉}␊
446␊
447␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
448␉␉␉␉␉␉{␊
449␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
450␉␉␉␉␉␉␉return true;␊
451␉␉␉␉␉␉}␊
452␊
453␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
454␉␉␉␉␉␉{␊
455␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
456␉␉␉␉␉␉␉return true;␊
457␉␉␉␉␉␉}␊
458␊
459␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊
460␉␉␉␉␉␉{␊
461␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊
462␉␉␉␉␉␉␉return true;␊
463␉␉␉␉␉␉}␊
464␊
465␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M3))␊
466␉␉␉␉␉␉{␊
467␉␉␉␉␉␉␉value->word = 0xC05;␊
468␉␉␉␉␉␉␉return true;␊
469␉␉␉␉␉␉}␊
470␊
471␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M5))␊
472␉␉␉␉␉␉{␊
473␉␉␉␉␉␉␉value->word = 0xD05;␊
474␉␉␉␉␉␉␉return true;␊
475␉␉␉␉␉␉}␊
476␊
477␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M7))␊
478␉␉␉␉␉␉{␊
479␉␉␉␉␉␉␉value->word = 0xE05;␊
480␉␉␉␉␉␉␉return true;␊
481␉␉␉␉␉␉}␊
482␊
483␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
484␉␉␉␉␉␉{␊
485␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
486␉␉␉␉␉␉␉return true;␊
487␉␉␉␉␉␉}␊
488␊
489␉␉␉␉␉␉return true;␊
490␊
491␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
492␊
493␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
494␉␉␉␉␉␉return true;␊
495␊
496␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
497␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
498␊
499␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
500␉␉␉␉␉␉return true;␊
501␊
502␉␉␉␉␉default:␊
503␊
504␉␉␉␉␉␉return true;␊
505␉␉␉␉␉␉break; // Unsupported CPU type␊
506␉␉␉␉}␊
507␉␉␉␉break;␊
508␊
509␉␉␉default:␊
510␉␉␉␉break;␊
511␉␉}␊
512␉}␊
513/*␊
514␉if (Platform.CPU.Vendor == CPUID_VENDOR_AMD) // AMD␊
515␉{␊
516␉␉value->word = simpleGetSMBOemProcessorType();␊
517␉␉return true;␊
518␉}␊
519*/␊
520␉return false;␊
521}␊
522␊
523bool getSMBMemoryDeviceMemoryType(returnType *value)␊
524{␊
525␉static int idx = -1;␊
526␉int␉map;␊
527␊
528␉idx++;␊
529␉if (idx < MAX_RAM_SLOTS)␊
530␉{␊
531␉␉map = Platform.DMI.DIMM[idx];␊
532␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
533␉␉{␊
534␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
535␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
536␉␉␉return true;␊
537␉␉}␊
538␉}␊
539␊
540␉return false;␊
541//␉value->byte = SMB_MEM_TYPE_DDR2;␊
542//␉return true;␊
543}␊
544␊
545bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
546{␊
547␉value->word = 0xFFFF;␊
548␉return true;␊
549}␊
550␊
551bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
552{␊
553␉static int idx = -1;␊
554␉int␉map;␊
555␊
556␉idx++;␊
557␉if (idx < MAX_RAM_SLOTS)␊
558␉{␊
559␉␉map = Platform.DMI.DIMM[idx];␊
560␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
561␉␉{␊
562␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
563␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
564␉␉␉return true;␊
565␉␉}␊
566␉}␊
567␊
568␉return false;␊
569//␉value->dword = 800;␊
570//␉return true;␊
571}␊
572␊
573bool getSMBMemoryDeviceManufacturer(returnType *value)␊
574{␊
575␉static int idx = -1;␊
576␉int␉map;␊
577␊
578␉idx++;␊
579␉if (idx < MAX_RAM_SLOTS)␊
580␉{␊
581␉␉map = Platform.DMI.DIMM[idx];␊
582␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
583␉␉{␊
584␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
585␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
586␉␉␉return true;␊
587␉␉}␊
588␉}␊
589␊
590␉if (!bootInfo->memDetect)␊
591␉{␊
592␉␉return false;␊
593␉}␊
594␉value->string = NOT_AVAILABLE;␊
595␉return true;␊
596}␊
597␊
598bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
599{␊
600␉static int idx = -1;␊
601␉int␉map;␊
602␊
603␉idx++;␊
604␊
605␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n", idx, MAX_RAM_SLOTS);␊
606␊
607␉if (idx < MAX_RAM_SLOTS)␊
608␉{␊
609␉␉map = Platform.DMI.DIMM[idx];␊
610␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
611␉␉{␊
612␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
613␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
614␉␉␉return true;␊
615␉␉}␊
616␉}␊
617␊
618␉if (!bootInfo->memDetect)␊
619␉{␊
620␉␉return false;␊
621␉}␊
622␉value->string = NOT_AVAILABLE;␊
623␉return true;␊
624}␊
625␊
626bool getSMBMemoryDevicePartNumber(returnType *value)␊
627{␊
628␉static int idx = -1;␊
629␉int␉map;␊
630␊
631␉idx++;␊
632␉if (idx < MAX_RAM_SLOTS)␊
633␉{␊
634␉␉map = Platform.DMI.DIMM[idx];␊
635␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
636␉␉{␊
637␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
638␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
639␉␉␉return true;␊
640␉␉}␊
641␉}␊
642␊
643␉if (!bootInfo->memDetect)␊
644␉{␊
645␉␉return false;␊
646␉}␊
647␉value->string = NOT_AVAILABLE;␊
648␉return true;␊
649}␊
650␊
651// getting smbios addr with fast compare ops, late checksum testing ...␊
652#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
653static const char *const SMTAG = "_SM_";␊
654//static const char *const SM3TAG = "_SM3_"; // smbios3_decode␊
655static const char *const DMITAG = "_DMI_";␊
656␊
657SMBEntryPoint *getAddressOfSmbiosTable(void)␊
658{␊
659␉SMBEntryPoint␉*smbios;␊
660␉/*␊
661␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
662␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
663␉ */␊
664␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
665␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊
666␉{␊
667␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
668␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
669␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
670␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
671␉␉{␊
672␉␉␉return smbios;␊
673␉ }␊
674␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
675␉}␊
676␉printf("ERROR: Unable to find SMBIOS!\n");␊
677␉pause();␊
678␉return NULL;␊
679}␊
680

Archive Download this file

Revision: 2849