1 | /*␊ |
2 | * spd.c - serial presence detect memory information␊ |
3 | *␊ |
4 | * Originally restored from pcefi10.5 by netkas␊ |
5 | * Dynamic mem detection original impl. by Rekursor␊ |
6 | * System profiler fix and other fixes by Mozodojo.␊ |
7 | */␊ |
8 | ␊ |
9 | #include "libsaio.h"␊ |
10 | #include "pci.h"␊ |
11 | #include "platform.h"␊ |
12 | #include "spd.h"␊ |
13 | #include "cpu.h"␊ |
14 | #include "saio_internal.h"␊ |
15 | #include "bootstruct.h"␊ |
16 | #include "memvendors.h"␊ |
17 | ␊ |
18 | #ifndef DEBUG_SPD␊ |
19 | ␉#define DEBUG_SPD 0␊ |
20 | #endif␊ |
21 | ␊ |
22 | #if DEBUG_SPD␊ |
23 | ␉#define DBG(x...)␉printf(x)␊ |
24 | #else␊ |
25 | ␉#define DBG(x...)␉msglog(x)␊ |
26 | #endif␊ |
27 | ␊ |
28 | static const char *spd_memory_types[] =␊ |
29 | {␊ |
30 | ␉"RAM",␉␉␉␉/* 00h Undefined */␊ |
31 | ␉"STD FPM DRAM",␉␉␉/* 01h FPM */␊ |
32 | ␉"EDO",␉␉␉␉/* 02h EDO */␊ |
33 | ␉"PIPE NIBBLE",␉␉␉/* 03h PIPELINE NIBBLE */␊ |
34 | ␉"SDRAM",␉␉␉/* 04h SDRAM */␊ |
35 | ␉"ROM",␉␉␉␉/* 05h MULTIPLEXED ROM */␊ |
36 | ␉"DDR SGRAM",␉␉␉/* 06h SGRAM DDR */␊ |
37 | ␉"DDR SDRAM",␉␉␉/* 07h SDRAM DDR */␊ |
38 | ␉"DDR2 SDRAM",␉␉␉/* 08h SDRAM DDR 2 */␊ |
39 | ␉"DDR2 SDRAM FB-DIMM",␉␉/* 09h Undefined */␊ |
40 | ␉"DDR2 SDRAM FB-DIMM Probe",␉/* 0Ah Undefined */␊ |
41 | ␉"DDR3 SDRAM",␉␉␉/* 0Bh SDRAM DDR 3 */␊ |
42 | ␉"DDR4 SDRAM"␉␉␉/* 0Ch SDRAM DDR 4 */␊ |
43 | };␊ |
44 | ␊ |
45 | #define UNKNOWN_MEM_TYPE 2␊ |
46 | static uint8_t spd_mem_to_smbios[] =␊ |
47 | {␊ |
48 | ␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊ |
49 | ␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊ |
50 | ␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊ |
51 | ␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊ |
52 | ␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊ |
53 | ␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊ |
54 | ␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊ |
55 | ␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊ |
56 | ␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊ |
57 | ␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊ |
58 | ␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊ |
59 | ␉SMB_MEM_TYPE_DDR3,␉␉/* 0Bh SDRAM DDR 3 */␊ |
60 | ␉SMB_MEM_TYPE_DDR4␉␉/* 0Ch SDRAM DDR 4 */␊ |
61 | };␊ |
62 | #define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊ |
63 | ␊ |
64 | #define rdtsc(low,high) \␊ |
65 | __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊ |
66 | ␊ |
67 | // Intel SMB reg offsets␊ |
68 | #define SMBHSTSTS 0␊ |
69 | #define SMBHSTCNT 2␊ |
70 | #define SMBHSTCMD 3␊ |
71 | #define SMBHSTADD 4␊ |
72 | #define SMBHSTDAT 5␊ |
73 | #define SMBHSTDAT1 6␊ |
74 | #define SBMBLKDAT 7␊ |
75 | ␊ |
76 | int spd_indexes[] = {␊ |
77 | ␉SPD_MEMORY_TYPE,␊ |
78 | ␉SPD_DDR3_MEMORY_BANK,␊ |
79 | ␉SPD_DDR3_MEMORY_CODE,␊ |
80 | ␉SPD_NUM_ROWS,␊ |
81 | ␉SPD_NUM_COLUMNS,␊ |
82 | ␉SPD_NUM_DIMM_BANKS,␊ |
83 | ␉SPD_NUM_BANKS_PER_SDRAM,␊ |
84 | ␉4,7,8,9,12,64, /* TODO: give names to these values */␊ |
85 | ␉95,96,97,98, 122,123,124,125 /* UIS */␊ |
86 | };␊ |
87 | #define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊ |
88 | ␊ |
89 | /** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊ |
90 | ␊ |
91 | static unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊ |
92 | {␊ |
93 | ␉int l1, h1, l2, h2;␊ |
94 | ␉unsigned long long t;␊ |
95 | ␊ |
96 | ␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊ |
97 | ␉outb(base + SMBHSTDAT, 0xff);␊ |
98 | ␊ |
99 | ␉rdtsc(l1, h1);␊ |
100 | ␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊ |
101 | ␉{␊ |
102 | ␉␉rdtsc(l2, h2);␊ |
103 | ␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊ |
104 | ␉␉if (t > 5)␊ |
105 | ␉␉{␊ |
106 | ␉␉␉return 0xFF;␉// break␊ |
107 | ␉␉}␊ |
108 | ␉}␊ |
109 | ␊ |
110 | ␉outb(base + SMBHSTCMD, cmd);␊ |
111 | ␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊ |
112 | ␉outb(base + SMBHSTCNT, 0x48 );␊ |
113 | ␊ |
114 | ␉rdtsc(l1, h1);␊ |
115 | ␊ |
116 | ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait till command finished␊ |
117 | ␉{␊ |
118 | ␉␉rdtsc(l2, h2);␊ |
119 | ␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊ |
120 | ␉␉if (t > 5)␊ |
121 | ␉␉{␊ |
122 | ␉␉␉break;␉// break after 5ms␊ |
123 | ␉␉}␊ |
124 | ␉}␊ |
125 | ␉return inb(base + SMBHSTDAT);␊ |
126 | }␊ |
127 | ␊ |
128 | /* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊ |
129 | #define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊ |
130 | ␊ |
131 | /** Read from spd *used* values only*/␊ |
132 | static void init_spd(char *spd, uint32_t base, int slot)␊ |
133 | {␊ |
134 | ␉int i;␊ |
135 | ␉for (i = 0; i < SPD_INDEXES_SIZE; i++)␊ |
136 | ␉{␊ |
137 | ␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊ |
138 | ␉}␊ |
139 | }␊ |
140 | ␊ |
141 | // Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,␊ |
142 | // have different formats, always return a valid ptr.␊ |
143 | static const char *getVendorName(RamSlotInfo_t *slot, uint32_t base, int slot_num)␊ |
144 | {␊ |
145 | ␉uint8_t bank = 0;␊ |
146 | ␉uint8_t code = 0;␊ |
147 | ␉int i = 0;␊ |
148 | ␉uint8_t *spd = (uint8_t *) slot->spd;␊ |
149 | ␊ |
150 | ␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊ |
151 | ␉{␊ |
152 | ␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊ |
153 | ␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊ |
154 | ␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊ |
155 | ␉␉{␊ |
156 | ␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊ |
157 | ␉␉␉{␊ |
158 | ␉␉␉␉return vendorMap[i].name;␊ |
159 | ␉␉␉}␊ |
160 | ␉␉}␊ |
161 | ␉}␊ |
162 | ␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊ |
163 | ␉{␊ |
164 | ␉␉if(spd[64]==0x7f)␊ |
165 | ␉␉{␊ |
166 | ␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊ |
167 | ␉␉␉{␊ |
168 | ␉␉␉␉bank++;␊ |
169 | ␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊ |
170 | ␉␉␉}␊ |
171 | ␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊ |
172 | ␉␉␉code = spd[i];␊ |
173 | ␉␉}␊ |
174 | ␉␉else␊ |
175 | ␉␉{␊ |
176 | ␉␉␉code = spd[64];␊ |
177 | ␉␉␉bank = 0;␊ |
178 | ␉␉}␊ |
179 | ␊ |
180 | ␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊ |
181 | ␉␉{␊ |
182 | ␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊ |
183 | ␉␉␉{␊ |
184 | ␉␉␉␉return vendorMap[i].name;␊ |
185 | ␉␉␉}␊ |
186 | ␉␉}␊ |
187 | ␉}␊ |
188 | ␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊ |
189 | ␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊ |
190 | ␉␉return "Unifosa";␊ |
191 | ␉}␊ |
192 | ␉return "NoName";␊ |
193 | }␊ |
194 | ␊ |
195 | /* Get Default Memory Module Speed (no overclocking handled) */␊ |
196 | static int getDDRspeedMhz(const char * spd)␊ |
197 | {␊ |
198 | ␊ |
199 | ␉if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))␊ |
200 | ␉{␊ |
201 | ␉␉switch(spd[9])␊ |
202 | ␉␉{␊ |
203 | ␉␉␉case 0x50:␊ |
204 | ␉␉␉␉return 400;␊ |
205 | ␉␉␉case 0x3d:␊ |
206 | ␉␉␉␉return 533;␊ |
207 | ␉␉␉case 0x30:␊ |
208 | ␉␉␉␉return 667;␊ |
209 | ␉␉␉case 0x25:␊ |
210 | ␉␉␉default:␊ |
211 | ␉␉␉␉return 800;␊ |
212 | ␉␉␉case 0x1E:␊ |
213 | ␉␉␉␉return 1066;␊ |
214 | ␉␉}␊ |
215 | ␉}␊ |
216 | ␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊ |
217 | ␉{␊ |
218 | ␉␉switch(spd[12])␊ |
219 | ␉␉{␊ |
220 | ␉␉␉case 0x0f:␊ |
221 | ␉␉␉␉return 1066;␊ |
222 | ␉␉␉case 0x0c:␊ |
223 | ␉␉␉␉return 1333;␊ |
224 | ␉␉␉case 0x0a:␊ |
225 | ␉␉␉␉return 1600;␊ |
226 | ␉␉␉case 0x14:␊ |
227 | ␉␉␉default:␊ |
228 | ␉␉␉␉return 800;␊ |
229 | ␉␉}␊ |
230 | ␉}␊ |
231 | ␉return 800; // default freq for unknown types␊ |
232 | }␊ |
233 | ␊ |
234 | #define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊ |
235 | #define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊ |
236 | ␊ |
237 | /* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊ |
238 | static const char *getDDRSerial(const char *spd)␊ |
239 | {␊ |
240 | ␉static char asciiSerial[17];␊ |
241 | ␊ |
242 | ␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊ |
243 | ␉{␊ |
244 | ␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊ |
245 | ␉}␊ |
246 | ␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊ |
247 | ␉{␊ |
248 | ␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊ |
249 | ␉}␊ |
250 | ␉else␊ |
251 | ␉{␊ |
252 | ␉␉strcpy(asciiSerial, "0000000000000000");␊ |
253 | ␉}␊ |
254 | ␊ |
255 | ␉return strdup(asciiSerial);␊ |
256 | }␊ |
257 | ␊ |
258 | /* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊ |
259 | static const char *getDDRPartNum(char *spd, uint32_t base, int slot)␊ |
260 | {␊ |
261 | ␉int i, start = 0, index = 0;␊ |
262 | ␉char c;␊ |
263 | ␉static char asciiPartNo[32];␊ |
264 | ␊ |
265 | ␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊ |
266 | ␉{␊ |
267 | ␉␉start = 128;␊ |
268 | ␉}␊ |
269 | ␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR)␊ |
270 | ␉{␊ |
271 | ␉␉start = 73;␊ |
272 | ␉}␊ |
273 | ␉␊ |
274 | ␉// Check that the spd part name is zero terminated and that it is ascii:␊ |
275 | ␉bzero(asciiPartNo, sizeof(asciiPartNo));␊ |
276 | ␉for (i = start; i < start + sizeof(asciiPartNo); i++)␊ |
277 | ␉{␊ |
278 | ␉␉READ_SPD(spd, base, slot, (uint8_t)i); // only read once the corresponding model part (ddr3 or ddr2)␊ |
279 | ␉␉c = spd[i];␊ |
280 | ␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊ |
281 | ␉␉{␊ |
282 | ␉␉␉// It seems that System Profiler likes only letters and digits...␊ |
283 | ␉␉␉asciiPartNo[index++] = c;␊ |
284 | ␉␉}␊ |
285 | ␉␉else if (!isascii(c))␊ |
286 | ␉␉{␊ |
287 | ␉␉␉break;␊ |
288 | ␉␉}␊ |
289 | ␉}␊ |
290 | ␊ |
291 | ␉return strdup(asciiPartNo);␊ |
292 | }␊ |
293 | ␊ |
294 | int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊ |
295 | ␊ |
296 | /* Read from smbus the SPD content and interpret it for detecting memory attributes */␊ |
297 | static void read_smb_intel(pci_dt_t *smbus_dev)␊ |
298 | {␊ |
299 | ␉int␉␉i, speed;␊ |
300 | ␉uint8_t␉␉spd_size, spd_type;␊ |
301 | ␉uint32_t␉base, mmio, hostc;␊ |
302 | ␉uint16_t␉cmd;␊ |
303 | //␉bool␉␉dump = false;␊ |
304 | ␉RamSlotInfo_t␉*slot;␊ |
305 | ␊ |
306 | ␉cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊ |
307 | ␊ |
308 | ␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊ |
309 | ␊ |
310 | ␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊ |
311 | ␊ |
312 | ␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊ |
313 | ␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊ |
314 | ␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊ |
315 | ␊ |
316 | ␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",␊ |
317 | ␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊ |
318 | ␊ |
319 | ␉//Azi: no use for this!␊ |
320 | ␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊ |
321 | ␉// needed at least for laptops␊ |
322 | ␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊ |
323 | ␊ |
324 | ␉char spdbuf[MAX_SPD_SIZE];␊ |
325 | ␉// Search MAX_RAM_SLOTS slots␊ |
326 | ␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊ |
327 | ␉{␊ |
328 | ␉␉slot = &Platform.RAM.DIMM[i];␊ |
329 | ␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊ |
330 | ␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊ |
331 | ␉␉// Check spd is present␊ |
332 | ␉␉if (spd_size && (spd_size != 0xff))␊ |
333 | ␉␉{␊ |
334 | ␉␉␉slot->spd = spdbuf;␊ |
335 | ␉␉␉slot->InUse = true;␊ |
336 | ␊ |
337 | ␉␉␉bzero(slot->spd, spd_size);␊ |
338 | ␊ |
339 | ␉␉␉// Copy spd data into buffer␊ |
340 | ␊ |
341 | ␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊ |
342 | ␉␉␉init_spd(slot->spd, base, i);␊ |
343 | ␊ |
344 | ␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊ |
345 | ␉␉␉{␊ |
346 | ␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊ |
347 | ␊ |
348 | ␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊ |
349 | ␉␉␉␉␉+ (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊ |
350 | ␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊ |
351 | ␉␉␉␉␉slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊ |
352 | ␉␉␉␉break;␊ |
353 | ␊ |
354 | ␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊ |
355 | ␊ |
356 | ␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊ |
357 | ␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊ |
358 | ␉␉␉␉break;␊ |
359 | ␊ |
360 | ␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊ |
361 | ␊ |
362 | ␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊ |
363 | ␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊ |
364 | ␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊ |
365 | ␊ |
366 | ␉␉␉␉break;␊ |
367 | ␊ |
368 | ␉␉␉␉default:␊ |
369 | ␉␉␉␉␉slot->ModuleSize = 0;␊ |
370 | ␉␉␉␉break;␊ |
371 | ␊ |
372 | ␉␉␉}␊ |
373 | ␊ |
374 | ␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊ |
375 | ␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊ |
376 | ␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE)␊ |
377 | ␉␉␉{␊ |
378 | ␉␉␉␉continue;␊ |
379 | ␉␉␉}␊ |
380 | ␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊ |
381 | ␉␉␉slot->Vendor = getVendorName(slot, base, i);␊ |
382 | ␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊ |
383 | ␊ |
384 | ␉␉␉// determine spd speed␊ |
385 | ␉␉␉speed = (uint16_t)getDDRspeedMhz(slot->spd);␊ |
386 | ␉␉␉if (slot->Frequency < speed)␊ |
387 | ␉␉␉{␊ |
388 | ␉␉␉␉slot->Frequency = speed;␊ |
389 | ␉␉␉}␊ |
390 | ␊ |
391 | ␉␉␉// pci memory controller if available, is more reliable␊ |
392 | ␉␉␉if (Platform.RAM.Frequency > 0)␊ |
393 | ␉␉␉{␊ |
394 | ␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊ |
395 | ␉␉␉␉// now round off special cases␊ |
396 | ␉␉␉␉uint32_t fmod100 = freq %100;␊ |
397 | ␉␉␉␉switch(fmod100)␊ |
398 | ␉␉␉␉{␊ |
399 | ␉␉␉␉␉case 1:␉freq--;␉break;␊ |
400 | ␉␉␉␉␉case 32:␉freq++;␉break;␊ |
401 | ␉␉␉␉␉case 65:␉freq++; break;␊ |
402 | ␉␉␉␉␉case 98:␉freq+=2;break;␊ |
403 | ␉␉␉␉␉case 99:␉freq++; break;␊ |
404 | ␉␉␉␉}␊ |
405 | ␉␉␉␉slot->Frequency = freq;␊ |
406 | ␉␉␉␉DBG("RAM speed %dMHz \n", freq);␊ |
407 | ␉␉␉}␊ |
408 | ␊ |
409 | ␉␉␉verbose("\tSlot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n\t\tPartNo=%s SerialNo=%s\n",␊ |
410 | ␉␉␉␉i,␊ |
411 | ␉␉␉␉(int)slot->Type,␊ |
412 | ␉␉␉␉slot->ModuleSize, ␊ |
413 | ␉␉␉␉spd_memory_types[spd_type],␊ |
414 | ␉␉␉␉slot->Frequency,␊ |
415 | ␉␉␉␉slot->Vendor,␊ |
416 | ␉␉␉␉slot->PartNo,␊ |
417 | ␉␉␉␉slot->SerialNo);␊ |
418 | ␉␉␉slot->InUse = true;␊ |
419 | ␉␉}␊ |
420 | ␊ |
421 | ␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊ |
422 | ␉␉Platform.DMI.DIMM[i]= ␊ |
423 | ␉(uint32_t)((i > 0 && Platform.RAM.DIMM[1].InUse == false && fullBanks && Platform.DMI.CntMemorySlots == 2) ? mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊ |
424 | ␊ |
425 | ␉␉slot->spd = NULL;␊ |
426 | ␊ |
427 | ␉} // for␊ |
428 | }␊ |
429 | ␊ |
430 | static struct smbus_controllers_t smbus_controllers[] = {␊ |
431 | ␊ |
432 | ␉// Intel␊ |
433 | ␉{0x8086, 0x1C22, "P67",␉␉␉read_smb_intel },␊ |
434 | ␉{0x8086, 0x1D22, "X79",␉␉␉read_smb_intel },␊ |
435 | ␉{0x8086, 0x1D70, "X79",␉␉␉read_smb_intel },␊ |
436 | ␉{0x8086, 0x1D71, "X79",␉␉␉read_smb_intel },␊ |
437 | ␉{0x8086, 0x1D72, "C608",␉␉read_smb_intel },␊ |
438 | ␉{0x8086, 0x1E22, "Z77",␉␉␉read_smb_intel },␊ |
439 | ␉{0x8086, 0x2330, "DH89xxCC",␉␉read_smb_intel },␊ |
440 | ␉{0x8086, 0x2413, "82801AA",␉␉read_smb_intel },␊ |
441 | ␉{0x8086, 0x2423, "BAM",␉␉␉read_smb_intel },␊ |
442 | ␉{0x8086, 0x2443, "BAM",␉␉␉read_smb_intel },␊ |
443 | ␉{0x8086, 0x2483, "CAM",␉␉␉read_smb_intel },␊ |
444 | ␉{0x8086, 0x24C3, "ICH4",␉␉read_smb_intel },␊ |
445 | ␉{0x8086, 0x24D3, "ICH5",␉␉read_smb_intel },␊ |
446 | ␉{0x8086, 0x25A4, "6300ESB",␉␉read_smb_intel },␊ |
447 | ␉{0x8086, 0x266A, "ICH6",␉␉read_smb_intel },␊ |
448 | ␉{0x8086, 0x269B, "ESB",␉␉␉read_smb_intel },␊ |
449 | ␉{0x8086, 0x27DA, "ICH7",␉␉read_smb_intel },␊ |
450 | ␉{0x8086, 0x283E, "ICH8",␉␉read_smb_intel },␊ |
451 | ␉{0x8086, 0x2930, "ICH9",␉␉read_smb_intel },␊ |
452 | ␉{0x8086, 0x3A30, "ICH10",␉␉read_smb_intel },␊ |
453 | ␉{0x8086, 0x3A60, "ICH10",␉␉read_smb_intel },␊ |
454 | ␉{0x8086, 0x3B30, "P55",␉␉␉read_smb_intel },␊ |
455 | ␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel },␊ |
456 | ␉{0x8086, 0x8119, "US15W",␉␉read_smb_intel },␊ |
457 | ␉{0x8086, 0x8C22, "HSW",␉␉␉read_smb_intel },␊ |
458 | ␉{0x8086, 0x8CA2, "Z97/H97",␉␉read_smb_intel },␊ |
459 | ␉{0x8086, 0x8D22, "X99",␉␉␉read_smb_intel },␊ |
460 | ␉{0x8086, 0x9C22, "HSW-ULT",␉␉read_smb_intel }␊ |
461 | ␊ |
462 | ␉// AMD␊ |
463 | //␉{0x1002, 0x4385, "AMD SB600/700",␉... },␊ |
464 | //␉{0x1022, 0x780B, "AMD SB800/900",␉... }␊ |
465 | ␊ |
466 | };␊ |
467 | ␊ |
468 | // initial call : pci_dt = root_pci_dev;␊ |
469 | // find_and_read_smbus_controller(root_pci_dev);␊ |
470 | bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊ |
471 | {␊ |
472 | ␉pci_dt_t␉*current = pci_dt;␊ |
473 | ␉int i;␊ |
474 | ␊ |
475 | ␉while (current)␊ |
476 | ␉{␊ |
477 | #if 0␊ |
478 | ␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊ |
479 | ␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊ |
480 | ␉␉current->class_id, current->vendor_id, current->device_id, ␊ |
481 | ␉␉get_pci_dev_path(current));␊ |
482 | #endif␊ |
483 | ␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊ |
484 | ␉␉{␊ |
485 | ␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊ |
486 | ␉␉␉{␊ |
487 | ␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊ |
488 | ␉␉␉␉return true;␊ |
489 | ␉␉␉}␊ |
490 | ␉␉}␊ |
491 | ␉␉find_and_read_smbus_controller(current->children);␊ |
492 | ␉␉current = current->next;␊ |
493 | ␉}␊ |
494 | ␉return false; // not found␊ |
495 | }␊ |
496 | ␊ |
497 | void scan_spd(PlatformInfo_t *p)␊ |
498 | {␊ |
499 | ␉find_and_read_smbus_controller(root_pci_dev);␊ |
500 | }␊ |
501 | ␊ |
502 | |