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Root/trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "config.h"␊
10#include "libsaio.h"␊
11#include "pci.h"␊
12#include "platform.h"␊
13#include "spd.h"␊
14#include "cpu.h"␊
15#include "saio_internal.h"␊
16#include "bootstruct.h"␊
17#include "memvendors.h"␊
18␊
19#if DEBUG_SPD␊
20␉#define DBG(x...)␉printf(x)␊
21#else␊
22␉#define DBG(x...)␉msglog(x)␊
23#endif␊
24␊
25static const char *spd_memory_types[] =␊
26{␊
27␉"RAM",␉␉␉␉/* 00h Undefined */␊
28␉"STD FPM DRAM",␉␉␉/* 01h FPM */␊
29␉"EDO",␉␉␉␉/* 02h EDO */␊
30␉"PIPE NIBBLE",␉␉␉/* 03h PIPELINE NIBBLE */␊
31␉"SDRAM",␉␉␉/* 04h SDRAM */␊
32␉"ROM",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
33␉"DDR SGRAM",␉␉␉/* 06h SGRAM DDR */␊
34␉"DDR SDRAM",␉␉␉/* 07h SDRAM DDR */␊
35␉"DDR2 SDRAM",␉␉␉/* 08h SDRAM DDR 2 */␊
36␉"DDR2 SDRAM FB-DIMM",␉␉/* 09h Undefined */␊
37␉"DDR2 SDRAM FB-DIMM Probe",␉/* 0Ah Undefined */␊
38␉"DDR3 SDRAM",␉␉␉/* 0Bh SDRAM DDR 3 */␊
39␉"DDR4 SDRAM"␉␉␉/* 0Ch SDRAM DDR 4 */␊
40};␊
41␊
42#define UNKNOWN_MEM_TYPE 2␊
43static uint8_t spd_mem_to_smbios[] =␊
44{␊
45␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
46␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
49␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
50␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
51␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
52␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
53␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
54␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
55␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
56␉SMB_MEM_TYPE_DDR3,␉␉/* 0Bh SDRAM DDR 3 */␊
57␉SMB_MEM_TYPE_DDR4␉␉/* 0Ch SDRAM DDR 4 */␊
58};␊
59#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
60␊
61#define rdtsc(low,high) \␊
62__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
63␊
64#define SMBHSTSTS 0␊
65#define SMBHSTCNT 2␊
66#define SMBHSTCMD 3␊
67#define SMBHSTADD 4␊
68#define SMBHSTDAT 5␊
69#define SBMBLKDAT 7␊
70␊
71int spd_indexes[] = {␊
72␉SPD_MEMORY_TYPE,␊
73␉SPD_DDR3_MEMORY_BANK,␊
74␉SPD_DDR3_MEMORY_CODE,␊
75␉SPD_NUM_ROWS,␊
76␉SPD_NUM_COLUMNS,␊
77␉SPD_NUM_DIMM_BANKS,␊
78␉SPD_NUM_BANKS_PER_SDRAM,␊
79␉4,7,8,9,12,64, /* TODO: give names to these values */␊
80␉95,96,97,98, 122,123,124,125 /* UIS */␊
81};␊
82#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
83␊
84/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
85␊
86unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
87{␊
88␉int l1, h1, l2, h2;␊
89␉unsigned long long t;␊
90␊
91␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
92␉outb(base + SMBHSTDAT, 0xff);␊
93␊
94␉rdtsc(l1, h1);␊
95␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
96␉{␊
97␉␉rdtsc(l2, h2);␊
98␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
99␉␉if (t > 5)␊
100␉␉{␊
101␉␉␉return 0xFF;␉// break␊
102␉␉}␊
103␉}␊
104␊
105␉outb(base + SMBHSTCMD, cmd);␊
106␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
107␉outb(base + SMBHSTCNT, 0x48 );␊
108␊
109␉rdtsc(l1, h1);␊
110␊
111␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait till command finished␊
112␉{␊
113␉␉rdtsc(l2, h2);␊
114␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
115␉␉if (t > 5)␊
116␉␉{␊
117␉␉␉break;␉// break after 5ms␊
118␉␉}␊
119␉}␊
120␉return inb(base + SMBHSTDAT);␊
121}␊
122␊
123/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
124#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
125␊
126/** Read from spd *used* values only*/␊
127static void init_spd(char *spd, uint32_t base, int slot)␊
128{␊
129␉int i;␊
130␉for (i = 0; i < SPD_INDEXES_SIZE; i++)␊
131␉{␊
132␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
133␉}␊
134}␊
135␊
136// Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,␊
137// have different formats, always return a valid ptr.␊
138const char *getVendorName(RamSlotInfo_t *slot, uint32_t base, int slot_num)␊
139{␊
140␉uint8_t bank = 0;␊
141␉uint8_t code = 0;␊
142␉int i = 0;␊
143␉uint8_t *spd = (uint8_t *) slot->spd;␊
144␊
145␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
146␉{␊
147␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
148␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
149␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
150␉␉{␊
151␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
152␉␉␉{␊
153␉␉␉␉return vendorMap[i].name;␊
154␉␉␉}␊
155␉␉}␊
156␉}␊
157␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
158␉{␊
159␉␉if(spd[64]==0x7f)␊
160␉␉{␊
161␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
162␉␉␉{␊
163␉␉␉␉bank++;␊
164␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
165␉␉␉}␊
166␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
167␉␉␉code = spd[i];␊
168␉␉}␊
169␉␉else␊
170␉␉{␊
171␉␉␉code = spd[64];␊
172␉␉␉bank = 0;␊
173␉␉}␊
174␊
175␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
176␉␉{␊
177␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
178␉␉␉{␊
179␉␉␉␉return vendorMap[i].name;␊
180␉␉␉}␊
181␉␉}␊
182␉}␊
183␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
184␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊
185␉␉return "Unifosa";␊
186␉}␊
187␉return "NoName";␊
188}␊
189␊
190/* Get Default Memory Module Speed (no overclocking handled) */␊
191int getDDRspeedMhz(const char * spd)␊
192{␊
193␊
194␉if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))␊
195␉{␊
196␉␉switch(spd[9])␊
197␉␉{␊
198␉␉␉case 0x50:␊
199␉␉␉␉return 400;␊
200␉␉␉case 0x3d:␊
201␉␉␉␉return 533;␊
202␉␉␉case 0x30:␊
203␉␉␉␉return 667;␊
204␉␉␉case 0x25:␊
205␉␉␉default:␊
206␉␉␉␉return 800;␊
207␉␉␉case 0x1E:␊
208␉␉␉␉return 1066;␊
209␉␉}␊
210␉}␊
211␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
212␉{␊
213␉␉switch(spd[12])␊
214␉␉{␊
215␉␉␉case 0x0f:␊
216␉␉␉␉return 1066;␊
217␉␉␉case 0x0c:␊
218␉␉␉␉return 1333;␊
219␉␉␉case 0x0a:␊
220␉␉␉␉return 1600;␊
221␉␉␉case 0x14:␊
222␉␉␉default:␊
223␉␉␉␉return 800;␊
224␉␉}␊
225␉}␊
226␉return 800; // default freq for unknown types␊
227}␊
228␊
229#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
230#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
231␊
232/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
233const char *getDDRSerial(const char *spd)␊
234{␊
235␉static char asciiSerial[17];␊
236␊
237␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
238␉{␊
239␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
240␉}␊
241␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
242␉{␊
243␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%2X%2X%2X%2X%2X%2X%2X%2X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
244␉}␊
245␉else␊
246␉{␊
247␉␉strcpy(asciiSerial, "0000000000000000");␊
248␉}␊
249␊
250␉return strdup(asciiSerial);␊
251}␊
252␊
253/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
254const char *getDDRPartNum(char *spd, uint32_t base, int slot)␊
255{␊
256␉int i, start = 0, index = 0;␊
257␉char c;␊
258␉static char asciiPartNo[32];␊
259␊
260␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
261␉{␊
262␉␉start = 128;␊
263␉}␊
264␉else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR)␊
265␉{␊
266␉␉start = 73;␊
267␉}␊
268␉␊
269␉// Check that the spd part name is zero terminated and that it is ascii:␊
270␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
271␉for (i = start; i < start + sizeof(asciiPartNo); i++)␊
272␉{␊
273␉␉READ_SPD(spd, base, slot, (uint8_t)i); // only read once the corresponding model part (ddr3 or ddr2)␊
274␉␉c = spd[i];␊
275␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
276␉␉{␊
277␉␉␉// It seems that System Profiler likes only letters and digits...␊
278␉␉␉asciiPartNo[index++] = c;␊
279␉␉}␊
280␉␉else if (!isascii(c))␊
281␉␉{␊
282␉␉␉break;␊
283␉␉}␊
284␉}␊
285␊
286␉return strdup(asciiPartNo);␊
287}␊
288␊
289int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
290␊
291/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
292static void read_smb_intel(pci_dt_t *smbus_dev)␊
293{␊
294␉int␉␉i, speed;␊
295␉uint8_t␉␉spd_size, spd_type;␊
296␉uint32_t␉base, mmio, hostc;␊
297␉uint16_t␉cmd;␊
298//␉bool␉␉dump = false;␊
299␉RamSlotInfo_t␉*slot;␊
300␊
301␉cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
302␊
303␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
304␊
305␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
306␊
307␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
308␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
309␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
310␊
311␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",␊
312␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
313␊
314␉//Azi: no use for this!␊
315␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
316␉// needed at least for laptops␊
317␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
318␊
319␉char spdbuf[MAX_SPD_SIZE];␊
320␉// Search MAX_RAM_SLOTS slots␊
321␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊
322␉{␊
323␉␉slot = &Platform.RAM.DIMM[i];␊
324␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
325␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
326␉␉// Check spd is present␊
327␉␉if (spd_size && (spd_size != 0xff))␊
328␉␉{␊
329␉␉␉slot->spd = spdbuf;␊
330␉␉␉slot->InUse = true;␊
331␊
332␉␉␉bzero(slot->spd, spd_size);␊
333␊
334␉␉␉// Copy spd data into buffer␊
335␊
336␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
337␉␉␉init_spd(slot->spd, base, i);␊
338␊
339␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
340␉␉␉{␊
341␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
342␊
343␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
344␉␉␉␉␉+ (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
345␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
346␉␉␉␉␉slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
347␉␉␉␉break;␊
348␊
349␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
350␊
351␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
352␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
353␉␉␉␉break;␊
354␊
355␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
356␊
357␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
358␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
359␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
360␊
361␉␉␉␉break;␊
362␊
363␉␉␉␉default:␊
364␉␉␉␉␉slot->ModuleSize = 0;␊
365␉␉␉␉break;␊
366␊
367␉␉␉}␊
368␊
369␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
370␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
371␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE)␊
372␉␉␉{␊
373␉␉␉␉continue;␊
374␉␉␉}␊
375␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
376␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
377␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
378␊
379␉␉␉// determine spd speed␊
380␉␉␉speed = (uint16_t)getDDRspeedMhz(slot->spd);␊
381␉␉␉if (slot->Frequency < speed)␊
382␉␉␉{␊
383␉␉␉␉slot->Frequency = speed;␊
384␉␉␉}␊
385␊
386␉␉␉// pci memory controller if available, is more reliable␊
387␉␉␉if (Platform.RAM.Frequency > 0)␊
388␉␉␉{␊
389␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
390␉␉␉␉// now round off special cases␊
391␉␉␉␉uint32_t fmod100 = freq %100;␊
392␉␉␉␉switch(fmod100)␊
393␉␉␉␉{␊
394␉␉␉␉␉case 1:␉freq--;␉break;␊
395␉␉␉␉␉case 32:␉freq++;␉break;␊
396␉␉␉␉␉case 65:␉freq++; break;␊
397␉␉␉␉␉case 98:␉freq+=2;break;␊
398␉␉␉␉␉case 99:␉freq++; break;␊
399␉␉␉␉}␊
400␉␉␉␉slot->Frequency = freq;␊
401␉␉␉␉DBG("RAM speed %dMHz \n", freq);␊
402␉␉␉}␊
403␊
404␉␉␉verbose("\tSlot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n\t\tPartNo=%s SerialNo=%s\n",␊
405␉␉␉␉i,␊
406␉␉␉␉(int)slot->Type,␊
407␉␉␉␉slot->ModuleSize, ␊
408␉␉␉␉spd_memory_types[spd_type],␊
409␉␉␉␉slot->Frequency,␊
410␉␉␉␉slot->Vendor,␊
411␉␉␉␉slot->PartNo,␊
412␉␉␉␉slot->SerialNo);␊
413␉␉␉slot->InUse = true;␊
414␉␉}␊
415␊
416␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
417␉␉Platform.DMI.DIMM[i]= ␊
418 ␉(uint32_t)((i > 0 && Platform.RAM.DIMM[1].InUse == false && fullBanks && Platform.DMI.CntMemorySlots == 2) ? mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
419␊
420␉␉slot->spd = NULL;␊
421␊
422␉} // for␊
423}␊
424␊
425static struct smbus_controllers_t smbus_controllers[] = {␊
426␊
427␉// Intel␊
428␉{0x8086, 0x1C22, "P67",␉␉␉read_smb_intel },␊
429␉{0x8086, 0x1D22, "X79",␉␉␉read_smb_intel },␊
430␉{0x8086, 0x1D70, "X79",␉␉␉read_smb_intel },␊
431␉{0x8086, 0x1D71, "X79",␉␉␉read_smb_intel },␊
432␉{0x8086, 0x1D72, "C608",␉␉read_smb_intel },␊
433␉{0x8086, 0x1E22, "Z77",␉␉␉read_smb_intel },␊
434␉{0x8086, 0x2330, "DH89xxCC",␉␉read_smb_intel },␊
435␉{0x8086, 0x2413, "82801AA",␉␉read_smb_intel },␊
436␉{0x8086, 0x2423, "BAM",␉␉␉read_smb_intel },␊
437␉{0x8086, 0x2443, "BAM",␉␉␉read_smb_intel },␊
438␉{0x8086, 0x2483, "CAM",␉␉␉read_smb_intel },␊
439␉{0x8086, 0x24C3, "ICH4",␉␉read_smb_intel },␊
440␉{0x8086, 0x24D3, "ICH5",␉␉read_smb_intel },␊
441␉{0x8086, 0x25A4, "6300ESB",␉␉read_smb_intel },␊
442␉{0x8086, 0x266A, "ICH6",␉␉read_smb_intel },␊
443␉{0x8086, 0x269B, "ESB",␉␉␉read_smb_intel },␊
444␉{0x8086, 0x27DA, "ICH7",␉␉read_smb_intel },␊
445␉{0x8086, 0x283E, "ICH8",␉␉read_smb_intel },␊
446␉{0x8086, 0x2930, "ICH9",␉␉read_smb_intel },␊
447␉{0x8086, 0x3A30, "ICH10",␉␉read_smb_intel },␊
448␉{0x8086, 0x3A60, "ICH10",␉␉read_smb_intel },␊
449␉{0x8086, 0x3B30, "P55",␉␉␉read_smb_intel },␊
450␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel },␊
451␉{0x8086, 0x8119, "US15W",␉␉read_smb_intel },␊
452␉{0x8086, 0x8C22, "HSW",␉␉␉read_smb_intel },␊
453␉{0x8086, 0x8CA2, "Z97/H97",␉␉read_smb_intel },␊
454␉{0x8086, 0x8D22, "X99",␉␉␉read_smb_intel },␊
455␉{0x8086, 0x9C22, "HSW-ULT",␉␉read_smb_intel }␊
456␊
457␉// AMD␊
458//␉{0x1002, 0x4385, "AMD SB600/700",␉... },␊
459//␉{0x1022, 0x780B, "AMD SB800/900",␉... }␊
460␊
461};␊
462␊
463// initial call : pci_dt = root_pci_dev;␊
464// find_and_read_smbus_controller(root_pci_dev);␊
465bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
466{␊
467␉pci_dt_t␉*current = pci_dt;␊
468␉int i;␊
469␊
470␉while (current)␊
471␉{␊
472#if 0␊
473␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
474␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
475␉␉current->class_id, current->vendor_id, current->device_id, ␊
476␉␉get_pci_dev_path(current));␊
477#endif␊
478␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
479␉␉{␊
480␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
481␉␉␉{␊
482␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
483␉␉␉␉return true;␊
484␉␉␉}␊
485␉␉}␊
486␉␉find_and_read_smbus_controller(current->children);␊
487␉␉current = current->next;␊
488␉}␊
489␉return false; // not found␊
490}␊
491␊
492void scan_spd(PlatformInfo_t *p)␊
493{␊
494␉find_and_read_smbus_controller(root_pci_dev);␊
495}␊
496␊
497

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