| 1 | /*␊ |
| 2 | * platform.h␊ |
| 3 | * AsereBLN: reworked and extended␊ |
| 4 | *␊ |
| 5 | */␊ |
| 6 | //Azi:style␊ |
| 7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
| 8 | #define __LIBSAIO_PLATFORM_H␊ |
| 9 | ␊ |
| 10 | #include "libsaio.h"␊ |
| 11 | ␊ |
| 12 | extern bool platformCPUFeature(uint32_t);␊ |
| 13 | extern void scan_platform(void);␊ |
| 14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
| 15 | ␊ |
| 16 | /* CPUID index into cpuid_raw */␊ |
| 17 | #define CPUID_0␉␉␉␉␉0␊ |
| 18 | #define CPUID_1␉␉␉␉␉1␊ |
| 19 | #define CPUID_2␉␉␉␉␉2␊ |
| 20 | #define CPUID_3␉␉␉␉␉3␊ |
| 21 | #define CPUID_4␉␉␉␉␉4␊ |
| 22 | #define CPUID_80␉␉␉␉5␊ |
| 23 | #define CPUID_81␉␉␉␉6␊ |
| 24 | #define CPUID_MAX␉␉␉␉7␊ |
| 25 | ␊ |
| 26 | /* CPU Features */␊ |
| 27 | #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉␉␉// MMX Instruction Set␊ |
| 28 | #define CPU_FEATURE_SSE␉␉␉0x00000002␉␉␉␉// SSE Instruction Set␊ |
| 29 | #define CPU_FEATURE_SSE2␉␉0x00000004␉␉␉␉// SSE2 Instruction Set␊ |
| 30 | #define CPU_FEATURE_SSE3␉␉0x00000008␉␉␉␉// SSE3 Instruction Set␊ |
| 31 | #define CPU_FEATURE_SSE41␉␉0x00000010␉␉␉␉// SSE41 Instruction Set␊ |
| 32 | #define CPU_FEATURE_SSE42␉␉0x00000020␉␉␉␉// SSE42 Instruction Set␊ |
| 33 | #define CPU_FEATURE_EM64T␉␉0x00000040␉␉␉␉// 64Bit Support␊ |
| 34 | #define CPU_FEATURE_HTT␉␉␉0x00000080␉␉␉␉// HyperThreading␊ |
| 35 | #define CPU_FEATURE_MOBILE␉␉0x00000100␉␉␉␉// Mobile CPU␊ |
| 36 | #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉␉␉// MSR Support␊ |
| 37 | ␊ |
| 38 | /* SMBIOS Memory Types */ ␊ |
| 39 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
| 40 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
| 41 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
| 42 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
| 43 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
| 44 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
| 45 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
| 46 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
| 47 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
| 48 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
| 49 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
| 50 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
| 51 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
| 52 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
| 53 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
| 54 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
| 55 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
| 56 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
| 57 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
| 58 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
| 59 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
| 60 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
| 61 | ␊ |
| 62 | /* Memory Configuration Types */ ␊ |
| 63 | #define SMB_MEM_CHANNEL_UNKNOWN␉0␊ |
| 64 | #define SMB_MEM_CHANNEL_SINGLE␉1␊ |
| 65 | #define SMB_MEM_CHANNEL_DUAL␉2␊ |
| 66 | #define SMB_MEM_CHANNEL_TRIPLE␉3␊ |
| 67 | ␊ |
| 68 | /* Maximum number of ram slots */␊ |
| 69 | #define MAX_RAM_SLOTS␉␉␉8␊ |
| 70 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
| 71 | ␊ |
| 72 | /* Maximum number of SPD bytes */␊ |
| 73 | #define MAX_SPD_SIZE␉␉␉256␊ |
| 74 | ␊ |
| 75 | /* Size of SMBIOS UUID in bytes */␊ |
| 76 | #define UUID_LEN␉␉␉␉16␊ |
| 77 | ␊ |
| 78 | typedef struct _RamSlotInfo_t␊ |
| 79 | {␊ |
| 80 | uint32_t␉␉␉␉␉ModuleSize;␉␉␉␉// Size of Module in MB␊ |
| 81 | uint32_t␉␉␉␉␉Frequency;␉␉␉␉// in Mhz␊ |
| 82 | const char*␉␉␉␉␉Vendor;␊ |
| 83 | const char*␉␉␉␉␉PartNo;␊ |
| 84 | const char*␉␉␉␉␉SerialNo;␊ |
| 85 | char*␉␉␉␉␉␉spd;␉␉␉␉␉// SPD Dump␊ |
| 86 | bool␉␉␉␉␉␉InUse;␊ |
| 87 | uint8_t␉␉␉␉␉␉Type;␊ |
| 88 | uint8_t␉␉␉␉␉␉BankConnections;␉␉// table type 6, see (3.3.7)␊ |
| 89 | uint8_t␉␉␉␉␉␉BankConnCnt;␊ |
| 90 | } RamSlotInfo_t;␊ |
| 91 | ␊ |
| 92 | typedef struct _PlatformInfo_t␊ |
| 93 | {␊ |
| 94 | ␉struct CPU␊ |
| 95 | ␉{␊ |
| 96 | ␉␉uint32_t␉␉␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
| 97 | ␉␉uint32_t␉␉␉␉Vendor;␉␉␉␉␉// Vendor␊ |
| 98 | ␉␉uint32_t␉␉␉␉Model;␉␉␉␉␉// Model␊ |
| 99 | ␉␉uint32_t␉␉␉␉ExtModel;␉␉␉␉// Extended Model␊ |
| 100 | ␉␉uint32_t␉␉␉␉Family;␉␉␉␉␉// Family␊ |
| 101 | ␉␉uint32_t␉␉␉␉ExtFamily;␉␉␉␉// Extended Family␊ |
| 102 | ␉␉uint32_t␉␉␉␉NoCores;␉␉␉␉// No Cores per Package␊ |
| 103 | ␉␉uint32_t␉␉␉␉NoThreads;␉␉␉␉// Threads per Package␊ |
| 104 | ␉␉uint8_t␉␉␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊ |
| 105 | ␉␉uint8_t␉␉␉␉␉MaxDiv;␊ |
| 106 | ␉␉uint8_t␉␉␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊ |
| 107 | ␉␉uint8_t␉␉␉␉␉CurrDiv;␊ |
| 108 | ␉␉uint64_t␉␉␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊ |
| 109 | ␉␉uint64_t␉␉␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊ |
| 110 | ␉␉uint64_t␉␉␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊ |
| 111 | ␉␉uint32_t␉␉␉␉BrandString[16];␉␉// 48 Byte Branding String␊ |
| 112 | ␉␉uint32_t␉␉␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
| 113 | ␉} CPU;␊ |
| 114 | ␊ |
| 115 | ␉struct RAM {␊ |
| 116 | ␉␉uint64_t␉␉␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
| 117 | ␉␉uint32_t␉␉␉␉Divider;␉␉␉␉// Memory divider␊ |
| 118 | ␉␉uint8_t␉␉␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
| 119 | ␉␉uint8_t␉␉␉␉␉TRC;␉␉␉␉␉␊ |
| 120 | ␉␉uint8_t␉␉␉␉␉TRP;␊ |
| 121 | ␉␉uint8_t␉␉␉␉␉RAS;␊ |
| 122 | ␉␉uint8_t␉␉␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
| 123 | ␉␉uint8_t␉␉␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
| 124 | ␉␉uint8_t␉␉␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
| 125 | ␉␉RamSlotInfo_t␉␉DIMM[MAX_RAM_SLOTS];␉␉// Information about each slot␊ |
| 126 | ␉} RAM;␊ |
| 127 | ␊ |
| 128 | ␉struct DMI␊ |
| 129 | ␉{␊ |
| 130 | ␉␉int␉␉␉␉␉␉MaxMemorySlots;␉␉␉// number of memory slots polulated by SMBIOS␊ |
| 131 | ␉␉int␉␉␉␉␉␉CntMemorySlots;␉␉␉// number of memory slots counted␊ |
| 132 | ␉␉int␉␉␉␉␉␉MemoryModules;␉␉␉// number of memory modules installed␊ |
| 133 | ␉␉int␉␉␉␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
| 134 | ␉} DMI;␊ |
| 135 | ␉uint8_t␉␉␉␉␉␉Type;␉␉␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊ |
| 136 | } PlatformInfo_t;␊ |
| 137 | ␊ |
| 138 | extern PlatformInfo_t Platform;␊ |
| 139 | ␊ |
| 140 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
| 141 | |
