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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9␊
10#ifndef DEBUG_CPU␊
11#define DEBUG_CPU 0 //Azi:---␊
12#endif␊
13␊
14#if DEBUG_CPU␊
15#define DBG(x...)␉␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20/*␊
21 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␉<---Azi:tsc␊
22 */␊
23static uint64_t measure_tsc_frequency(void)␊
24{␊
25 uint64_t tscStart;␊
26 uint64_t tscEnd;␊
27 uint64_t tscDelta = 0xffffffffffffffffULL;␊
28 unsigned long pollCount;␊
29 uint64_t retval = 0;␊
30 int i;␊
31␊
32 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
33 * counter 2. We run this loop 3 times to make sure the cache␊
34 * is hot and we take the minimum delta from all of the runs.␊
35 * That is to say that we're biased towards measuring the minimum␊
36 * number of TSC ticks that occur while waiting for the timer to␊
37 * expire. That theoretically helps avoid inconsistencies when␊
38 * running under a VM if the TSC is not virtualized and the host␊
39 * steals time. The TSC is normally virtualized for VMware.␊
40 */␊
41 for(i = 0; i < 10; ++i)␊
42 {␊
43 enable_PIT2();␊
44 set_PIT2_mode0(CALIBRATE_LATCH);␊
45 tscStart = rdtsc64();␊
46 pollCount = poll_PIT2_gate();␊
47 tscEnd = rdtsc64();␊
48 /* The poll loop must have run at least a few times for accuracy */␊
49 if(pollCount <= 1)␊
50 continue;␊
51 /* The TSC must increment at LEAST once every millisecond. We␊
52 * should have waited exactly 30 msec so the TSC delta should␊
53 * be >= 30. Anything less and the processor is way too slow.␊
54 */␊
55 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
56 continue;␊
57 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
58 if( (tscEnd - tscStart) < tscDelta )␊
59 tscDelta = tscEnd - tscStart;␊
60 }␊
61 /* tscDelta is now the least number of TSC ticks the processor made in␊
62 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
63 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
64 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
65 * Hz so we need to convert our milliseconds to seconds. Since we're␊
66 * dividing by the milliseconds, we simply multiply by 1000.␊
67 */␊
68␊
69 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
70 * that we're going to multiply by 1000 first so we do need at least some␊
71 * arithmetic headroom. For now, 32-bit should be enough.␊
72 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
73 */␊
74 if(tscDelta > (1ULL<<32))␊
75 retval = 0;␊
76 else␊
77 {␊
78 retval = tscDelta * 1000 / 30;␊
79 }␊
80 disable_PIT2();␊
81 return retval;␊
82}␊
83␊
84/*␊
85 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
86 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
87 * a max multi. (used to calculate the FSB freq.),␊
88 * and a current multi. (used to calculate the CPU freq.)␊
89 * - fsbFrequency = tscFrequency / multi␉␉␉␉␉␉␉␉␉<---Azi:fsb␊
90 * - cpuFrequency = fsbFrequency * multi␊
91 */␊
92␊
93void scan_cpu(PlatformInfo_t *p)␊
94{␊
95␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
96␉uint64_t␉msr, flex_ratio;␊
97␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv;␊
98␊
99␉maxcoef = maxdiv = currcoef = currdiv = 0;␊
100␊
101␉/* get cpuid values */␊
102␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
103␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
104␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
105␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
106␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
107␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
108␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
109␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
110␉}␊
111#if DEBUG_CPU␊
112␉{␊
113␉␉int␉␉i;␊
114␉␉printf("CPUID Raw Values:\n");␊
115␉␉for (i=0; i<CPUID_MAX; i++) {␊
116␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
117␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
118␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
119␉␉}␊
120␉}␊
121#endif␊
122␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
123␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
124␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
125␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
126␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
127␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
128␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
129␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
130␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
131␊
132␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
133␉␊
134␉/* get brand string (if supported) */␊
135␉/* Copyright: from Apple's XNU cpuid.c */␊
136␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
137␉␉uint32_t␉reg[4];␊
138 char str[128], *s;␊
139␉␉/*␊
140␉␉ * The brand string 48 bytes (max), guaranteed to␊
141␉␉ * be NUL terminated.␊
142␉␉ */␊
143␉␉do_cpuid(0x80000002, reg);␊
144␉␉bcopy((char *)reg, &str[0], 16);␊
145␉␉do_cpuid(0x80000003, reg);␊
146␉␉bcopy((char *)reg, &str[16], 16);␊
147␉␉do_cpuid(0x80000004, reg);␊
148␉␉bcopy((char *)reg, &str[32], 16);␊
149␉␉for (s = str; *s != '\0'; s++) {␊
150␉␉␉if (*s != ' ') break;␊
151␉␉}␊
152␉␉␊
153␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
154␉␉␊
155␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
156␉␉␉ /*␊
157␉␉␉ * This string means we have a firmware-programmable brand string,␊
158␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
159␉␉␉ */␊
160␉␉␉ p->CPU.BrandString[0] = '\0';␊
161␉␉ }␊
162␉}␊
163␉␊
164␉/* setup features */␊
165␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
166␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
167␉}␊
168␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
169␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
170␉}␊
171␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
172␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
173␉}␊
174␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
175␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
176␉}␊
177␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
178␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
179␉}␊
180␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
181␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
182␉}␊
183␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
184␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
185␉}␊
186␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
187␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
188␉}␊
189␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
190␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
191␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
192␉}␊
193␊
194␉tscFrequency = measure_tsc_frequency();␊
195␉fsbFrequency = 0;␊
196␉cpuFrequency = 0;␊
197␉␊
198␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f/*Azi:fsb, my fam*/))) {␊
199␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03/*Azi:fsb, my fam/model*/)) {␊
200␉␉␉/* Nehalem CPU model */␊
201␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e␊
202␉␉␉ || p->CPU.Model == 0x1f || p->CPU.Model == 0x25 || p->CPU.Model == 0x2c)) {␊
203␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
204␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
205␉␉␉␉currcoef = (msr >> 8) & 0xff;␊
206␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
207␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
208␉␉␉␉if ((msr >> 16) & 0x01) {␊
209␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
210␉␉␉␉␉if (currcoef > flex_ratio) {␊
211␉␉␉␉␉␉currcoef = flex_ratio;␊
212␉␉␉␉␉}␊
213␉␉␉␉}␊
214␊
215␉␉␉␉if (currcoef)␊
216␉␉␉␉{␊
217␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
218␉␉␉␉}␊
219␉␉␉␉cpuFrequency = tscFrequency;␊
220␉␉␉}␊
221␉␉␉else␊
222␉␉␉{␊
223␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
224␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
225␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
226␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
227␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
228␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
229␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
230␊
231␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
232␉␉␉␉{␊
233␉␉␉␉␉/* On these models, maxcoef defines TSC freq Azi:fsb mine */␊
234␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
235␉␉␉␉}␊
236␉␉␉␉else␊
237␉␉␉␉{␊
238␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
239␉␉␉␉␉/* XXX */␊
240␉␉␉␉␉maxcoef = currcoef;␊
241␉␉␉␉}␊
242␊
243␉␉␉␉if (maxcoef)␊
244␉␉␉␉{␊
245␉␉␉␉␉if (maxdiv)␊
246␉␉␉␉␉{␊
247␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
248␉␉␉␉␉}␊
249␉␉␉␉␉else␊
250␉␉␉␉␉{␊
251␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
252␉␉␉␉␉}␊
253␉␉␉␉␉␊
254␉␉␉␉␉if (currdiv)␊
255␉␉␉␉␉{␊
256␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
257␉␉␉␉␉}␊
258␉␉␉␉␉else␊
259␉␉␉␉␉{␊
260␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
261␉␉␉␉␉}␊
262␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
263␉␉␉␉}␊
264␉␉␉}␊
265␉␉}␊
266␉␉/* Mobile CPU ? */␊
267␉␉if (rdmsr64(0x17) & (1<<28)) {␊
268␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
269␉␉}␊
270␉}␊
271#if 0␊
272␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
273␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
274␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
275␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
276␉␉␉currdiv = (msr & 0x01) * 2;␊
277␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
278␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
279␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
280␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
281␉␉␉else /* K11+ */␊
282␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
283␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
284␉␉}␊
285␊
286␉␉if (currcoef) {␊
287␉␉␉if (currdiv) {␊
288␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
289␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
290␉␉␉} else {␊
291␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
292␉␉␉␉DBG("%d\n", currcoef);␊
293␉␉␉}␊
294␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
295␉␉␉cpuFrequency = tscFrequency;␊
296␉␉}␊
297␉}␊
298␊
299␉if (!fsbFrequency) {␊
300␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
301␉␉cpuFrequency = tscFrequency;␊
302␉␉DBG("0 ! using the default value for FSB !\n");␊
303␉}␊
304#endif␊
305␊
306␉p->CPU.MaxCoef = maxcoef;␊
307␉p->CPU.MaxDiv = maxdiv;␊
308␉p->CPU.CurrCoef = currcoef;␊
309␉p->CPU.CurrDiv = currdiv;␊
310␉p->CPU.TSCFrequency = tscFrequency;␊
311␉p->CPU.FSBFrequency = fsbFrequency;␊
312␉p->CPU.CPUFrequency = cpuFrequency;␊
313#if DEBUG_CPU␊
314␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
315␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
316␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
317␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
318␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
319␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
320␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
321␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
322␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
323␉pause();␊
324#endif␊
325}␊
326

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