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Root/branches/azimutz/Chazileon/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "saio_internal.h"␊
14#include "bootstruct.h"␊
15#include "memvendors.h"␊
16␊
17#ifndef DEBUG_SPD␊
18#define DEBUG_SPD 0␊
19#endif␊
20␊
21#if DEBUG_SPD␊
22#define DBG(x...)␉printf(x)␊
23#else␊
24#define DBG(x...)␊
25#endif␊
26␊
27static const char *spd_memory_types[] =␊
28{␊
29␉"RAM", // 00h Undefined␊
30␉"FPM", // 01h FPM␊
31␉"EDO", // 02h EDO␊
32␉"",␉␉␉␉// 03h PIPELINE NIBBLE␊
33␉"SDRAM", // 04h SDRAM␊
34␉"",␉␉␉␉// 05h MULTIPLEXED ROM␊
35␉"DDR SGRAM",␉// 06h SGRAM DDR␊
36␉"DDR SDRAM",␉// 07h SDRAM DDR␊
37␉"DDR2 SDRAM", // 08h SDRAM DDR 2␊
38␉"",␉␉␉␉// 09h Undefined␊
39␉"",␉␉␉␉// 0Ah Undefined␊
40␉"DDR3 SDRAM" // 0Bh SDRAM DDR 3␊
41};␊
42␊
43#define UNKNOWN_MEM_TYPE 2␊
44static uint8_t spd_mem_to_smbios[] =␊
45{␊
46␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
47␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
48␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
49␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
50␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
51␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
52␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
53␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
54␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
55␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
56␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
57␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
58};␊
59#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
60␊
61#define rdtsc(low,high) \␊
62__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
63␊
64#define SMBHSTSTS 0␊
65#define SMBHSTCNT 2␊
66#define SMBHSTCMD 3␊
67#define SMBHSTADD 4␊
68#define SMBHSTDAT 5␊
69#define SBMBLKDAT 7␊
70␊
71/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
72unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
73{␊
74 int l1, h1, l2, h2;␊
75 unsigned long long t;␊
76␉␊
77 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
78 outb(base + SMBHSTDAT, 0xff);␊
79␉␊
80 while( inb(base + SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
81␉␊
82 outb(base + SMBHSTCMD, cmd);␊
83 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
84 outb(base + SMBHSTCNT, 0x48 );␊
85␉␊
86 rdtsc(l1, h1);␊
87␉␊
88 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
89␉{␉␊
90␉␉rdtsc(l2, h2);␊
91␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
92␉␉if (t > 5)␊
93␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
94 }␊
95 return inb(base + SMBHSTDAT);␊
96}␊
97␊
98/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
99#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
100␊
101int spd_indexes[] = {␊
102␉SPD_MEMORY_TYPE,␊
103␉SPD_DDR3_MEMORY_BANK,␊
104␉SPD_DDR3_MEMORY_CODE,␊
105␉SPD_NUM_ROWS,␊
106␉SPD_NUM_COLUMNS,␊
107␉SPD_NUM_DIMM_BANKS,␊
108␉SPD_NUM_BANKS_PER_SDRAM,␊
109␉4,7,8,9,12,64, /* TODO: give names to these values */␊
110␉95,96,97,98, 122,123,124,125 /* UIS */␊
111};␊
112#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
113␊
114/** Read from spd *used* values only*/␊
115static void init_spd(char * spd, uint32_t base, int slot)␊
116{␊
117␉int i;␊
118␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
119␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
120␉}␊
121}␊
122␊
123/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
124 have different formats, always return a valid ptr.*/␊
125const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
126{␊
127 uint8_t bank = 0;␊
128 uint8_t code = 0;␊
129 int i = 0;␊
130 uint8_t * spd = (uint8_t *) slot->spd;␊
131␊
132 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
133 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
134 code = spd[SPD_DDR3_MEMORY_CODE];␊
135 for (i=0; i < VEN_MAP_SIZE; i++)␊
136 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
137 return vendorMap[i].name;␊
138 }␊
139 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
140 if(spd[64]==0x7f) {␊
141 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
142␉␉␉ bank++;␊
143␉␉␉ READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
144␉␉␉}␊
145␉␉␉READ_SPD(spd, base, slot_num,i);␊
146 code = spd[i];␊
147 } else {␊
148 code = spd[64]; ␊
149 bank = 0;␊
150 }␊
151 for (i=0; i < VEN_MAP_SIZE; i++)␊
152 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
153 return vendorMap[i].name;␊
154 }␊
155 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
156 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
157 return "Unifosa";␊
158 return "NoName";␊
159}␊
160␊
161/** Get Default Memory Module Speed (no overclocking handled) */␊
162int getDDRspeedMhz(const char * spd)␊
163{␊
164 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
165 switch(spd[12]) { // byte 12␊
166 case 0x0f:␊
167 return 1066; // data rate, not Mhz!␊
168 case 0x0c:␊
169 return 1333;␊
170 case 0x0a:␊
171 return 1600;␊
172 case 0x14: // 800␊
173 default:␊
174 return 800;␊
175 }␊
176 } ␊
177 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
178 switch(spd[9]) { // byte 9␊
179 case 0x50:␊
180 return 400;␊
181 case 0x3d:␊
182 return 533;␊
183 case 0x30:␊
184 return 667;␊
185 case 0x25: // 800␊
186 default:␊
187 return 800;␊
188 }␊
189 }␊
190 return 800; // default freq for unknown types␊
191} //Azi: works fine for my DDR2.␊
192␊
193#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4)) // msbit?␊
194#define SLST(a) ((uint8_t)(spd[a] & 0x0f)) // lsbit?␊
195␊
196/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
197const char *getDDRSerial(const char* spd)␊
198{␊
199 static char asciiSerial[16];␊
200 ␊
201 if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
202 {␊
203␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7 Azi:msb*/, SLST(122), SMST(123), SLST(123),␊
204␉␉␉␉␉␉␉␉␉␉␉SMST(124), SLST(124), SMST(125), SLST(125));␊
205␊
206 }␊
207 else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR␊
208 { ␊
209␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96),␊
210␉␉␉␉␉␉␉␉␉␉␉SMST(97), SLST(97), SMST(98), SLST(98));␊
211 }␊
212␊
213 return strdup(asciiSerial);␊
214}␊
215␊
216/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
217const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
218{␊
219␉static char asciiPartNo[32];␊
220␉int i, start = 0, index = 0;␊
221␊
222 if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)␊
223␉{␊
224␉␉start = 128;␊
225␉}␊
226 else␊
227␉if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2)␊
228␉{␊
229␉␉start = 73;␊
230␉}␊
231␉␊
232␉memset(asciiPartNo, 0, sizeof(asciiPartNo));␊
233␉␊
234␉char c;␊
235␉␊
236␉for (i = start; i < start + sizeof(asciiPartNo); i++)␊
237␉{␊
238␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
239␉␉␊
240␉␉c = spd[i];␊
241␉␉␊
242␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
243␉␉␉asciiPartNo[index++] = c;␊
244␉␉else␊
245␉␉if (isspace(c)) //Azi: break at first space␊
246␉␉␉break;␊
247␉}␊
248␉␊
249␉return strdup(asciiPartNo);␊
250 return NULL; //Azi: ???␊
251}␊
252␊
253int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
254␊
255␊
256/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
257static void read_smb_intel(pci_dt_t *smbus_dev)␊
258{ ␊
259 int i, speed;␊
260 uint8_t spd_size, spd_type;␊
261 uint32_t base;␊
262 bool dump = false;␊
263 RamSlotInfo_t* slot;␊
264␊
265 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
266 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
267␊
268 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
269 bool fullBanks = // needed at least for laptops␊
270 Platform.DMI.MemoryModules == Platform.DMI.MaxMemorySlots;␊
271 // Search MAX_RAM_SLOTS slots␊
272␉char spdbuf[256];␊
273␊
274 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
275 slot = &Platform.RAM.DIMM[i];␊
276 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
277 // Check spd is present␊
278 if (spd_size && (spd_size != 0xff) ) {␊
279␊
280␉␉␉slot->spd = spdbuf;␊
281 slot->InUse = true;␊
282␊
283 bzero(slot->spd, spd_size);␊
284 ␊
285 // Copy spd data into buffer␊
286 ␊
287␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
288 init_spd(slot->spd, base, i);␊
289␉␉␉␊
290 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
291 case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
292 ␊
293 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
294 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
295 break;␊
296 ␊
297 case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
298 ␊
299 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
300 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
301 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
302 ␊
303 break;␊
304 }␊
305 ␊
306 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
307 slot->Type = spd_mem_to_smbios[spd_type];␊
308 slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
309 slot->Vendor = getVendorName(slot, base, i);␊
310 slot->SerialNo = getDDRSerial(slot->spd);␊
311␊
312 // determine spd speed␊
313 speed = getDDRspeedMhz(slot->spd);␊
314 if (slot->Frequency<speed) slot->Frequency = speed;␊
315␉␉␉␊
316␉␉␉// pci memory controller if available, is more reliable␊
317␉␉␉if (Platform.RAM.Frequency > 0) {␊
318␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
319␉␉␉␉// now round off special cases␊
320␉␉␉␉uint32_t fmod100 = freq %100;␊
321␉␉␉␉switch(fmod100) {␊
322␉␉␉␉␉case 1:␉freq--;␉break;␊
323␉␉␉␉␉case 32:␉freq++;␉break;␊
324␉␉␉␉␉case 65:␉freq++; break;␊
325␉␉␉␉␉case 98:␉freq+=2;break;␊
326␉␉␉␉␉case 99:␉freq++; break;␊
327␉␉␉␉}␊
328␉␉␉␉slot->Frequency = freq;␊
329␉␉␉}␊
330␉␉␉␊
331␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
332 i, ␊
333 (int)slot->Type,␊
334 slot->ModuleSize, ␊
335 spd_memory_types[spd_type],␊
336 slot->Frequency,␊
337 slot->Vendor,␊
338 slot->PartNo,␊
339 slot->SerialNo);␊
340␉␉␉if(DEBUG_SPD) {␊
341 dumpPhysAddr("spd content: ",slot->spd, spd_size);␊
342 getc();␊
343 }␊
344 }␊
345␊
346 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
347 Platform.DMI.DIMM[i]= ␊
348 i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots==2 ? ␊
349 mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
350 ␊
351␉␉slot->spd = NULL;␊
352␊
353 } // for␊
354}␊
355␊
356static struct smbus_controllers_t smbus_controllers[] = {␊
357␊
358␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
359␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
360␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
361␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
362␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
363␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
364␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
365␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
366␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
367␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
368␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
369␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
370␊
371};␊
372␊
373// initial call : pci_dt = root_pci_dev;␊
374// find_and_read_smbus_controller(root_pci_dev);␊
375bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
376{␊
377 pci_dt_t␉*current = pci_dt;␊
378 int i;␊
379␊
380 while (current) {␊
381#if 0␊
382 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
383 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
384 current->class_id, current->vendor_id, current->device_id, ␊
385 get_pci_dev_path(current));␊
386#endif␊
387␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
388 {␊
389 if (current->vendor_id == smbus_controllers[i].vendor &&␊
390 current->device_id == smbus_controllers[i].device)␊
391 {␊
392 smbus_controllers[i].read_smb(current); // read smb␊
393 return true;␊
394 } ␊
395 }␊
396 find_and_read_smbus_controller(current->children);␊
397 current = current->next;␊
398 }␊
399 return false; // not found␊
400}␊
401␊
402void scan_spd(PlatformInfo_t *p)␊
403{␊
404 find_and_read_smbus_controller(root_pci_dev);␊
405}␊
406

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