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1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "boot.h"␊
12#include "bootstruct.h"␊
13#include "pci.h"␊
14␊
15#ifndef DEBUG_USB␊
16#define DEBUG_USB 0␊
17#endif␊
18␊
19#if DEBUG_USB␊
20#define DBG(x...)␉printf(x)␊
21#else␊
22#define DBG(x...)␊
23#endif␊
24␊
25␊
26struct pciList␊
27{␊
28␉pci_dt_t* pciDev;␊
29␉struct pciList* next;␊
30};␊
31␊
32struct pciList* usbList = NULL;␊
33␊
34int legacy_off (pci_dt_t *pci_dev);␊
35int ehci_acquire (pci_dt_t *pci_dev);␊
36int uhci_reset (pci_dt_t *pci_dev);␊
37␊
38// Add usb device to the list␊
39void notify_usb_dev(pci_dt_t *pci_dev)␊
40{␊
41␉struct pciList* current = usbList;␊
42␉if(!usbList)␊
43␉{␊
44␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
45␉␉usbList->next = NULL;␊
46␉␉usbList->pciDev = pci_dev;␊
47␉}␊
48␉else␊
49␉{␊
50␉␉while(current != NULL && current->next != NULL)␊
51␉␉{␊
52␉␉␉current = current->next;␊
53␉␉}␊
54␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
55␉␉current = current->next;␊
56␉␉␊
57␉␉current->pciDev = pci_dev;␊
58␉␉current->next = NULL;␊
59␉}␊
60}␊
61␊
62// Loop through the list and call the apropriate patch function␊
63int usb_loop()␊
64{␊
65␉int retVal = 1;␊
66␉bool fix_ehci, fix_uhci, fix_usb, fix_legacy;␊
67␉fix_ehci = fix_uhci = fix_usb = fix_legacy = false;␊
68␉␊
69␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))␊
70␉{␊
71␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊
72␉}␊
73␉else ␊
74␉{␊
75␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊
76␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊
77␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊
78␉}␊
79␉␊
80␉struct pciList* current = usbList;␊
81␉␊
82␉while(current)␊
83␉{␊
84␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
85␉␉{␊
86␉␉␉// EHCI␊
87␉␉␉case 0x20:␊
88␉␉ ␉if (fix_ehci)␊
89␉␉␉␉␉retVal &= ehci_acquire(current->pciDev);␊
90␉␉␉␉␊
91␉␉ ␉if (fix_legacy)␊
92␉␉␉␉␉retVal &= legacy_off(current->pciDev);␊
93␉␉␉␉␊
94␉␉␉␉break;␊
95␉␉␉␉␊
96␉␉␉// UHCI␊
97␉␉␉case 0x00:␊
98␉␉␉␉if (fix_uhci)␊
99␉␉␉␉␉retVal &= uhci_reset(current->pciDev);␊
100␊
101␉␉␉␉break;␊
102␉␉}␊
103␉␉␊
104␉␉current = current->next;␊
105␉}␊
106␉return retVal;␊
107}␊
108␊
109int legacy_off (pci_dt_t *pci_dev)␊
110{␊
111␉// Set usb legacy off modification by Signal64␊
112␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
113␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
114␉// AKA: Make this run immediatly before the kernel is called␊
115␉uint32_t␉capaddr, opaddr; ␉␉␊
116␉uint8_t␉␉eecp;␉␉␉␊
117␉uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊
118␉uint32_t␉usblegsup, usblegctlsts;␉␉␊
119␉␊
120␉int isOSowned;␊
121␉int isBIOSowned;␊
122␉␊
123␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
124␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
125␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
126␉␊
127␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
128␉capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
129␉␊
130␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
131␉opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
132␉␊
133␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
134␉eecp = *((unsigned char*)(capaddr + 9));␊
135␉␊
136␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
137␉␊
138␉usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
139␉usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
140␉usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
141␉␊
142␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
143␉␊
144␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
145␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
146␉␊
147␉// informational only␊
148␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
149␉isOSowned = !!((usblegsup) & (1 << (24)));␊
150␉␊
151␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
152␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
153␉␊
154␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
155␉␊
156␉// Reset registers to Legacy OFF␊
157␉DBG("Clearing USBLEGCTLSTS\n");␊
158␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
159␉␊
160␉// if delay value is in milliseconds it doesn't appear to work. ␊
161␉// setting value to anything up to 65535 does not add the expected delay here.␊
162␉delay(100);␊
163␉␊
164␉usbcmd = *((unsigned int*)(opaddr));␊
165␉usbsts = *((unsigned int*)(opaddr + 4));␊
166␉usbintr = *((unsigned int*)(opaddr + 8));␊
167␉␊
168␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
169␉␊
170␉DBG("Clearing Registers\n");␊
171␉␊
172␉// clear registers to default␊
173␉usbcmd = (usbcmd & 0xffffff00);␊
174␉*((unsigned int*)(opaddr)) = usbcmd;␊
175␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
176␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
177␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
178␉␊
179␉// get the results␊
180␉usbcmd = *((unsigned int*)(opaddr));␊
181␉usbsts = *((unsigned int*)(opaddr + 4));␊
182␉usbintr = *((unsigned int*)(opaddr + 8));␊
183␉␊
184␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
185␉␊
186␉// read 32bit USBLEGSUP (eecp+0) ␊
187␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
188␉␊
189␉// informational only␊
190␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
191␉isOSowned = !!((usblegsup) & (1 << (24)));␊
192␉␊
193␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
194␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
195␉␊
196␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
197␉␊
198␉verbose("Legacy USB Off Done\n");␉␊
199␉return 1;␊
200}␊
201␊
202int ehci_acquire (pci_dt_t *pci_dev)␊
203{␊
204␉int␉␉j, k;␊
205␉uint32_t␉base;␊
206␉uint8_t␉␉eecp;␊
207␉uint8_t␉␉legacy[8];␊
208␉bool␉␉isOwnershipConflict;␉␊
209␉bool␉␉alwaysHardBIOSReset;␊
210␊
211␉alwaysHardBIOSReset = false;␉␊
212␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
213␉␉alwaysHardBIOSReset = true;␊
214␉}␊
215␊
216␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
217␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
218␊
219␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
220␉␉pci_dev->vendor_id, pci_dev->device_id,␊
221␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
222␉␉base);␊
223␊
224␉if (*((unsigned char*)base) < 0xc)␊
225␉{␊
226␉␉DBG("Config space too small: no legacy implementation\n");␊
227␉␉return 1;␊
228␉}␊
229␉eecp = *((unsigned char*)(base + 9));␊
230␉if (!eecp) {␊
231␉␉DBG("No extended capabilities: no legacy implementation\n");␊
232␉␉return 1;␊
233␉}␊
234␊
235␉DBG("eecp=%x\n",eecp);␊
236␊
237␉// bad way to do it␊
238␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
239␉for (j = 0; j < 8; j++) {␊
240␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
241␉␉DBG("%02x ", legacy[j]);␊
242␉}␊
243␉DBG("\n");␊
244␊
245␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
246␉//We try soft reset first - some systems hang on reboot with hard reset␊
247␉// Definitely needed during reboot on 10.4.6␊
248␊
249␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊
250␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
251␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
252␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
253␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
254␉␉for (k = 0; k < 25; k++) {␊
255␉␉␉for (j = 0; j < 8; j++) {␊
256␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
257␉␉␉}␊
258␉␉␉if (legacy[3] == 0) {␊
259␉␉␉␉break;␊
260␉␉␉}␊
261␉␉␉delay(10);␊
262␉␉}␊
263␉}␉␊
264␊
265␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
266␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
267␊
268␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
269␉for (k = 0; k < 25; k++) {␊
270␉␉for (j = 0;j < 8; j++) {␊
271␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
272␉␉}␊
273␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
274␉␉if (legacy[2] == 0) {␊
275␉␉␉break;␊
276␉␉}␊
277␉␉delay(10);␊
278␉}␊
279␊
280␉for (j = 0;j < 8; j++) {␊
281␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
282␉}␊
283␉isOwnershipConflict = ((legacy[2]) != 0);␊
284␉if (isOwnershipConflict) {␊
285␉␉// Soft reset has failed. Assume SMI being ignored␊
286␉␉// Hard reset␊
287␉␉// Force Clear BIOS BIT␊
288␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
289␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
290␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
291␊
292␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
293␉␉for (k = 0; k < 25; k++) {␊
294␉␉␉for (j = 0; j < 8; j++) {␊
295␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
296␉␉␉}␊
297␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
298␊
299␉␉␉if ((legacy[2]) == 0) {␊
300␉␉␉␉break;␊
301␉␉␉}␊
302␉␉␉delay(10);␉␊
303␉␉}␉␉␊
304␉␉// Disable further SMI events␊
305␉␉for (j = 4; j < 8; j++) {␊
306␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
307␉␉}␊
308␉}␊
309␊
310␉for (j = 0; j < 8; j++) {␊
311␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
312␉}␊
313␊
314␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
315␊
316␉// Final Ownership Resolution Check...␊
317␉if (legacy[2] & 1) {␉␉␉␉␉␊
318␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
319␉␉return 0;␊
320␉}␊
321␊
322␉DBG("EHCI Acquire OS Ownership done\n");␉␊
323␉return 1;␊
324}␊
325␊
326int uhci_reset (pci_dt_t *pci_dev)␊
327{␊
328␉uint32_t base, port_base;␊
329␉␊
330␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
331␉port_base = (base >> 5) & 0x07ff;␊
332␊
333␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
334␉␉pci_dev->vendor_id, pci_dev->device_id,␊
335␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
336␉␉port_base, base);␊
337␉␊
338␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
339␊
340␉outw (port_base, 0x0002);␊
341␉delay(10);␊
342␉outw (port_base+4,0);␊
343␉delay(10);␊
344␉outw (port_base,0);␊
345␉return 1;␊
346}␊
347

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