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Root/branches/rekursor/i386/libsaio/nvidia.c

1/*␊
2 * NVidia injector␊
3 *␊
4 * Copyright (C) 2009 Jasmin Fazlic, iNDi␊
5 *␊
6 * NVidia injector is free software: you can redistribute it and/or modify␊
7 * it under the terms of the GNU General Public License as published by␊
8 * the Free Software Foundation, either version 3 of the License, or␊
9 * (at your option) any later version.␊
10 *␊
11 * NVidia driver and injector is distributed in the hope that it will be useful,␊
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 * GNU General Public License for more details.␊
15 *␊
16 * You should have received a copy of the GNU General Public License␊
17 * along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "libsaio.h"␊
52#include "boot.h"␊
53#include "bootstruct.h"␊
54#include "pci.h"␊
55#include "platform.h"␊
56#include "device_inject.h"␊
57#include "nvidia.h"␊
58␊
59#ifndef DEBUG_NVIDIA␊
60#define DEBUG_NVIDIA 0␊
61#endif␊
62␊
63#if DEBUG_NVIDIA␊
64#define DBG(x...)␉printf(x)␊
65#else␊
66#define DBG(x...)␊
67#endif␊
68␊
69#define NVIDIA_ROM_SIZE 0x10000␊
70#define PATCH_ROM_SUCCESS 1␊
71#define PATCH_ROM_SUCCESS_HAS_LVDS 2␊
72#define PATCH_ROM_FAILED 0␊
73#define MAX_NUM_DCB_ENTRIES 16␊
74␊
75#define TYPE_GROUPED 0xff␊
76␊
77extern uint32_t devices_number;␊
78␊
79const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac" };␊
80const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac" };␊
81const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display" };␊
82const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display" };␊
83const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent" };␊
84const char *nvidia_name_0[]␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
85const char *nvidia_name_1[]␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
86const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉"Slot-1" };␊
87␊
88static uint8_t default_NVCAP[]= {␊
89␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
90␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
91␉0x00, 0x00, 0x00, 0x00␊
92};␊
93␊
94static struct nv_chipsets_t NVKnownChipsets[] = {␊
95␉{ 0x00000000, "Unknown" },␊
96␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
97␉{ 0x10DE0041, "GeForce 6800" },␊
98␉{ 0x10DE0042, "GeForce 6800 LE" },␊
99␉{ 0x10DE0043, "GeForce 6800 XE" },␊
100␉{ 0x10DE0044, "GeForce 6800 XT" },␊
101␉{ 0x10DE0045, "GeForce 6800 GT" },␊
102␉{ 0x10DE0046, "GeForce 6800 GT" },␊
103␉{ 0x10DE0047, "GeForce 6800 GS" },␊
104␉{ 0x10DE0048, "GeForce 6800 XT" },␊
105␉{ 0x10DE004E, "Quadro FX 4000" },␊
106␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
107␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
108␉{ 0x10DE0092, "GeForce 7800 GT" },␊
109␉{ 0x10DE0093, "GeForce 7800 GS" },␊
110␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
111␉{ 0x10DE0098, "GeForce Go 7800" },␊
112␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
113␉{ 0x10DE009D, "Quadro FX 4500" },␊
114␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
115␉{ 0x10DE00C1, "GeForce 6800" },␊
116␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
117␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
118␉{ 0x10DE00C8, "GeForce Go 6800" },␊
119␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
120␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
121␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
122␉{ 0x10DE00CE, "Quadro FX 1400" },␊
123␉{ 0x10DE0140, "GeForce 6600 GT" },␊
124␉{ 0x10DE0141, "GeForce 6600" },␊
125␉{ 0x10DE0142, "GeForce 6600 LE" },␊
126␉{ 0x10DE0143, "GeForce 6600 VE" },␊
127␉{ 0x10DE0144, "GeForce Go 6600" },␊
128␉{ 0x10DE0145, "GeForce 6610 XL" },␊
129␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
130␉{ 0x10DE0147, "GeForce 6700 XL" },␊
131␉{ 0x10DE0148, "GeForce Go 6600" },␊
132␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
133␉{ 0x10DE014C, "Quadro FX 550" },␊
134␉{ 0x10DE014D, "Quadro FX 550" },␊
135␉{ 0x10DE014E, "Quadro FX 540" },␊
136␉{ 0x10DE014F, "GeForce 6200" },␊
137␉{ 0x10DE0160, "GeForce 6500" },␊
138␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
139␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
140␉{ 0x10DE0163, "GeForce 6200 LE" },␊
141␉{ 0x10DE0164, "GeForce Go 6200" },␊
142␉{ 0x10DE0165, "Quadro NVS 285" },␊
143␉{ 0x10DE0166, "GeForce Go 6400" },␊
144␉{ 0x10DE0167, "GeForce Go 6200" },␊
145␉{ 0x10DE0168, "GeForce Go 6400" },␊
146␉{ 0x10DE0169, "GeForce 6250" },␊
147␉{ 0x10DE016A, "GeForce 7100 GS" },␊
148␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
149␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
150␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
151␉{ 0x10DE019D, "Quadro FX 5600" },␊
152␉{ 0x10DE019E, "Quadro FX 4600" },␊
153␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
154␉{ 0x10DE01D3, "GeForce 7300 SE" },␊
155␉{ 0x10DE01D6, "GeForce Go 7200" },␊
156␉{ 0x10DE01D7, "GeForce Go 7300" },␊
157␉{ 0x10DE01D8, "GeForce Go 7400" },␊
158␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
159␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
160␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
161␉{ 0x10DE01DC, "Quadro FX 350M" },␊
162␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
163␉{ 0x10DE01DE, "Quadro FX 350" },␊
164␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
165␉{ 0x10DE0211, "GeForce 6800" },␊
166␉{ 0x10DE0212, "GeForce 6800 LE" },␊
167␉{ 0x10DE0215, "GeForce 6800 GT" },␊
168␉{ 0x10DE0218, "GeForce 6800 XT" },␊
169␉{ 0x10DE0221, "GeForce 6200" },␊
170␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
171␉{ 0x10DE0240, "GeForce 6150" },␊
172␉{ 0x10DE0241, "GeForce 6150 LE" },␊
173␉{ 0x10DE0242, "GeForce 6100" },␊
174␉{ 0x10DE0244, "GeForce Go 6150" },␊
175␉{ 0x10DE0247, "GeForce Go 6100" },␊
176␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
177␉{ 0x10DE0291, "GeForce 7900 GT" },␊
178␉{ 0x10DE0292, "GeForce 7900 GS" },␊
179␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
180␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
181␉{ 0x10DE029A, "Quadro FX 2500M" },␊
182␉{ 0x10DE029B, "Quadro FX 1500M" },␊
183␉{ 0x10DE029C, "Quadro FX 5500" },␊
184␉{ 0x10DE029D, "Quadro FX 3500" },␊
185␉{ 0x10DE029E, "Quadro FX 1500" },␊
186␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
187␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
188␉{ 0x10DE0302, "GeForce FX 5800" },␊
189␉{ 0x10DE0308, "Quadro FX 2000" },␊
190␉{ 0x10DE0309, "Quadro FX 1000" },␊
191␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
192␉{ 0x10DE0312, "GeForce FX 5600" },␊
193␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
194␉{ 0x10DE031A, "GeForce FX Go5600" },␊
195␉{ 0x10DE031B, "GeForce FX Go5650" },␊
196␉{ 0x10DE031C, "Quadro FX Go700" },␊
197␉{ 0x10DE0324, "GeForce FX Go5200" },␊
198␉{ 0x10DE0325, "GeForce FX Go5250" },␊
199␉{ 0x10DE0326, "GeForce FX 5500" },␊
200␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
201␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
202␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
203␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
204␉{ 0x10DE032D, "GeForce FX Go5100" },␊
205␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
206␉{ 0x10DE0331, "GeForce FX 5900" },␊
207␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
208␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
209␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
210␉{ 0x10DE0338, "Quadro FX 3000" },␊
211␉{ 0x10DE033F, "Quadro FX 700" },␊
212␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
213␉{ 0x10DE0342, "GeForce FX 5700" },␊
214␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
215␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
216␉{ 0x10DE0347, "GeForce FX Go5700" },␊
217␉{ 0x10DE0348, "GeForce FX Go5700" },␊
218␉{ 0x10DE034C, "Quadro FX Go1000" },␊
219␉{ 0x10DE034E, "Quadro FX 1100" },␊
220␉{ 0x10DE0391, "GeForce 7600 GT" },␊
221␉{ 0x10DE0392, "GeForce 7600 GS" },␊
222␉{ 0x10DE0393, "GeForce 7300 GT" },␊
223␉{ 0x10DE0394, "GeForce 7600 LE" },␊
224␉{ 0x10DE0395, "GeForce 7300 GT" },␊
225␉{ 0x10DE0397, "GeForce Go 7700" },␊
226␉{ 0x10DE0398, "GeForce Go 7600" },␊
227␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
228␉{ 0x10DE039A, "Quadro NVS 300M" },␊
229␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
230␉{ 0x10DE039C, "Quadro FX 550M" },␊
231␉{ 0x10DE039E, "Quadro FX 560" },␊
232␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
233␉{ 0x10DE0401, "GeForce 8600 GT" },␊
234␉{ 0x10DE0402, "GeForce 8600 GT" },␊
235␉{ 0x10DE0403, "GeForce 8600 GS" },␊
236␉{ 0x10DE0404, "GeForce 8400 GS" },␊
237␉{ 0x10DE0405, "GeForce 9500M GS" },␊
238␉{ 0x10DE0407, "GeForce 8600M GT" },␊
239␉{ 0x10DE0408, "GeForce 9650M GS" },␊
240␉{ 0x10DE0409, "GeForce 8700M GT" },␊
241␉{ 0x10DE040A, "Quadro FX 370" },␊
242␉{ 0x10DE040B, "Quadro NVS 320M" },␊
243␉{ 0x10DE040C, "Quadro FX 570M" },␊
244␉{ 0x10DE040D, "Quadro FX 1600M" },␊
245␉{ 0x10DE040E, "Quadro FX 570" },␊
246␉{ 0x10DE040F, "Quadro FX 1700" },␊
247␉{ 0x10DE0420, "GeForce 8400 SE" },␊
248␉{ 0x10DE0421, "GeForce 8500 GT" },␊
249␉{ 0x10DE0422, "GeForce 8400 GS" },␊
250␉{ 0x10DE0423, "GeForce 8300 GS" },␊
251␉{ 0x10DE0424, "GeForce 8400 GS" },␊
252␉{ 0x10DE0425, "GeForce 8600M GS" },␊
253␉{ 0x10DE0426, "GeForce 8400M GT" },␊
254␉{ 0x10DE0427, "GeForce 8400M GS" },␊
255␉{ 0x10DE0428, "GeForce 8400M G" },␊
256␉{ 0x10DE0429, "Quadro NVS 140M" },␊
257␉{ 0x10DE042A, "Quadro NVS 130M" },␊
258␉{ 0x10DE042B, "Quadro NVS 135M" },␊
259␉{ 0x10DE042C, "GeForce 9400 GT" },␊
260␉{ 0x10DE042D, "Quadro FX 360M" },␊
261␉{ 0x10DE042E, "GeForce 9300M G" },␊
262␉{ 0x10DE042F, "Quadro NVS 290" },␊
263␉{ 0x10DE05E0, "GeForce GTX 295" },␊
264␉{ 0x10DE05E1, "GeForce GTX 280" },␊
265␉{ 0x10DE05E2, "GeForce GTX 260" },␊
266␉{ 0x10DE05E3, "GeForce GTX 285" },␊
267␉{ 0x10DE05E6, "GeForce GTX 275" },␊
268␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
269␉{ 0x10DE0602, "GeForce 8800 GT" },␊
270␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
271␉{ 0x10DE0605, "GeForce 9800 GT" },␊
272␉{ 0x10DE0606, "GeForce 8800 GS" },␊
273␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
274␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
275␉{ 0x10DE060D, "GeForce 8800 GS" },␊
276␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
277␉{ 0x10DE0611, "GeForce 8800 GT" },␊
278␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
279␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
280␉{ 0x10DE0614, "GeForce 9800 GT" },␊
281␉{ 0x10DE061A, "Quadro FX 3700" },␊
282␉{ 0x10DE061C, "Quadro FX 3600M" },␊
283␉{ 0x10DE0622, "GeForce 9600 GT" },␊
284␉{ 0x10DE0623, "GeForce 9600 GS" },␊
285␉{ 0x10DE0626, "GeForce GT 130" },␊
286␉{ 0x10DE0627, "GeForce GT 140" },␊
287␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
288␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
289␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
290␉{ 0x10DE0640, "GeForce 9500 GT" },␊
291␉{ 0x10DE0641, "GeForce 9400 GT" },␊
292␉{ 0x10DE0642, "GeForce 8400 GS" },␊
293␉{ 0x10DE0643, "GeForce 9500 GT" },␊
294␉{ 0x10DE0644, "GeForce 9500 GS" },␊
295␉{ 0x10DE0645, "GeForce 9500 GS" },␊
296␉{ 0x10DE0646, "GeForce GT 120" },␊
297␉{ 0x10DE0647, "GeForce 9600M GT" },␊
298␉{ 0x10DE0648, "GeForce 9600M GS" },␊
299␉{ 0x10DE0649, "GeForce 9600M GT" },␊
300␉{ 0x10DE064B, "GeForce 9500M G" },␊
301␉{ 0x10DE065B, "GeForce 9400 GT" },␊
302␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
303␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
304␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
305␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
306␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
307␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
308␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
309␉{ 0x10DE0A20, "GeForce GT220" },␊
310␉{ 0x10DE0A60, "GeForce G210" },␊
311␉{ 0x10DE0A65, "GeForce 210" }␊
312};␊
313␊
314static uint16_t swap16(uint16_t x)␊
315{␊
316␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
317}␊
318␊
319static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
320{␊
321␉uint8_t ret[2];␊
322␉ret[0] = ptr[offset+1];␊
323␉ret[1] = ptr[offset];␊
324␉return *((uint16_t*)&ret);␊
325}␊
326␊
327#if 0␊
328static uint32_t swap32(uint32_t x)␊
329{␊
330␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
331}␊
332␊
333static uint8_t read8(uint8_t *ptr, uint16_t offset)␊
334{ ␊
335␉return ptr[offset];␊
336}␊
337␊
338static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
339{␊
340␉uint8_t ret[4];␊
341␉ret[0] = ptr[offset+3];␊
342␉ret[1] = ptr[offset+2];␊
343␉ret[2] = ptr[offset+1];␊
344␉ret[3] = ptr[offset];␊
345␉return *((uint32_t*)&ret);␊
346}␊
347#endif␊
348␊
349static int patch_nvidia_rom(uint8_t *rom)␊
350{␊
351␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
352␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
353␉␉return PATCH_ROM_FAILED;␊
354␉}␊
355␉␊
356␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
357␉if(!dcbptr) {␊
358␉␉printf("no dcb table found\n");␊
359␉␉return PATCH_ROM_FAILED;␊
360␉}/* else␊
361␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊
362␉ */␊
363␉uint8_t *dcbtable = &rom[dcbptr];␊
364␉uint8_t dcbtable_version = dcbtable[0];␊
365␉uint8_t headerlength = 0;␊
366␉uint8_t recordlength = 0;␊
367␉uint8_t numentries = 0;␊
368␉␊
369␉if(dcbtable_version >= 0x20) {␊
370␉␉uint32_t sig;␊
371␉␉␊
372␉␉if(dcbtable_version >= 0x30) {␊
373␉␉␉headerlength = dcbtable[1];␊
374␉␉␉numentries = dcbtable[2];␊
375␉␉␉recordlength = dcbtable[3];␊
376␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
377␉␉} else {␊
378␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
379␉␉␉headerlength = 8;␊
380␉␉}␊
381␉␉if (sig != 0x4edcbdcb) {␊
382␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊
383␉␉␉return PATCH_ROM_FAILED;␊
384␉␉}␊
385␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊
386␉␉char sig[8] = { 0 };␊
387␉␉␊
388␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
389␉␉recordlength = 10;␊
390␉␉if (strcmp(sig, "DEV_REC")) {␊
391␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
392␉␉␉return PATCH_ROM_FAILED;␊
393␉␉}␊
394␉} else {␊
395␉␉return PATCH_ROM_FAILED;␊
396␉}␊
397␉␊
398␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊
399␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
400␉␊
401␉uint8_t num_outputs = 0, i=0;␊
402␉struct dcbentry {␊
403␉␉uint8_t type;␊
404␉␉uint8_t index;␊
405␉␉uint8_t *heads;␊
406␉} entries[numentries];␊
407␉␊
408␉for (i = 0; i < numentries; i++) {␊
409␉␉uint32_t connection;␊
410␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
411␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
412␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
413␉␉␉continue;␊
414␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
415␉␉␉continue;␊
416␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
417␉␉␉continue;␊
418␉␉␊
419␉␉entries[num_outputs].type = connection & 0xf;␊
420␉␉entries[num_outputs].index = num_outputs;␊
421␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
422␊
423␉}␊
424␉␊
425␉int has_lvds = false;␊
426␉uint8_t channel1 = 0, channel2 = 0;␊
427␉␊
428␉for(i=0; i<num_outputs; i++) {␊
429␉␉if(entries[i].type == 3) {␊
430␉␉␉has_lvds = true;␊
431␉␉␉//printf("found LVDS\n");␊
432␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
433␉␉␉entries[i].type = TYPE_GROUPED;␊
434␉␉}␊
435␉}␊
436␉// if we have a LVDS output, we group the rest to the second channel␊
437␉if(has_lvds) {␊
438␉␉for(i=0; i<num_outputs; i++) {␊
439␉␉␉if(entries[i].type == TYPE_GROUPED)␊
440␉␉␉␉continue;␊
441␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
442␉␉␉entries[i].type = TYPE_GROUPED;␊
443␉␉}␊
444␉} else {␊
445␉␉//␊
446␉␉int x;␊
447␉␉// we loop twice as we need to generate two channels␊
448␉␉for(x=0; x<=1; x++) {␊
449␉␉␉for(i=0; i<num_outputs; i++) {␊
450␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊
451␉␉␉␉␉continue;␊
452␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
453␉␉␉␉// we always group ANALOG and TMDS␊
454␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
455␉␉␉␉if(i && entries[i].type == 0x2) {␊
456␉␉␉␉␉switch (x) {␊
457␉␉␉␉␉␉case 0:␊
458␉␉␉␉␉␉␉//printf("group channel 1\n");␊
459␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
460␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
461␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
462␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
463␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
464␉␉␉␉␉␉␉}␊
465␉␉␉␉␉␉␉// group TV as well if there is one␊
466␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
467␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
468␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
469␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
470␉␉␉␉␉␉␉}␊
471␉␉␉␉␉␉␉break;␊
472␉␉␉␉␉␉case 1:␊
473␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
474␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
475␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
476␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
477␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
478␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
479␉␉␉␉␉␉␉}␊
480␉␉␉␉␉␉␉// group TV as well if there is one␊
481␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
482␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
483␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
484␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
485␉␉␉␉␉␉␉}␊
486␉␉␉␉␉␉␉break;␊
487␉␉␉␉␉␉␉␊
488␉␉␉␉␉}␊
489␉␉␉␉␉break;␊
490␉␉␉␉}␊
491␉␉␉}␊
492␉␉}␊
493␉}␊
494␉␊
495␉// if we have left ungrouped outputs merge them to the empty channel␊
496␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
497␉togroup = &channel2;␊
498␉for(i=0; i<num_outputs;i++)␊
499␉␉if(entries[i].type != TYPE_GROUPED) {␊
500␉␉␉//printf("%d not grouped\n", i);␊
501␉␉␉if(togroup)␊
502␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
503␉␉␉entries[i].type = TYPE_GROUPED;␊
504␉␉}␊
505␉␊
506␉if(channel1 > channel2) {␊
507␉␉uint8_t buff = channel1;␊
508␉␉channel1 = channel2;␊
509␉␉channel2 = buff;␊
510␉}␊
511␉␊
512␉default_NVCAP[6] = channel1;␊
513␉default_NVCAP[8] = channel2;␊
514␉␊
515␉// patching HEADS␊
516␉for(i=0; i<num_outputs;i++) {␊
517␉␉if(channel1 & (1 << i))␊
518␉␉␉*entries[i].heads = 1;␊
519␉␉else if(channel2 & (1 << i))␊
520␉␉␉*entries[i].heads = 2;␊
521␉}␊
522␉␊
523␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
524}␊
525␊
526static char *get_nvidia_model(uint32_t id) {␊
527␉int␉i;␊
528␊
529␉for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
530␉␉if (NVKnownChipsets[i].device == id) {␊
531␉␉␉return NVKnownChipsets[i].name;␊
532␉␉}␊
533␉}␊
534␉return NVKnownChipsets[0].name;␊
535}␊
536␊
537static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
538{␊
539␉int␉fd;␊
540␉int␉size;␊
541␊
542␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊
543␉␉return 0;␊
544␉}␊
545␉size = file_size(fd);␊
546␉if (size > bufsize) {␊
547␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊
548␉␉size = bufsize;␊
549␉}␊
550␉size = read(fd, (char *)buf, size);␊
551␉close(fd);␊
552␉return size;␊
553}␊
554␊
555static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
556{␊
557␉char␉tmp[16]; ␊
558␉int␉len;␊
559␊
560␉if(!device)␊
561␉␉return 0;␊
562␊
563␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
564␉␉return 0;␊
565␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
566␉␉return 0;␊
567␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
568␉␉return 0;␊
569␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
570␉␉return 0;␊
571␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
572␉␉return 0;␊
573␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
574␉␉return 0;␊
575␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
576␉␉return 0;␊
577␉len = sprintf(tmp, "Slot-%x", devices_number);␊
578␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *)tmp, len + 1);␊
579␉devices_number++;␊
580␊
581␉return 1;␊
582}␊
583␊
584bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
585{␊
586␉struct DevPropDevice␉␉*device;␊
587␉char␉␉␉␉*devicepath;␊
588␉struct pci_rom_pci_header_t␉*rom_pci_header;␉␊
589␉volatile uint8_t␉␉*regs;␊
590␉uint8_t␉␉␉␉*rom;␊
591␉uint8_t␉␉␉␉*nvRom;␊
592␉uint32_t␉␉␉videoRam;␊
593␉uint32_t␉␉␉nvBiosOveride;␊
594␉uint32_t␉␉␉bar[7];␊
595␉uint32_t␉␉␉boot_display;␊
596␉int␉␉␉␉nvPatch;␊
597␉char␉␉␉␉biosVersion[32];␊
598␉char␉␉␉␉nvFilename[32];␊
599␉char␉␉␉␉*model;␊
600␉bool␉␉␉␉doit;␊
601␊
602␉devicepath = get_pci_dev_path(nvda_dev);␊
603␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
604␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
605␊
606␉// Amount of VRAM in kilobytes␊
607␉videoRam = (REG32(0x10020c) & 0xfff00000) >> 10;␊
608␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
609␊
610␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊
611␉␉model, (videoRam / 1024),␊
612␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
613␉␉devicepath);␊
614␊
615␉rom = MALLOC(NVIDIA_ROM_SIZE);␊
616␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);␊
617␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {␊
618␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
619␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
620␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
621␉} else {␊
622␉␉// Otherwise read bios from card␊
623␉␉nvBiosOveride = 0;␊
624␊
625␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
626␊
627␉␉// PRAMIN first␊
628␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
629␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
630␉␉␊
631␉␉// Valid Signature ?␊
632␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
633␉␉␉// PROM next␊
634␉␉␉// Enable PROM access␊
635␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
636␊
637␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
638␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
639␉␉␉␊
640␉␉␉// disable PROM access␊
641␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊
642␊
643␉␉␉// Valid Signature ?␊
644␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
645␉␉␉␉// 0xC0000 last␊
646␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
647␉␉␉␉␊
648␉␉␉␉// Valid Signature ?␊
649␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
650␉␉␉␉␉verbose("Unable to locate video bios.\n");␊
651␉␉␉␉␉return 0;␊
652␉␉␉␉} else {␊
653␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
654␉␉␉␉}␊
655␉␉␉} else {␊
656␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
657␉␉␉}␊
658␉␉} else {␊
659␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
660␉␉}␊
661␉}␊
662␊
663␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
664␉␉printf("nVidia ROM Patching Failed!\n");␊
665␉␉return false;␊
666␉}␊
667␊
668␉rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
669␊
670␉// check for 'PCIR' sig␊
671␉if (rom_pci_header->signature == 0x50434952) {␊
672␉␉if (rom_pci_header->device != nvda_dev->device_id) {␊
673␉␉␉// Get Model from the OpROM␊
674␉␉␉model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);␊
675␉␉} else {␊
676␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
677␉␉}␊
678␉}␊
679␊
680␉if (!string) {␊
681␉␉string = devprop_create_string();␊
682␉}␊
683␉device = devprop_add_device(string, devicepath);␊
684␊
685␉/* FIXME: for primary graphics card only */␊
686␉boot_display = 1;␊
687␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
688␊
689␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
690␉␉uint8_t built_in = 0x01;␊
691␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
692␉}␊
693␊
694␉videoRam *= 1024;␊
695␉sprintf(biosVersion, "xx.xx.xx - %s", (nvBiosOveride > 0) ? nvFilename : "internal");␊
696␉␊
697␉devprop_add_nvidia_template(device);␊
698␉devprop_add_value(device, "NVCAP", default_NVCAP, 20);␊
699␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
700␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
701␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
702␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {␊
703␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
704␉}␊
705␊
706␉stringdata = MALLOC(sizeof(uint8_t) * string->length);␊
707␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
708␉stringlength = string->length;␊
709␊
710␉return true;␊
711}␊
712

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