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1//********************************************************************␍␊
2// MINIMUM ATA LOW LEVEL I/O DRIVER -- MINDRVR.C␍␊
3//␍␊
4// by Hale Landis (hlandis@ata-atapi.com)␍␊
5//␍␊
6// There is no copyright and there are no restrictions on the use␍␊
7// of this ATA Low Level I/O Driver code. It is distributed to␍␊
8// help other programmers understand how the ATA device interface␍␊
9// works and it is distributed without any warranty. Use this␍␊
10// code at your own risk.␍␊
11//␍␊
12// Minimum ATA Driver (MINDRVR) is a subset of ATADRVR. MINDRVR␍␊
13// has a single header file and a single C file. MINDRVR can␍␊
14// be used as the starting point for an ATADRVR for an embedded␍␊
15// system. NOTE all the places in the MINDRVR.H and MINDRVR.C files␍␊
16// where there is a comment containing the string "!!!".␍␊
17//␍␊
18// Use the header file mindrvr.h in any C files that call MINDRVR␍␊
19// functions.␍␊
20//␍␊
21// This code is based on the ATA/ATAPI-4,-5 and -6 standards and␍␊
22// on interviews with various ATA controller and drive designers.␍␊
23//␍␊
24// Note that MINDRVR does not support ATA CHS addressing.␍␊
25//␍␊
26// Most of the MINDRVR code is standard C code and should compile␍␊
27// using any C compiler. It has been tested using Borland C/C++ 4.5.␍␊
28//␍␊
29// This C source file is the header file for the driver␍␊
30// and is used in the MINDRVR.C files and must also be used␍␊
31// by any program using the MINDRVR code/functions.␍␊
32//********************************************************************␍␊
33␍␊
34// Added boot-132 support by netkas, 2009␍␊
35␍␊
36#include "mindrvr.h"␍␊
37#include "io_inline.h"␍␊
38␍␊
39//**************************************************************␍␊
40//␍␊
41// !!! data that functions outside of MINDRVR must use␍␊
42//␍␊
43// Note that there is no actual "interrupt handler" provide in␍␊
44// MINDRVR. The interrupt handler is usually a small function that␍␊
45// is very system specific. However, MINDRVR expects that interrupt␍␊
46// handler function to provide some status data at the time the␍␊
47// interrupt handler is executed.␍␊
48//␍␊
49// In many systems, including PCI bus based systems, when an␍␊
50// interrupt is received from an ATA controller, the interrupt␍␊
51// handler must acknowledge the interrupt by reading both the␍␊
52// ATA/ATAPI device Status register and the controller status␍␊
53// register. This status must be stored here so that MINDRVR␍␊
54// can use it.␍␊
55//␍␊
56//**************************************************************␍␊
57␍␊
58unsigned char int_ata_status; // ATA status read by interrupt handler␍␊
59␍␊
60unsigned char int_bmide_status; // BMIDE status read by interrupt handler␍␊
61␍␊
62unsigned char int_use_intr_flag = INT_DEFAULT_INTERRUPT_MODE;␍␊
63␍␊
64struct REG_CMD_INFO reg_cmd_info;␍␊
65␍␊
66int reg_config_info[2];␍␊
67␍␊
68unsigned char * pio_bmide_base_addr;␍␊
69␍␊
70unsigned char * pio_reg_addrs[9];␍␊
71/* =␍␊
72{␍␊
73 PIO_BASE_ADDR1 + 0, // [0] CB_DATA␍␊
74 PIO_BASE_ADDR1 + 1, // [1] CB_FR & CB_ER␍␊
75 PIO_BASE_ADDR1 + 2, // [2] CB_SC␍␊
76 PIO_BASE_ADDR1 + 3, // [3] CB_SN␍␊
77 PIO_BASE_ADDR1 + 4, // [4] CB_CL␍␊
78 PIO_BASE_ADDR1 + 5, // [5] CB_CH␍␊
79 PIO_BASE_ADDR1 + 6, // [6] CB_DH␍␊
80 PIO_BASE_ADDR1 + 7, // [7] CB_CMD & CB_STAT␍␊
81 PIO_BASE_ADDR2 + 0 // [8] CB_DC & CB_ASTAT␍␊
82} ;␍␊
83*/␍␊
84unsigned char pio_xfer_width = PIO_DEFAULT_XFER_WIDTH;␍␊
85␍␊
86//**************************************************************␍␊
87//␍␊
88// functions internal and private to MINDRVR␍␊
89//␍␊
90//**************************************************************␍␊
91␍␊
92static void sub_setup_command( void );␍␊
93static void sub_trace_command( void );␍␊
94static int sub_select( unsigned char dev );␍␊
95static void sub_wait_poll( unsigned char we, unsigned char pe );␍␊
96␍␊
97unsigned char pio_inbyte( unsigned char addr );␍␊
98void pio_outbyte( int addr, unsigned char data );␍␊
99static unsigned int pio_inword( unsigned char addr );␍␊
100static void pio_outword( int addr, unsigned int data );␍␊
101static unsigned long pio_indword( unsigned char addr );␍␊
102static void pio_outdword( int addr, unsigned long data );␍␊
103static void pio_drq_block_in( unsigned char addrDataReg,␍␊
104 unsigned char * bufAddr,␍␊
105 long wordCnt );␍␊
106static void pio_drq_block_out( unsigned char addrDataReg,␍␊
107 unsigned char * bufAddr,␍␊
108 long wordCnt );␍␊
109static void pio_rep_inbyte( unsigned char addrDataReg,␍␊
110 unsigned char * bufAddr,␍␊
111 long byteCnt );␍␊
112static void pio_rep_outbyte( unsigned char addrDataReg,␍␊
113 unsigned char * bufAddr,␍␊
114 long byteCnt );␍␊
115static void pio_rep_inword( unsigned char addrDataReg,␍␊
116 unsigned char * bufAddr,␍␊
117 long wordCnt );␍␊
118static void pio_rep_outword( unsigned char addrDataReg,␍␊
119 unsigned char * bufAddr,␍␊
120 long wordCnt );␍␊
121static void pio_rep_indword( unsigned char addrDataReg,␍␊
122 unsigned char * bufAddr,␍␊
123 long dwordCnt );␍␊
124static void pio_rep_outdword( unsigned char addrDataReg,␍␊
125 unsigned char * bufAddr,␍␊
126 long dwordCnt );␍␊
127␍␊
128static unsigned char pio_readBusMstrCmd( void );␍␊
129static unsigned char pio_readBusMstrStatus( void );␍␊
130static void pio_writeBusMstrCmd( unsigned char x );␍␊
131static void pio_writeBusMstrStatus( unsigned char x );␍␊
132␍␊
133static long tmr_cmd_start_time; // command start time␍␊
134static void tmr_set_timeout( void );␍␊
135static int tmr_chk_timeout( void );␍␊
136␍␊
137// This macro provides a small delay that is used in several␍␊
138// places in the ATA command protocols:␍␊
139␍␊
140#define DELAY400NS { pio_inbyte( CB_ASTAT ); pio_inbyte( CB_ASTAT ); \␍␊
141 pio_inbyte( CB_ASTAT ); pio_inbyte( CB_ASTAT ); }␍␊
142␍␊
143␍␊
144void pio_set_iobase_addr( unsigned int base1,␍␊
145 unsigned int base2,␍␊
146 unsigned int base3 )␍␊
147␍␊
148{␍␊
149 pio_bmide_base_addr = base3;␍␊
150 pio_reg_addrs[ CB_DATA ] = (unsigned char *)(base1 + 0); // 0␍␊
151 pio_reg_addrs[ CB_FR ] = (unsigned char *)(base1 + 1); // 1␍␊
152 pio_reg_addrs[ CB_SC ] = (unsigned char *)(base1 + 2); // 2␍␊
153 pio_reg_addrs[ CB_SN ] = (unsigned char *)(base1 + 3); // 3␍␊
154 pio_reg_addrs[ CB_CL ] = (unsigned char *)(base1 + 4); // 4␍␊
155 pio_reg_addrs[ CB_CH ] = (unsigned char *)(base1 + 5); // 5␍␊
156 pio_reg_addrs[ CB_DH ] = (unsigned char *)(base1 + 6); // 6␍␊
157 pio_reg_addrs[ CB_CMD ] = (unsigned char *)(base1 + 7); // 7␍␊
158 pio_reg_addrs[ CB_DC ] = (unsigned char *)(base2 + 2); // 8 //was + 6␍␊
159}␍␊
160␍␊
161//*************************************************************␍␊
162//␍␊
163// reg_config() - Check the host adapter and determine the␍␊
164// number and type of drives attached.␍␊
165//␍␊
166// This process is not documented by any of the ATA standards.␍␊
167//␍␊
168// Infomation is returned by this function is in␍␊
169// reg_config_info[] -- see MINDRVR.H.␍␊
170//␍␊
171//*************************************************************␍␊
172␍␊
173int reg_config( void )␍␊
174␍␊
175{␍␊
176 int numDev = 0;␍␊
177 unsigned char sc;␍␊
178 unsigned char sn;␍␊
179 unsigned char cl;␍␊
180 unsigned char ch;␍␊
181 unsigned char st;␍␊
182 unsigned char dc;␍␊
183␍␊
184 // setup register values␍␊
185␍␊
186 dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
187␍␊
188 // reset Bus Master Error bit␍␊
189␍␊
190 pio_writeBusMstrStatus( BM_SR_MASK_ERR );␍␊
191␍␊
192 // assume there are no devices␍␊
193␍␊
194 reg_config_info[0] = REG_CONFIG_TYPE_NONE;␍␊
195 reg_config_info[1] = REG_CONFIG_TYPE_NONE;␍␊
196␍␊
197 // set up Device Control register␍␊
198␍␊
199 pio_outbyte( CB_DC, dc );␍␊
200␍␊
201 // lets see if there is a device 0␍␊
202␍␊
203 pio_outbyte( CB_DH, CB_DH_DEV0 );␍␊
204 DELAY400NS;␍␊
205 pio_outbyte( CB_SC, 0x55 );␍␊
206 pio_outbyte( CB_SN, 0xaa );␍␊
207 pio_outbyte( CB_SC, 0xaa );␍␊
208 pio_outbyte( CB_SN, 0x55 );␍␊
209 pio_outbyte( CB_SC, 0x55 );␍␊
210 pio_outbyte( CB_SN, 0xaa );␍␊
211 sc = pio_inbyte( CB_SC );␍␊
212 sn = pio_inbyte( CB_SN );␍␊
213 if ( ( sc == 0x55 ) && ( sn == 0xaa ) )␍␊
214 reg_config_info[0] = REG_CONFIG_TYPE_UNKN;␍␊
215␍␊
216 // lets see if there is a device 1␍␊
217␍␊
218 pio_outbyte( CB_DH, CB_DH_DEV1 );␍␊
219 DELAY400NS;␍␊
220 pio_outbyte( CB_SC, 0x55 );␍␊
221 pio_outbyte( CB_SN, 0xaa );␍␊
222 pio_outbyte( CB_SC, 0xaa );␍␊
223 pio_outbyte( CB_SN, 0x55 );␍␊
224 pio_outbyte( CB_SC, 0x55 );␍␊
225 pio_outbyte( CB_SN, 0xaa );␍␊
226 sc = pio_inbyte( CB_SC );␍␊
227 sn = pio_inbyte( CB_SN );␍␊
228 if ( ( sc == 0x55 ) && ( sn == 0xaa ) )␍␊
229 reg_config_info[1] = REG_CONFIG_TYPE_UNKN;␍␊
230␉␍␊
231 // now we think we know which devices, if any are there,␍␊
232 // so lets try a soft reset (ignoring any errors).␍␊
233␍␊
234 pio_outbyte( CB_DH, CB_DH_DEV0 );␍␊
235 DELAY400NS;␍␊
236 reg_reset( 0 );␍␊
237␍␊
238 // lets check device 0 again, is device 0 really there?␍␊
239 // is it ATA or ATAPI?␍␊
240␍␊
241 pio_outbyte( CB_DH, CB_DH_DEV0 );␍␊
242 DELAY400NS;␍␊
243 sc = pio_inbyte( CB_SC );␍␊
244 sn = pio_inbyte( CB_SN );␍␊
245 if ( ( sc == 0x01 ) && ( sn == 0x01 ) )␍␊
246 {␍␊
247 reg_config_info[0] = REG_CONFIG_TYPE_UNKN;␍␊
248 st = pio_inbyte( CB_STAT );␍␊
249 cl = pio_inbyte( CB_CL );␍␊
250 ch = pio_inbyte( CB_CH );␍␊
251 if ( ( ( cl == 0x14 ) && ( ch == 0xeb ) ) // PATAPI␍␊
252 ||␍␊
253 ( ( cl == 0x69 ) && ( ch == 0x96 ) ) // SATAPI␍␊
254 )␍␊
255 {␍␊
256 reg_config_info[0] = REG_CONFIG_TYPE_ATAPI;␍␊
257 }␍␊
258 else␍␊
259 if ( ( st != 0 )␍␊
260 &&␍␊
261 ( ( ( cl == 0x00 ) && ( ch == 0x00 ) ) // PATA␍␊
262 ||␍␊
263 ( ( cl == 0x3c ) && ( ch == 0xc3 ) ) ) // SATA␍␊
264 )␍␊
265 {␍␊
266 reg_config_info[0] = REG_CONFIG_TYPE_ATA;␍␊
267 }␍␊
268 }␍␊
269␍␊
270 // lets check device 1 again, is device 1 really there?␍␊
271 // is it ATA or ATAPI?␍␊
272␍␊
273 pio_outbyte( CB_DH, CB_DH_DEV1 );␍␊
274 DELAY400NS;␍␊
275 sc = pio_inbyte( CB_SC );␍␊
276 sn = pio_inbyte( CB_SN );␍␊
277 if ( ( sc == 0x01 ) && ( sn == 0x01 ) )␍␊
278 {␍␊
279 reg_config_info[1] = REG_CONFIG_TYPE_UNKN;␍␊
280 st = pio_inbyte( CB_STAT );␍␊
281 cl = pio_inbyte( CB_CL );␍␊
282 ch = pio_inbyte( CB_CH );␍␊
283 if ( ( ( cl == 0x14 ) && ( ch == 0xeb ) ) // PATAPI␍␊
284 ||␍␊
285 ( ( cl == 0x69 ) && ( ch == 0x96 ) ) // SATAPI␍␊
286 )␍␊
287 {␍␊
288 reg_config_info[1] = REG_CONFIG_TYPE_ATAPI;␍␊
289 }␍␊
290 else␍␊
291 if ( ( st != 0 )␍␊
292 &&␍␊
293 ( ( ( cl == 0x00 ) && ( ch == 0x00 ) ) // PATA␍␊
294 ||␍␊
295 ( ( cl == 0x3c ) && ( ch == 0xc3 ) ) ) // SATA␍␊
296 )␍␊
297 {␍␊
298 reg_config_info[1] = REG_CONFIG_TYPE_ATA;␍␊
299 }␍␊
300 }␍␊
301␍␊
302 // If possible, select a device that exists, try device 0 first.␍␊
303␍␊
304 if ( reg_config_info[1] != REG_CONFIG_TYPE_NONE )␍␊
305 {␍␊
306 pio_outbyte( CB_DH, CB_DH_DEV1 );␍␊
307 DELAY400NS;␍␊
308 numDev ++ ;␍␊
309 }␍␊
310 if ( reg_config_info[0] != REG_CONFIG_TYPE_NONE )␍␊
311 {␍␊
312 pio_outbyte( CB_DH, CB_DH_DEV0 );␍␊
313 DELAY400NS;␍␊
314 numDev ++ ;␍␊
315 }␍␊
316␍␊
317 // BMIDE Error=1?␍␊
318␍␊
319 if ( pio_readBusMstrStatus() & BM_SR_MASK_ERR )␍␊
320 {␍␊
321 reg_cmd_info.ec = 78; // yes␍␊
322 }␍␊
323␍␊
324 // return the number of devices found␍␊
325␍␊
326 return numDev;␍␊
327}␍␊
328␍␊
329//*************************************************************␍␊
330//␍␊
331// reg_reset() - Execute a Software Reset.␍␊
332//␍␊
333// See ATA-2 Section 9.2, ATA-3 Section 9.2, ATA-4 Section 8.3.␍␊
334//␍␊
335//*************************************************************␍␊
336␍␊
337int reg_reset( unsigned char devRtrn )␍␊
338␍␊
339{␍␊
340 unsigned char sc;␍␊
341 unsigned char sn;␍␊
342 unsigned char status;␍␊
343 unsigned char dc;␍␊
344␍␊
345 // setup register values␍␊
346␍␊
347 dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
348␍␊
349 // reset Bus Master Error bit␍␊
350␍␊
351 pio_writeBusMstrStatus( BM_SR_MASK_ERR );␍␊
352␍␊
353 // initialize the command timeout counter␍␊
354␍␊
355 tmr_set_timeout();␍␊
356␍␊
357 // Set and then reset the soft reset bit in the Device Control␍␊
358 // register. This causes device 0 be selected.␍␊
359␍␊
360 pio_outbyte( CB_DC, (unsigned char) ( dc | CB_DC_SRST ) );␍␊
361 DELAY400NS;␍␊
362 pio_outbyte( CB_DC, dc );␍␊
363 DELAY400NS;␍␊
364␍␊
365 // If there is a device 0, wait for device 0 to set BSY=0.␍␊
366␍␊
367 if ( reg_config_info[0] != REG_CONFIG_TYPE_NONE )␍␊
368 {␍␊
369 while ( 1 )␍␊
370 {␍␊
371 status = pio_inbyte( CB_STAT );␍␊
372 if ( ( status & CB_STAT_BSY ) == 0 )␍␊
373 break;␍␊
374 if ( tmr_chk_timeout() )␍␊
375 {␍␊
376 reg_cmd_info.to = 1;␍␊
377 reg_cmd_info.ec = 1;␍␊
378 break;␍␊
379 }␍␊
380 }␍␊
381 }␍␊
382␍␊
383 // If there is a device 1, wait until device 1 allows␍␊
384 // register access.␍␊
385␍␊
386 if ( reg_config_info[1] != REG_CONFIG_TYPE_NONE )␍␊
387 {␍␊
388 while ( 1 )␍␊
389 {␍␊
390 pio_outbyte( CB_DH, CB_DH_DEV1 );␍␊
391 DELAY400NS;␍␊
392 sc = pio_inbyte( CB_SC );␍␊
393 sn = pio_inbyte( CB_SN );␍␊
394 if ( ( sc == 0x01 ) && ( sn == 0x01 ) )␍␊
395 break;␍␊
396 if ( tmr_chk_timeout() )␍␊
397 {␍␊
398 reg_cmd_info.to = 1;␍␊
399 reg_cmd_info.ec = 2;␍␊
400 break;␍␊
401 }␍␊
402 }␍␊
403␍␊
404 // Now check if drive 1 set BSY=0.␍␊
405␍␊
406 if ( reg_cmd_info.ec == 0 )␍␊
407 {␍␊
408 if ( pio_inbyte( CB_STAT ) & CB_STAT_BSY )␍␊
409 {␍␊
410 reg_cmd_info.ec = 3;␍␊
411 }␍␊
412 }␍␊
413 }␍␊
414␍␊
415 // RESET_DONE:␍␊
416␍␊
417 // We are done but now we must select the device the caller␍␊
418 // requested. This will cause␍␊
419 // the correct data to be returned in reg_cmd_info.␍␊
420␍␊
421 pio_outbyte( CB_DH, (unsigned char) ( devRtrn ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
422 DELAY400NS;␍␊
423␍␊
424 // If possible, select a device that exists,␍␊
425 // try device 0 first.␍␊
426␍␊
427 if ( reg_config_info[1] != REG_CONFIG_TYPE_NONE )␍␊
428 {␍␊
429 pio_outbyte( CB_DH, CB_DH_DEV1 );␍␊
430 DELAY400NS;␍␊
431 }␍␊
432 if ( reg_config_info[0] != REG_CONFIG_TYPE_NONE )␍␊
433 {␍␊
434 pio_outbyte( CB_DH, CB_DH_DEV0 );␍␊
435 DELAY400NS;␍␊
436 }␍␊
437␍␊
438 // BMIDE Error=1?␍␊
439␍␊
440 if ( pio_readBusMstrStatus() & BM_SR_MASK_ERR )␍␊
441 {␍␊
442 reg_cmd_info.ec = 78; // yes␍␊
443 }␍␊
444␍␊
445 // All done. The return values of this function are described in␍␊
446 // MINDRVR.H.␍␊
447␍␊
448 sub_trace_command();␍␊
449 if ( reg_cmd_info.ec )␍␊
450 return 1;␍␊
451 return 0;␍␊
452}␍␊
453␍␊
454//*************************************************************␍␊
455//␍␊
456// exec_non_data_cmd() - Execute a non-data command.␍␊
457//␍␊
458// This includes the strange ATAPI DEVICE RESET 'command'␍␊
459// (command code 08H).␍␊
460//␍␊
461// Note special handling for Execute Device Diagnostics␍␊
462// command when there is no device 0.␍␊
463//␍␊
464// See ATA-2 Section 9.5, ATA-3 Section 9.5,␍␊
465// ATA-4 Section 8.8 Figure 12. Also see Section 8.5.␍␊
466//␍␊
467//*************************************************************␍␊
468␍␊
469static int exec_non_data_cmd( unsigned char dev );␍␊
470␍␊
471static int exec_non_data_cmd( unsigned char dev )␍␊
472␍␊
473{␍␊
474 unsigned char secCnt;␍␊
475 unsigned char secNum;␍␊
476 unsigned char status;␍␊
477 int polled = 0;␍␊
478␍␊
479 // reset Bus Master Error bit␍␊
480␍␊
481 pio_writeBusMstrStatus( BM_SR_MASK_ERR );␍␊
482␍␊
483 // Set command time out.␍␊
484␍␊
485 tmr_set_timeout();␍␊
486␍␊
487 // PAY ATTENTION HERE␍␊
488 // If the caller is attempting a Device Reset command, then␍␊
489 // don't do most of the normal stuff. Device Reset has no␍␊
490 // parameters, should not generate an interrupt and it is the␍␊
491 // only command that can be written to the Command register␍␊
492 // when a device has BSY=1 (a very strange command!). Not␍␊
493 // all devices support this command (even some ATAPI devices␍␊
494 // don't support the command.␍␊
495␍␊
496 if ( reg_cmd_info.cmd != CMD_DEVICE_RESET )␍␊
497 {␍␊
498 // Select the drive - call the sub_select function.␍␊
499 // Quit now if this fails.␍␊
500␍␊
501 if ( sub_select( dev ) )␍␊
502 {␍␊
503 return 1;␍␊
504 }␍␊
505␍␊
506 // Set up all the registers except the command register.␍␊
507␍␊
508 sub_setup_command();␍␊
509 }␍␊
510␍␊
511 // Start the command by setting the Command register. The drive␍␊
512 // should immediately set BUSY status.␍␊
513␍␊
514 pio_outbyte( CB_CMD, reg_cmd_info.cmd );␍␊
515␍␊
516 // Waste some time by reading the alternate status a few times.␍␊
517 // This gives the drive time to set BUSY in the status register on␍␊
518 // really fast systems. If we don't do this, a slow drive on a fast␍␊
519 // system may not set BUSY fast enough and we would think it had␍␊
520 // completed the command when it really had not even started the␍␊
521 // command yet.␍␊
522␍␊
523 DELAY400NS;␍␊
524␍␊
525 // IF␍␊
526 // This is an Exec Dev Diag command (cmd=0x90)␍␊
527 // and there is no device 0 then␍␊
528 // there will be no interrupt. So we must␍␊
529 // poll device 1 until it allows register␍␊
530 // access and then do normal polling of the Status␍␊
531 // register for BSY=0.␍␊
532 // ELSE␍␊
533 // IF␍␊
534 // This is a Dev Reset command (cmd=0x08) then␍␊
535 // there should be no interrupt. So we must␍␊
536 // poll for BSY=0.␍␊
537 // ELSE␍␊
538 // Do the normal wait for interrupt or polling for␍␊
539 // completion.␍␊
540␍␊
541 if ( ( reg_cmd_info.cmd == CMD_EXECUTE_DEVICE_DIAGNOSTIC )␍␊
542 &&␍␊
543 ( reg_config_info[0] == REG_CONFIG_TYPE_NONE )␍␊
544 )␍␊
545 {␍␊
546 polled = 1;␍␊
547 while ( 1 )␍␊
548 {␍␊
549 pio_outbyte( CB_DH, CB_DH_DEV1 );␍␊
550 DELAY400NS;␍␊
551 secCnt = pio_inbyte( CB_SC );␍␊
552 secNum = pio_inbyte( CB_SN );␍␊
553 if ( ( secCnt == 0x01 ) && ( secNum == 0x01 ) )␍␊
554 break;␍␊
555 if ( tmr_chk_timeout() )␍␊
556 {␍␊
557 reg_cmd_info.to = 1;␍␊
558 reg_cmd_info.ec = 24;␍␊
559 break;␍␊
560 }␍␊
561 }␍␊
562 }␍␊
563 else␍␊
564 {␍␊
565 if ( reg_cmd_info.cmd == CMD_DEVICE_RESET )␍␊
566 {␍␊
567 // Wait for not BUSY -or- wait for time out.␍␊
568␍␊
569 polled = 1;␍␊
570 sub_wait_poll( 0, 23 );␍␊
571 }␍␊
572 else␍␊
573 {␍␊
574 // Wait for interrupt -or- wait for not BUSY -or- wait for time out.␍␊
575␍␊
576 if ( ! int_use_intr_flag )␍␊
577 polled = 1;␍␊
578 sub_wait_poll( 22, 23 );␍␊
579 }␍␊
580 }␍␊
581␍␊
582 // If status was polled or if any error read the status register,␍␊
583 // otherwise get the status that was read by the interrupt handler.␍␊
584␍␊
585 if ( ( polled ) || ( reg_cmd_info.ec ) )␍␊
586 status = pio_inbyte( CB_STAT );␍␊
587 else␍␊
588 status = int_ata_status;␍␊
589␍␊
590 // Error if BUSY, DEVICE FAULT, DRQ or ERROR status now.␍␊
591␍␊
592 if ( reg_cmd_info.ec == 0 )␍␊
593 {␍␊
594 if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
595 {␍␊
596 reg_cmd_info.ec = 21;␍␊
597 }␍␊
598 }␍␊
599␍␊
600 // BMIDE Error=1?␍␊
601␍␊
602 if ( pio_readBusMstrStatus() & BM_SR_MASK_ERR )␍␊
603 {␍␊
604 reg_cmd_info.ec = 78; // yes␍␊
605 }␍␊
606␍␊
607 // NON_DATA_DONE:␍␊
608␍␊
609 // All done. The return values of this function are described in␍␊
610 // MINDRVR.H.␍␊
611␍␊
612 sub_trace_command();␍␊
613 if ( reg_cmd_info.ec )␍␊
614 return 1;␍␊
615 return 0;␍␊
616}␍␊
617␍␊
618//*************************************************************␍␊
619//␍␊
620// reg_non_data_lba28() - Easy way to execute a non-data command␍␊
621// using an LBA sector address.␍␊
622//␍␊
623//*************************************************************␍␊
624␍␊
625int reg_non_data_lba28( unsigned char dev, unsigned char cmd,␍␊
626 unsigned int fr, unsigned int sc,␍␊
627 unsigned long lba )␍␊
628␍␊
629{␍␊
630␍␊
631 // Setup current command information.␍␊
632␍␊
633 reg_cmd_info.cmd = cmd;␍␊
634 reg_cmd_info.fr = fr;␍␊
635 reg_cmd_info.sc = sc;␍␊
636 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
637 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
638 reg_cmd_info.ns = sc;␍␊
639 reg_cmd_info.lbaSize = LBA28;␍␊
640 reg_cmd_info.lbaHigh = 0L;␍␊
641 reg_cmd_info.lbaLow = lba;␍␊
642␍␊
643 // Execute the command.␍␊
644␍␊
645 return exec_non_data_cmd( dev );␍␊
646}␍␊
647␍␊
648//*************************************************************␍␊
649//␍␊
650// reg_non_data_lba48() - Easy way to execute a non-data command␍␊
651// using an LBA sector address.␍␊
652//␍␊
653//*************************************************************␍␊
654␍␊
655int reg_non_data_lba48( unsigned char dev, unsigned char cmd,␍␊
656 unsigned int fr, unsigned int sc,␍␊
657 unsigned long lbahi, unsigned long lbalo )␍␊
658␍␊
659{␍␊
660␍␊
661 // Setup current command infomation.␍␊
662␍␊
663 reg_cmd_info.cmd = cmd;␍␊
664 reg_cmd_info.fr = fr;␍␊
665 reg_cmd_info.sc = sc;␍␊
666 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
667 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
668 reg_cmd_info.ns = sc;␍␊
669 reg_cmd_info.lbaSize = LBA48;␍␊
670 reg_cmd_info.lbaHigh = lbahi;␍␊
671 reg_cmd_info.lbaLow = lbalo;␍␊
672␍␊
673 // Execute the command.␍␊
674␍␊
675 return exec_non_data_cmd( dev );␍␊
676}␍␊
677␍␊
678//*************************************************************␍␊
679//␍␊
680// exec_pio_data_in_cmd() - Execute a PIO Data In command.␍␊
681//␍␊
682// See ATA-2 Section 9.3, ATA-3 Section 9.3,␍␊
683// ATA-4 Section 8.6 Figure 10.␍␊
684//␍␊
685//*************************************************************␍␊
686␍␊
687static int exec_pio_data_in_cmd( unsigned char dev,␍␊
688 unsigned char * bufAddr,␍␊
689 long numSect, int multiCnt );␍␊
690␍␊
691␍␊
692static int exec_pio_data_in_cmd( unsigned char dev,␍␊
693 unsigned char * bufAddr,␍␊
694 long numSect, int multiCnt )␍␊
695␍␊
696{␍␊
697 unsigned char status;␍␊
698 long wordCnt;␍␊
699␍␊
700 // reset Bus Master Error bit␍␊
701␍␊
702 pio_writeBusMstrStatus( BM_SR_MASK_ERR );␍␊
703␍␊
704 // Set command time out.␍␊
705␍␊
706 tmr_set_timeout();␍␊
707␍␊
708 // Select the drive - call the sub_select function.␍␊
709 // Quit now if this fails.␍␊
710␍␊
711 if ( sub_select( dev ) )␍␊
712 {␍␊
713 return 1;␍␊
714 }␍␊
715␍␊
716 // Set up all the registers except the command register.␍␊
717␍␊
718 sub_setup_command();␍␊
719␍␊
720 // Start the command by setting the Command register. The drive␍␊
721 // should immediately set BUSY status.␍␊
722␍␊
723 pio_outbyte( CB_CMD, reg_cmd_info.cmd );␍␊
724␍␊
725 // Waste some time by reading the alternate status a few times.␍␊
726 // This gives the drive time to set BUSY in the status register on␍␊
727 // really fast systems. If we don't do this, a slow drive on a fast␍␊
728 // system may not set BUSY fast enough and we would think it had␍␊
729 // completed the command when it really had not even started the␍␊
730 // command yet.␍␊
731␍␊
732 DELAY400NS;␍␊
733␍␊
734 // Loop to read each sector.␍␊
735␍␊
736 while ( 1 )␍␊
737 {␍␊
738 // READ_LOOP:␍␊
739 //␍␊
740 // NOTE NOTE NOTE ... The primary status register (1f7) MUST NOT be␍␊
741 // read more than ONCE for each sector transferred! When the␍␊
742 // primary status register is read, the drive resets IRQ. The␍␊
743 // alternate status register (3f6) can be read any number of times.␍␊
744 // After interrupt read the the primary status register ONCE␍␊
745 // and transfer the 256 words (REP INSW). AS SOON as BOTH the␍␊
746 // primary status register has been read AND the last of the 256␍␊
747 // words has been read, the drive is allowed to generate the next␍␊
748 // IRQ (newer and faster drives could generate the next IRQ in␍␊
749 // 50 microseconds or less). If the primary status register is read␍␊
750 // more than once, there is the possibility of a race between the␍␊
751 // drive and the software and the next IRQ could be reset before␍␊
752 // the system interrupt controller sees it.␍␊
753␍␊
754 // Wait for interrupt -or- wait for not BUSY -or- wait for time out.␍␊
755␍␊
756 sub_wait_poll( 34, 35 );␍␊
757␍␊
758 // If polling or error read the status, otherwise␍␊
759 // get the status that was read by the interrupt handler.␍␊
760␍␊
761 if ( ( ! int_use_intr_flag ) || ( reg_cmd_info.ec ) )␍␊
762 status = pio_inbyte( CB_STAT );␍␊
763 else␍␊
764 status = int_ata_status;␍␊
765␍␊
766 // If there was a time out error, go to READ_DONE.␍␊
767␍␊
768 if ( reg_cmd_info.ec )␍␊
769 break; // go to READ_DONE␍␊
770␍␊
771 // If BSY=0 and DRQ=1, transfer the data,␍␊
772 // even if we find out there is an error later.␍␊
773␍␊
774 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) == CB_STAT_DRQ )␍␊
775 {␍␊
776␍␊
777 // increment number of DRQ packets␍␊
778␍␊
779 reg_cmd_info.drqPackets ++ ;␍␊
780␍␊
781 // determine the number of sectors to transfer␍␊
782␍␊
783 wordCnt = multiCnt ? multiCnt : 1;␍␊
784 if ( wordCnt > numSect )␍␊
785 wordCnt = numSect;␍␊
786 wordCnt = wordCnt * 256;␍␊
787␍␊
788 // Do the REP INSW to read the data for one DRQ block.␍␊
789␍␊
790 reg_cmd_info.totalBytesXfer += ( wordCnt << 1 );␍␊
791 pio_drq_block_in( CB_DATA, bufAddr, wordCnt );␍␊
792␍␊
793 DELAY400NS; // delay so device can get the status updated␍␊
794␍␊
795 // Note: The drive should have dropped DATA REQUEST by now. If there␍␊
796 // are more sectors to transfer, BUSY should be active now (unless␍␊
797 // there is an error).␍␊
798␍␊
799 // Decrement the count of sectors to be transferred␍␊
800 // and increment buffer address.␍␊
801␍␊
802 numSect = numSect - ( multiCnt ? multiCnt : 1 );␍␊
803 bufAddr = bufAddr + ( 512 * ( multiCnt ? multiCnt : 1 ) );␍␊
804 }␍␊
805␍␊
806 // So was there any error condition?␍␊
807␍␊
808 if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_ERR ) )␍␊
809 {␍␊
810 reg_cmd_info.ec = 31;␍␊
811 break; // go to READ_DONE␍␊
812 }␍␊
813␍␊
814 // DRQ should have been set -- was it?␍␊
815␍␊
816 if ( ( status & CB_STAT_DRQ ) == 0 )␍␊
817 {␍␊
818 reg_cmd_info.ec = 32;␍␊
819 break; // go to READ_DONE␍␊
820 }␍␊
821␍␊
822 // If all of the requested sectors have been transferred, make a␍␊
823 // few more checks before we exit.␍␊
824␍␊
825 if ( numSect < 1 )␍␊
826 {␍␊
827 // Since the drive has transferred all of the requested sectors␍␊
828 // without error, the drive should not have BUSY, DEVICE FAULT,␍␊
829 // DATA REQUEST or ERROR active now.␍␊
830␍␊
831 status = pio_inbyte( CB_STAT );␍␊
832 if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
833 {␍␊
834 reg_cmd_info.ec = 33;␍␊
835 break; // go to READ_DONE␍␊
836 }␍␊
837␍␊
838 // All sectors have been read without error, go to READ_DONE.␍␊
839␍␊
840 break; // go to READ_DONE␍␊
841␍␊
842 }␍␊
843␍␊
844 // This is the end of the read loop. If we get here, the loop is␍␊
845 // repeated to read the next sector. Go back to READ_LOOP.␍␊
846␍␊
847 }␍␊
848␍␊
849 // BMIDE Error=1?␍␊
850␍␊
851 if ( pio_readBusMstrStatus() & BM_SR_MASK_ERR )␍␊
852 {␍␊
853 reg_cmd_info.ec = 78; // yes␍␊
854 }␍␊
855␍␊
856 // READ_DONE:␍␊
857␍␊
858 // All done. The return values of this function are described in␍␊
859 // MINDRVR.H.␍␊
860␍␊
861 if ( reg_cmd_info.ec )␍␊
862 return 1;␍␊
863 return 0;␍␊
864}␍␊
865␍␊
866//*************************************************************␍␊
867//␍␊
868// reg_pio_data_in_lba28() - Easy way to execute a PIO Data In command␍␊
869// using an LBA sector address.␍␊
870//␍␊
871//*************************************************************␍␊
872␍␊
873int reg_pio_data_in_lba28( unsigned char dev, unsigned char cmd,␍␊
874 unsigned int fr, unsigned int sc,␍␊
875 unsigned long lba,␍␊
876 unsigned char * bufAddr,␍␊
877 long numSect, int multiCnt )␍␊
878␍␊
879{␍␊
880␍␊
881 reg_cmd_info.cmd = cmd;␍␊
882 reg_cmd_info.fr = fr;␍␊
883 reg_cmd_info.sc = sc;␍␊
884 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
885 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
886 reg_cmd_info.lbaSize = LBA28;␍␊
887 reg_cmd_info.lbaHigh = 0L;␍␊
888 reg_cmd_info.lbaLow = lba;␍␊
889␍␊
890 // these commands transfer only 1 sector␍␊
891 if ( ( cmd == CMD_IDENTIFY_DEVICE )␍␊
892 || ( cmd == CMD_IDENTIFY_DEVICE_PACKET )␍␊
893 )␍␊
894 numSect = 1;␍␊
895␍␊
896 // adjust multiple count␍␊
897 if ( multiCnt & 0x0800 )␍␊
898 {␍␊
899 // assume caller knows what they are doing␍␊
900 multiCnt &= 0x00ff;␍␊
901 }␍␊
902 else␍␊
903 {␍␊
904 // only Read Multiple uses multiCnt␍␊
905 if ( cmd != CMD_READ_MULTIPLE )␍␊
906 multiCnt = 1;␍␊
907 }␍␊
908␍␊
909 reg_cmd_info.ns = numSect;␍␊
910 reg_cmd_info.mc = multiCnt;␍␊
911␍␊
912 return exec_pio_data_in_cmd( dev, bufAddr, numSect, multiCnt );␍␊
913}␍␊
914␍␊
915//*************************************************************␍␊
916//␍␊
917// reg_pio_data_in_lba48() - Easy way to execute a PIO Data In command␍␊
918// using an LBA sector address.␍␊
919//␍␊
920//*************************************************************␍␊
921␍␊
922int reg_pio_data_in_lba48( unsigned char dev, unsigned char cmd,␍␊
923 unsigned int fr, unsigned int sc,␍␊
924 unsigned long lbahi, unsigned long lbalo,␍␊
925 unsigned char * bufAddr,␍␊
926 long numSect, int multiCnt )␍␊
927␍␊
928{␍␊
929␍␊
930 reg_cmd_info.cmd = cmd;␍␊
931 reg_cmd_info.fr = fr;␍␊
932 reg_cmd_info.sc = sc;␍␊
933 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
934 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
935 reg_cmd_info.lbaSize = LBA48;␍␊
936 reg_cmd_info.lbaHigh = lbahi;␍␊
937 reg_cmd_info.lbaLow = lbalo;␍␊
938␍␊
939 // adjust multiple count␍␊
940 if ( multiCnt & 0x0800 )␍␊
941 {␍␊
942 // assume caller knows what they are doing␍␊
943 multiCnt &= 0x00ff;␍␊
944 }␍␊
945 else␍␊
946 {␍␊
947 // only Read Multiple Ext uses multiCnt␍␊
948 if ( cmd != CMD_READ_MULTIPLE_EXT )␍␊
949 multiCnt = 1;␍␊
950 }␍␊
951␍␊
952 reg_cmd_info.ns = numSect;␍␊
953 reg_cmd_info.mc = multiCnt;␍␊
954␍␊
955 return exec_pio_data_in_cmd( dev, bufAddr, numSect, multiCnt );␍␊
956}␍␊
957␍␊
958//*************************************************************␍␊
959//␍␊
960// exec_pio_data_out_cmd() - Execute a PIO Data Out command.␍␊
961//␍␊
962// See ATA-2 Section 9.4, ATA-3 Section 9.4,␍␊
963// ATA-4 Section 8.7 Figure 11.␍␊
964//␍␊
965//*************************************************************␍␊
966␍␊
967static int exec_pio_data_out_cmd( unsigned char dev,␍␊
968 unsigned char * bufAddr,␍␊
969 long numSect, int multiCnt );␍␊
970␍␊
971static int exec_pio_data_out_cmd( unsigned char dev,␍␊
972 unsigned char * bufAddr,␍␊
973 long numSect, int multiCnt )␍␊
974␍␊
975{␍␊
976 unsigned char status;␍␊
977 int loopFlag = 1;␍␊
978 long wordCnt;␍␊
979␍␊
980 // reset Bus Master Error bit␍␊
981␍␊
982 pio_writeBusMstrStatus( BM_SR_MASK_ERR );␍␊
983␍␊
984 // Set command time out.␍␊
985␍␊
986 tmr_set_timeout();␍␊
987␍␊
988 // Select the drive - call the sub_select function.␍␊
989 // Quit now if this fails.␍␊
990␍␊
991 if ( sub_select( dev ) )␍␊
992 {␍␊
993 return 1;␍␊
994 }␍␊
995␍␊
996 // Set up all the registers except the command register.␍␊
997␍␊
998 sub_setup_command();␍␊
999␍␊
1000 // Start the command by setting the Command register. The drive␍␊
1001 // should immediately set BUSY status.␍␊
1002␍␊
1003 pio_outbyte( CB_CMD, reg_cmd_info.cmd );␍␊
1004␍␊
1005 // Waste some time by reading the alternate status a few times.␍␊
1006 // This gives the drive time to set BUSY in the status register on␍␊
1007 // really fast systems. If we don't do this, a slow drive on a fast␍␊
1008 // system may not set BUSY fast enough and we would think it had␍␊
1009 // completed the command when it really had not even started the␍␊
1010 // command yet.␍␊
1011␍␊
1012 DELAY400NS;␍␊
1013␍␊
1014 // Wait for not BUSY or time out.␍␊
1015 // Note: No interrupt is generated for the␍␊
1016 // first sector of a write command.␍␊
1017␍␊
1018 while ( 1 )␍␊
1019 {␍␊
1020 status = pio_inbyte( CB_ASTAT );␍␊
1021 if ( ( status & CB_STAT_BSY ) == 0 )␍␊
1022 break;␍␊
1023 if ( tmr_chk_timeout() )␍␊
1024 {␍␊
1025 reg_cmd_info.to = 1;␍␊
1026 reg_cmd_info.ec = 47;␍␊
1027 loopFlag = 0;␍␊
1028 break;␍␊
1029 }␍␊
1030 }␍␊
1031␍␊
1032 // This loop writes each sector.␍␊
1033␍␊
1034 while ( loopFlag )␍␊
1035 {␍␊
1036 // WRITE_LOOP:␍␊
1037 //␍␊
1038 // NOTE NOTE NOTE ... The primary status register (1f7) MUST NOT be␍␊
1039 // read more than ONCE for each sector transferred! When the␍␊
1040 // primary status register is read, the drive resets IRQ. The␍␊
1041 // alternate status register (3f6) can be read any number of times.␍␊
1042 // For correct results, transfer the 256 words (REP OUTSW), wait for␍␊
1043 // interrupt and then read the primary status register. AS␍␊
1044 // SOON as BOTH the primary status register has been read AND the␍␊
1045 // last of the 256 words has been written, the drive is allowed to␍␊
1046 // generate the next IRQ (newer and faster drives could generate␍␊
1047 // the next IRQ in 50 microseconds or less). If the primary␍␊
1048 // status register is read more than once, there is the possibility␍␊
1049 // of a race between the drive and the software and the next IRQ␍␊
1050 // could be reset before the system interrupt controller sees it.␍␊
1051␍␊
1052 // If BSY=0 and DRQ=1, transfer the data,␍␊
1053 // even if we find out there is an error later.␍␊
1054␍␊
1055 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) == CB_STAT_DRQ )␍␊
1056 {␍␊
1057␍␊
1058 // increment number of DRQ packets␍␊
1059␍␊
1060 reg_cmd_info.drqPackets ++ ;␍␊
1061␍␊
1062 // determine the number of sectors to transfer␍␊
1063␍␊
1064 wordCnt = multiCnt ? multiCnt : 1;␍␊
1065 if ( wordCnt > numSect )␍␊
1066 wordCnt = numSect;␍␊
1067 wordCnt = wordCnt * 256;␍␊
1068␍␊
1069 // Do the REP OUTSW to write the data for one DRQ block.␍␊
1070␍␊
1071 reg_cmd_info.totalBytesXfer += ( wordCnt << 1 );␍␊
1072 pio_drq_block_out( CB_DATA, bufAddr, wordCnt );␍␊
1073␍␊
1074 DELAY400NS; // delay so device can get the status updated␍␊
1075␍␊
1076 // Note: The drive should have dropped DATA REQUEST and␍␊
1077 // raised BUSY by now.␍␊
1078␍␊
1079 // Decrement the count of sectors to be transferred␍␊
1080 // and increment buffer address.␍␊
1081␍␊
1082 numSect = numSect - ( multiCnt ? multiCnt : 1 );␍␊
1083 bufAddr = bufAddr + ( 512 * ( multiCnt ? multiCnt : 1 ) );␍␊
1084 }␍␊
1085␍␊
1086 // So was there any error condition?␍␊
1087␍␊
1088 if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_ERR ) )␍␊
1089 {␍␊
1090 reg_cmd_info.ec = 41;␍␊
1091 break; // go to WRITE_DONE␍␊
1092 }␍␊
1093␍␊
1094 // DRQ should have been set -- was it?␍␊
1095␍␊
1096 if ( ( status & CB_STAT_DRQ ) == 0 )␍␊
1097 {␍␊
1098 reg_cmd_info.ec = 42;␍␊
1099 break; // go to WRITE_DONE␍␊
1100 }␍␊
1101␍␊
1102 // Wait for interrupt -or- wait for not BUSY -or- wait for time out.␍␊
1103␍␊
1104 sub_wait_poll( 44, 45 );␍␊
1105␍␊
1106 // If polling or error read the status, otherwise␍␊
1107 // get the status that was read by the interrupt handler.␍␊
1108␍␊
1109 if ( ( ! int_use_intr_flag ) || ( reg_cmd_info.ec ) )␍␊
1110 status = pio_inbyte( CB_STAT );␍␊
1111 else␍␊
1112 status = int_ata_status;␍␊
1113␍␊
1114 // If there was a time out error, go to WRITE_DONE.␍␊
1115␍␊
1116 if ( reg_cmd_info.ec )␍␊
1117 break; // go to WRITE_DONE␍␊
1118␍␊
1119 // If all of the requested sectors have been transferred, make a␍␊
1120 // few more checks before we exit.␍␊
1121␍␊
1122 if ( numSect < 1 )␍␊
1123 {␍␊
1124 // Since the drive has transferred all of the sectors without␍␊
1125 // error, the drive MUST not have BUSY, DEVICE FAULT, DATA REQUEST␍␊
1126 // or ERROR status at this time.␍␊
1127␍␊
1128 if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
1129 {␍␊
1130 reg_cmd_info.ec = 43;␍␊
1131 break; // go to WRITE_DONE␍␊
1132 }␍␊
1133␍␊
1134 // All sectors have been written without error, go to WRITE_DONE.␍␊
1135␍␊
1136 break; // go to WRITE_DONE␍␊
1137␍␊
1138 }␍␊
1139␍␊
1140 //␍␊
1141 // This is the end of the write loop. If we get here, the loop␍␊
1142 // is repeated to write the next sector. Go back to WRITE_LOOP.␍␊
1143␍␊
1144 }␍␊
1145␍␊
1146 // BMIDE Error=1?␍␊
1147␍␊
1148 if ( pio_readBusMstrStatus() & BM_SR_MASK_ERR )␍␊
1149 {␍␊
1150 reg_cmd_info.ec = 78; // yes␍␊
1151 }␍␊
1152␍␊
1153 // WRITE_DONE:␍␊
1154␍␊
1155 // All done. The return values of this function are described in␍␊
1156 // MINDRVR.H.␍␊
1157␍␊
1158 if ( reg_cmd_info.ec )␍␊
1159 return 1;␍␊
1160 return 0;␍␊
1161}␍␊
1162␍␊
1163//*************************************************************␍␊
1164//␍␊
1165// reg_pio_data_out_lba28() - Easy way to execute a PIO Data In command␍␊
1166// using an LBA sector address.␍␊
1167//␍␊
1168//*************************************************************␍␊
1169␍␊
1170int reg_pio_data_out_lba28( unsigned char dev, unsigned char cmd,␍␊
1171 unsigned int fr, unsigned int sc,␍␊
1172 unsigned long lba,␍␊
1173 unsigned char * bufAddr,␍␊
1174 long numSect, int multiCnt )␍␊
1175␍␊
1176{␍␊
1177␍␊
1178 reg_cmd_info.cmd = cmd;␍␊
1179 reg_cmd_info.fr = fr;␍␊
1180 reg_cmd_info.sc = sc;␍␊
1181 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
1182 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
1183 reg_cmd_info.lbaSize = LBA28;␍␊
1184 reg_cmd_info.lbaHigh = 0;␍␊
1185 reg_cmd_info.lbaLow = lba;␍␊
1186␍␊
1187 // adjust multiple count␍␊
1188 if ( multiCnt & 0x0800 )␍␊
1189 {␍␊
1190 // assume caller knows what they are doing␍␊
1191 multiCnt &= 0x00ff;␍␊
1192 }␍␊
1193 else␍␊
1194 {␍␊
1195 // only Write Multiple and CFA Write Multiple W/O Erase uses multiCnt␍␊
1196 if ( ( cmd != CMD_WRITE_MULTIPLE )␍␊
1197 && ( cmd != CMD_CFA_WRITE_MULTIPLE_WO_ERASE )␍␊
1198 )␍␊
1199 multiCnt = 1;␍␊
1200 }␍␊
1201␍␊
1202 reg_cmd_info.ns = numSect;␍␊
1203 reg_cmd_info.mc = multiCnt;␍␊
1204␍␊
1205 return exec_pio_data_out_cmd( dev, bufAddr, numSect, multiCnt );␍␊
1206}␍␊
1207␍␊
1208//*************************************************************␍␊
1209//␍␊
1210// reg_pio_data_out_lba48() - Easy way to execute a PIO Data In command␍␊
1211// using an LBA sector address.␍␊
1212//␍␊
1213//*************************************************************␍␊
1214␍␊
1215int reg_pio_data_out_lba48( unsigned char dev, unsigned char cmd,␍␊
1216 unsigned int fr, unsigned int sc,␍␊
1217 unsigned long lbahi, unsigned long lbalo,␍␊
1218 unsigned char * bufAddr,␍␊
1219 long numSect, int multiCnt )␍␊
1220␍␊
1221{␍␊
1222␍␊
1223 reg_cmd_info.cmd = cmd;␍␊
1224 reg_cmd_info.fr = fr;␍␊
1225 reg_cmd_info.sc = sc;␍␊
1226 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
1227 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
1228 reg_cmd_info.lbaSize = LBA48;␍␊
1229 reg_cmd_info.lbaHigh = lbahi;␍␊
1230 reg_cmd_info.lbaLow = lbalo;␍␊
1231␍␊
1232 // adjust multiple count␍␊
1233 if ( multiCnt & 0x0800 )␍␊
1234 {␍␊
1235 // assume caller knows what they are doing␍␊
1236 multiCnt &= 0x00ff;␍␊
1237 }␍␊
1238 else␍␊
1239 {␍␊
1240 // only Write Multiple Ext uses multiCnt␍␊
1241 if ( cmd != CMD_WRITE_MULTIPLE_EXT )␍␊
1242 multiCnt = 1;␍␊
1243 }␍␊
1244␍␊
1245 reg_cmd_info.ns = numSect;␍␊
1246 reg_cmd_info.mc = multiCnt;␍␊
1247␍␊
1248 return exec_pio_data_out_cmd( dev, bufAddr, numSect, multiCnt );␍␊
1249}␍␊
1250␍␊
1251#if INCLUDE_ATAPI_PIO␍␊
1252␍␊
1253//*************************************************************␍␊
1254//␍␊
1255// reg_packet() - Execute an ATAPI Packet (A0H) command.␍␊
1256//␍␊
1257// See ATA-4 Section 9.10, Figure 14.␍␊
1258//␍␊
1259//*************************************************************␍␊
1260␍␊
1261int reg_packet( unsigned char dev,␍␊
1262 unsigned int cpbc,␍␊
1263 unsigned char * cdbBufAddr,␍␊
1264 int dir,␍␊
1265 long dpbc,␍␊
1266 unsigned char * dataBufAddr )␍␊
1267␍␊
1268{␍␊
1269 unsigned char status;␍␊
1270 unsigned int byteCnt;␍␊
1271 long wordCnt;␍␊
1272␍␊
1273 // reset Bus Master Error bit␍␊
1274␍␊
1275 pio_writeBusMstrStatus( BM_SR_MASK_ERR );␍␊
1276␍␊
1277 // Make sure the command packet size is either 12 or 16␍␊
1278 // and save the command packet size and data.␍␊
1279␍␊
1280 cpbc = cpbc < 12 ? 12 : cpbc;␍␊
1281 cpbc = cpbc > 12 ? 16 : cpbc;␍␊
1282␍␊
1283 // Setup current command information.␍␊
1284␍␊
1285 reg_cmd_info.cmd = CMD_PACKET;␍␊
1286 reg_cmd_info.fr = 0;␍␊
1287 reg_cmd_info.sc = 0;␍␊
1288 reg_cmd_info.sn = 0;␍␊
1289 reg_cmd_info.cl = (unsigned char) ( dpbc & 0x00ff );␍␊
1290 reg_cmd_info.ch = ( unsigned char) ( ( dpbc & 0xff00 ) >> 8 );␍␊
1291 reg_cmd_info.dh = (unsigned char) ( dev ? CB_DH_DEV1 : CB_DH_DEV0 );␍␊
1292 reg_cmd_info.dc = (unsigned char) ( int_use_intr_flag ? 0 : CB_DC_NIEN );␍␊
1293␍␊
1294 // Set command time out.␍␊
1295␍␊
1296 tmr_set_timeout();␍␊
1297␍␊
1298 // Select the drive - call the sub_select function.␍␊
1299 // Quit now if this fails.␍␊
1300␍␊
1301 if ( sub_select( dev ) )␍␊
1302 {␍␊
1303 return 1;␍␊
1304 }␍␊
1305␍␊
1306 // Set up all the registers except the command register.␍␊
1307␍␊
1308 sub_setup_command();␍␊
1309␍␊
1310 // Start the command by setting the Command register. The drive␍␊
1311 // should immediately set BUSY status.␍␊
1312␍␊
1313 pio_outbyte( CB_CMD, CMD_PACKET );␍␊
1314␍␊
1315 // Waste some time by reading the alternate status a few times.␍␊
1316 // This gives the drive time to set BUSY in the status register on␍␊
1317 // really fast systems. If we don't do this, a slow drive on a fast␍␊
1318 // system may not set BUSY fast enough and we would think it had␍␊
1319 // completed the command when it really had not even started the␍␊
1320 // command yet.␍␊
1321␍␊
1322 DELAY400NS;␍␊
1323␍␊
1324 // Command packet transfer...␍␊
1325 // Poll Alternate Status for BSY=0.␍␊
1326␍␊
1327 while ( 1 )␍␊
1328 {␍␊
1329 status = pio_inbyte( CB_ASTAT ); // poll for not busy␍␊
1330 if ( ( status & CB_STAT_BSY ) == 0 )␍␊
1331 break;␍␊
1332 if ( tmr_chk_timeout() ) // time out yet ?␍␊
1333 {␍␊
1334 reg_cmd_info.to = 1;␍␊
1335 reg_cmd_info.ec = 51;␍␊
1336 dir = -1; // command done␍␊
1337 break;␍␊
1338 }␍␊
1339 }␍␊
1340␍␊
1341 // Command packet transfer...␍␊
1342 // Check for protocol failures... no interrupt here please!␍␊
1343␍␊
1344 // Command packet transfer...␍␊
1345 // If no error, transfer the command packet.␍␊
1346␍␊
1347 if ( reg_cmd_info.ec == 0 )␍␊
1348 {␍␊
1349␍␊
1350 // Command packet transfer...␍␊
1351 // Read the primary status register and the other ATAPI registers.␍␊
1352␍␊
1353 status = pio_inbyte( CB_STAT );␍␊
1354␍␊
1355 // Command packet transfer...␍␊
1356 // check status: must have BSY=0, DRQ=1 now␍␊
1357␍␊
1358 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
1359 != CB_STAT_DRQ␍␊
1360 )␍␊
1361 {␍␊
1362 reg_cmd_info.ec = 52;␍␊
1363 dir = -1; // command done␍␊
1364 }␍␊
1365 else␍␊
1366 {␍␊
1367 // Command packet transfer...␍␊
1368 // xfer the command packet (the cdb)␍␊
1369␍␊
1370 pio_drq_block_out( CB_DATA, cdbBufAddr, cpbc >> 1 );␍␊
1371␍␊
1372 DELAY400NS; // delay so device can get the status updated␍␊
1373 }␍␊
1374 }␍␊
1375␍␊
1376 // Data transfer loop...␍␊
1377 // If there is no error, enter the data transfer loop.␍␊
1378␍␊
1379 while ( reg_cmd_info.ec == 0 )␍␊
1380 {␍␊
1381 // Data transfer loop...␍␊
1382 // Wait for interrupt -or- wait for not BUSY -or- wait for time out.␍␊
1383␍␊
1384 sub_wait_poll( 53, 54 );␍␊
1385␍␊
1386 // Data transfer loop...␍␊
1387 // If there was a time out error, exit the data transfer loop.␍␊
1388␍␊
1389 if ( reg_cmd_info.ec )␍␊
1390 {␍␊
1391 dir = -1; // command done␍␊
1392 break;␍␊
1393 }␍␊
1394␍␊
1395 // Data transfer loop...␍␊
1396 // If using interrupts get the status read by the interrupt␍␊
1397 // handler, otherwise read the status register.␍␊
1398␍␊
1399 if ( int_use_intr_flag )␍␊
1400 status = int_ata_status;␍␊
1401 else␍␊
1402 status = pio_inbyte( CB_STAT );␍␊
1403␍␊
1404 // Data transfer loop...␍␊
1405 // Exit the read data loop if the device indicates this␍␊
1406 // is the end of the command.␍␊
1407␍␊
1408 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) == 0 )␍␊
1409 {␍␊
1410 dir = -1; // command done␍␊
1411 break;␍␊
1412 }␍␊
1413␍␊
1414 // Data transfer loop...␍␊
1415 // The device must want to transfer data...␍␊
1416 // check status: must have BSY=0, DRQ=1 now.␍␊
1417␍␊
1418 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) != CB_STAT_DRQ )␍␊
1419 {␍␊
1420 reg_cmd_info.ec = 55;␍␊
1421 dir = -1; // command done␍␊
1422 break;␍␊
1423 }␍␊
1424␍␊
1425 // Data transfer loop...␍␊
1426 // get the byte count, check for zero...␍␊
1427␍␊
1428 byteCnt = ( pio_inbyte( CB_CH ) << 8 ) | pio_inbyte( CB_CL );␍␊
1429 if ( byteCnt < 1 )␍␊
1430 {␍␊
1431 reg_cmd_info.ec = 59;␍␊
1432 dir = -1; // command done␍␊
1433 break;␍␊
1434 }␍␊
1435␍␊
1436 // Data transfer loop...␍␊
1437 // increment number of DRQ packets␍␊
1438␍␊
1439 reg_cmd_info.drqPackets ++ ;␍␊
1440␍␊
1441 // Data transfer loop...␍␊
1442 // transfer the data and update the i/o buffer address␍␊
1443 // and the number of bytes transfered.␍␊
1444␍␊
1445 wordCnt = ( byteCnt >> 1 ) + ( byteCnt & 0x0001 );␍␊
1446 reg_cmd_info.totalBytesXfer += ( wordCnt << 1 );␍␊
1447 if ( dir )␍␊
1448 pio_drq_block_out( CB_DATA, dataBufAddr, wordCnt );␍␊
1449 else␍␊
1450 pio_drq_block_in( CB_DATA, dataBufAddr, wordCnt );␍␊
1451 dataBufAddr = dataBufAddr + byteCnt;␍␊
1452␍␊
1453 DELAY400NS; // delay so device can get the status updated␍␊
1454 }␍␊
1455␍␊
1456 // End of command...␍␊
1457 // Wait for interrupt or poll for BSY=0,␍␊
1458 // but don't do this if there was any error or if this␍␊
1459 // was a commmand that did not transfer data.␍␊
1460␍␊
1461 if ( ( reg_cmd_info.ec == 0 ) && ( dir >= 0 ) )␍␊
1462 {␍␊
1463 sub_wait_poll( 56, 57 );␍␊
1464 }␍␊
1465␍␊
1466 // Final status check, only if no previous error.␍␊
1467␍␊
1468 if ( reg_cmd_info.ec == 0 )␍␊
1469 {␍␊
1470 // Final status check...␍␊
1471 // If using interrupts get the status read by the interrupt␍␊
1472 // handler, otherwise read the status register.␍␊
1473␍␊
1474 if ( int_use_intr_flag )␍␊
1475 status = int_ata_status;␍␊
1476 else␍␊
1477 status = pio_inbyte( CB_STAT );␍␊
1478␍␊
1479 // Final status check...␍␊
1480 // check for any error.␍␊
1481␍␊
1482 if ( status & ( CB_STAT_BSY | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
1483 {␍␊
1484 reg_cmd_info.ec = 58;␍␊
1485 }␍␊
1486 }␍␊
1487␍␊
1488 // Done...␍␊
1489␍␊
1490 // Final status check␍␊
1491 // BMIDE Error=1?␍␊
1492␍␊
1493 if ( pio_readBusMstrStatus() & BM_SR_MASK_ERR )␍␊
1494 {␍␊
1495 reg_cmd_info.ec = 78; // yes␍␊
1496 }␍␊
1497␍␊
1498 // All done. The return values of this function are described in␍␊
1499 // MINDRVR.H.␍␊
1500␍␊
1501 if ( reg_cmd_info.ec )␍␊
1502 return 1;␍␊
1503 return 0;␍␊
1504}␍␊
1505␍␊
1506#endif // INCLUDE_ATAPI␍␊
1507␍␊
1508#if INCLUDE_ATA_DMA␍␊
1509␍␊
1510//***********************************************************␍␊
1511//␍␊
1512// Some notes about PCI bus mastering DMA...␍␊
1513//␍␊
1514// !!! The DMA support in MINDRVR is based on x86 PCI bus mastering␍␊
1515// !!! ATA controller design as described by the T13 document␍␊
1516// !!! '1510 Host Controller Standard' (in sections 1-6).␍␊
1517//␍␊
1518// Note that the T13 1510D document also describes a␍␊
1519// complex DMA engine called ADMA. While ADMA is a good idea it␍␊
1520// will probably never be popular or widely implemented. MINDRVR␍␊
1521// does not support ADMA.␍␊
1522//␍␊
1523// The base address of the Bus Master Control Registers (BMIDE) is␍␊
1524// found in the PCI Configuration space for the ATA controller (at␍␊
1525// offset 0x20 in the config space data). This is normally an I/O␍␊
1526// address.␍␊
1527//␍␊
1528// The BMIDE data is 16 bytes of data starting at the BMIDE base␍␊
1529// address. The first 8 bytes is for the primary ATA channel and␍␊
1530// the second 8 bytes is for the secondary ATA channel. The 8 bytes␍␊
1531// contain a "command" byte and a "status" byte and a 4 byte␍␊
1532// (32-bit) physical memory address pointing to the Physical Region␍␊
1533// Descriptor (PRD) list. Each PRD entry describes an area of␍␊
1534// memory or data buffer for the DMA transfer. A region described␍␊
1535// by a PRD may not cross a 64K byte boundary in physical memory.␍␊
1536// Also, the PRD list must not cross a 64K byte boundary.␍␊
1537//␍␊
1538//***********************************************************␍␊
1539␍␊
1540//***********************************************************␍␊
1541//␍␊
1542// pci bus master registers and PRD list buffer,␍␊
1543// see the dma_pci_config() and set_up_xfer() functions.␍␊
1544//␍␊
1545// !!! Note that the PRD buffer is statically allocated here␍␊
1546// !!! but the actual address of the buffer is adjusted by␍␊
1547// !!! the dma_pci_config() function.␍␊
1548//␍␊
1549//***********************************************************␍␊
1550␍␊
1551static unsigned long * dma_pci_prd_ptr; // current PRD buffer address␍␊
1552static int dma_pci_num_prd; // current number of PRD entries␍␊
1553␍␊
1554static unsigned char statReg; // save BM status reg bits␍␊
1555static unsigned char rwControl; // read/write control bit setting␍␊
1556␍␊
1557#define MAX_TRANSFER_SIZE 262144L // max transfer size (in bytes,␍␊
1558 // should be multiple of 65536)␍␊
1559␍␊
1560#define MAX_SEG ((MAX_TRANSFER_SIZE/65536L)+2L) // number physical segments␍␊
1561#define MAX_PRD (MAX_SEG*4L) // number of PRDs required␍␊
1562␍␊
1563#define PRD_BUF_SIZE (48+(2*MAX_PRD*8)) // size of PRD list buffer␍␊
1564␍␊
1565static unsigned char prdBuf[PRD_BUF_SIZE]; // PRD buffer␍␊
1566static unsigned long * prdBufPtr; // first PRD addr␍␊
1567␍␊
1568//***********************************************************␍␊
1569//␍␊
1570// dma_pci_config() - configure/setup for Read/Write DMA␍␊
1571//␍␊
1572// The caller must call this function before attempting␍␊
1573// to use any ATA or ATAPI commands in PCI DMA mode.␍␊
1574//␍␊
1575// !!! MINDRVR assumes the entire DMA data transfer is contained␍␊
1576// !!! within a single contiguous I/O buffer. You may not need␍␊
1577// !!! the dma_pci_config() function depending on how your system␍␊
1578// !!! allocates the PRD buffer.␍␊
1579//␍␊
1580// !!! This function shows an example of PRD buffer allocation.␍␊
1581// !!! The PRD buffer must be aligned␍␊
1582// !!! on a 8 byte boundary and must not cross a 64K byte␍␊
1583// !!! boundary in memory.␍␊
1584//␍␊
1585//***********************************************************␍␊
1586␍␊
1587int dma_pci_config( void )␍␊
1588␍␊
1589{␍␊
1590 unsigned long lw;␍␊
1591␍␊
1592 // Set up the PRD entry list buffer address - the PRD entry list␍␊
1593 // may not span a 64KB boundary in physical memory. Space is␍␊
1594 // allocated (above) for this buffer such that it will be␍␊
1595 // aligned on a seqment boundary␍␊
1596 // and such that the PRD list will not span a 64KB boundary...␍␊
1597 lw = (unsigned long) prdBuf;␍␊
1598 // ...move up to an 8 byte boundary.␍␊
1599 lw = lw + 15;␍␊
1600 lw = lw & 0xfffffff8L;␍␊
1601 // ...check for 64KB boundary in the first part of the PRD buffer,␍␊
1602 // ...if so just move the buffer to that boundary.␍␊
1603 if ( ( lw & 0xffff0000L )␍␊
1604 !=␍␊
1605 ( ( lw + ( MAX_PRD * 8L ) - 1L ) & 0xffff0000L )␍␊
1606 )␍␊
1607 lw = ( lw + ( MAX_PRD * 8L ) ) & 0xffff0000L;␍␊
1608 // ... return the address of the first PRD␍␊
1609 dma_pci_prd_ptr = prdBufPtr = (unsigned long *) lw;␍␊
1610 // ... return the current number of PRD entries␍␊
1611 dma_pci_num_prd = 0;␍␊
1612␍␊
1613 // read the BM status reg and save the upper 3 bits.␍␊
1614 statReg = (unsigned char) ( pio_readBusMstrStatus() & 0x60 );␍␊
1615␍␊
1616 return 0;␍␊
1617}␍␊
1618␍␊
1619//***********************************************************␍␊
1620//␍␊
1621// set_up_xfer() -- set up the PRD entry list␍␊
1622//␍␊
1623// !!! MINDRVR assumes the entire DMA data transfer is contained␍␊
1624// !!! within a single contiguous I/O buffer. You may not need␍␊
1625// !!! a much more complex set_up_xfer() function to support␍␊
1626// !!! true scatter/gather lists.␍␊
1627//␍␊
1628// The PRD list must be aligned on an 8 byte boundary and the␍␊
1629// list must not cross a 64K byte boundary in memory.␍␊
1630//␍␊
1631//***********************************************************␍␊
1632␍␊
1633static int set_up_xfer( int dir, long bc, unsigned char * bufAddr );␍␊
1634␍␊
1635static int set_up_xfer( int dir, long bc, unsigned char * bufAddr )␍␊
1636␍␊
1637{␍␊
1638 int numPrd; // number of PRD required␍␊
1639 int maxPrd; // max number of PRD allowed␍␊
1640 unsigned long temp;␍␊
1641 unsigned long phyAddr; // physical memory address␍␊
1642 unsigned long * prdPtr; // pointer to PRD entry list␍␊
1643␍␊
1644 // disable/stop the dma channel, clear interrupt and error bits␍␊
1645 pio_writeBusMstrCmd( BM_CR_MASK_STOP );␍␊
1646 pio_writeBusMstrStatus( (unsigned char) ( statReg | BM_SR_MASK_INT | BM_SR_MASK_ERR ) );␍␊
1647␍␊
1648 // setup to build the PRD list...␍␊
1649 // ...max PRDs allowed␍␊
1650 maxPrd = (int) MAX_PRD;␍␊
1651 // ...PRD buffer address␍␊
1652 prdPtr = prdBufPtr;␍␊
1653 dma_pci_prd_ptr = prdPtr;␍␊
1654 // ... convert I/O buffer address to an physical memory address␍␊
1655 phyAddr = (unsigned long) bufAddr;␍␊
1656␍␊
1657 // build the PRD list...␍␊
1658 // ...PRD entry format:␍␊
1659 // +0 to +3 = memory address␍␊
1660 // +4 to +5 = 0x0000 (not EOT) or 0x8000 (EOT)␍␊
1661 // +6 to +7 = byte count␍␊
1662 // ...zero number of PRDs␍␊
1663 numPrd = 0;␍␊
1664 // ...loop to build each PRD␍␊
1665 while ( bc > 0 )␍␊
1666 {␍␊
1667 if ( numPrd >= maxPrd )␍␊
1668 return 1;␍␊
1669 // set this PRD's address␍␊
1670 prdPtr[0] = phyAddr;␍␊
1671 // set count for this PRD␍␊
1672 temp = 65536L; // max PRD length␍␊
1673 if ( temp > bc ) // count to large?␍␊
1674 temp = bc; // yes - use actual count␍␊
1675 // check if count will fit␍␊
1676 phyAddr = phyAddr + temp;␍␊
1677 if ( ( phyAddr & 0xffff0000L ) != ( prdPtr[0] & 0xffff0000L ) )␍␊
1678 {␍␊
1679 phyAddr = phyAddr & 0xffff0000L;␍␊
1680 temp = phyAddr - prdPtr[0];␍␊
1681 }␍␊
1682 // set this PRD's count␍␊
1683 prdPtr[1] = temp & 0x0000ffffL;␍␊
1684 // update byte count␍␊
1685 bc = bc - temp;␍␊
1686 // set the end bit in the prd list␍␊
1687 if ( bc < 1 )␍␊
1688 prdPtr[1] = prdPtr[1] | 0x80000000L;␍␊
1689 prdPtr ++ ;␍␊
1690 prdPtr ++ ;␍␊
1691 numPrd ++ ;␍␊
1692 }␍␊
1693␍␊
1694 // return the current PRD list size and␍␊
1695 // write into BMIDE PRD address registers.␍␊
1696␍␊
1697 dma_pci_num_prd = numPrd;␍␊
1698 * (unsigned long *) (pio_bmide_base_addr + BM_PRD_ADDR_LOW )␍␊
1699 = (unsigned long) prdBufPtr;␍␊
1700␍␊
1701 // set the read/write control:␍␊
1702 // PCI reads for ATA Write DMA commands,␍␊
1703 // PCI writes for ATA Read DMA commands.␍␊
1704␍␊
1705 if ( dir )␍␊
1706 rwControl = BM_CR_MASK_READ; // ATA Write DMA␍␊
1707 else␍␊
1708 rwControl = BM_CR_MASK_WRITE; // ATA Read DMA␍␊
1709 pio_writeBusMstrCmd( rwControl );␍␊
1710 return 0;␍␊
1711}␍␊
1712␍␊
1713//***********************************************************␍␊
1714//␍␊
1715// exec_pci_ata_cmd() - PCI Bus Master for ATA R/W DMA commands␍␊
1716//␍␊
1717//***********************************************************␍␊
1718␍␊
1719static int exec_pci_ata_cmd( unsigned char dev,␍␊
1720 unsigned char * bufAddr,␍␊
1721 long numSect );␍␊
1722␍␊
1723static int exec_pci_ata_cmd( unsigned char dev,␍␊
1724 unsigned char * bufAddr,␍␊
1725 long numSect )␍␊
1726␍␊
1727{␍␊
1728 unsigned char status;␍␊
1729␍␊
1730 // Quit now if the command is incorrect.␍␊
1731␍␊
1732 if ( ( reg_cmd_info.cmd != CMD_READ_DMA )␍␊
1733 && ( reg_cmd_info.cmd != CMD_READ_DMA_EXT )␍␊
1734 && ( reg_cmd_info.cmd != CMD_WRITE_DMA )␍␊
1735 && ( reg_cmd_info.cmd != CMD_WRITE_DMA_EXT ) )␍␊
1736 {␍␊
1737 reg_cmd_info.ec = 77;␍␊
1738 return 1;␍␊
1739 }␍␊
1740␍␊
1741 // Set up the dma transfer␍␊
1742␍␊
1743 if ( set_up_xfer( ( reg_cmd_info.cmd == CMD_WRITE_DMA )␍␊
1744 ||␍␊
1745 ( reg_cmd_info.cmd == CMD_WRITE_DMA_EXT ),␍␊
1746 numSect * 512L, bufAddr ) )␍␊
1747 {␍␊
1748 reg_cmd_info.ec = 61;␍␊
1749 return 1;␍␊
1750 }␍␊
1751␍␊
1752 // Set command time out.␍␊
1753␍␊
1754 tmr_set_timeout();␍␊
1755␍␊
1756 // Select the drive - call the sub_select function.␍␊
1757 // Quit now if this fails.␍␊
1758␍␊
1759 if ( sub_select( dev ) )␍␊
1760 {␍␊
1761 return 1;␍␊
1762 }␍␊
1763␍␊
1764 // Set up all the registers except the command register.␍␊
1765␍␊
1766 sub_setup_command();␍␊
1767␍␊
1768 // Start the command by setting the Command register. The drive␍␊
1769 // should immediately set BUSY status.␍␊
1770␍␊
1771 pio_outbyte( CB_CMD, reg_cmd_info.cmd );␍␊
1772␍␊
1773 // The drive should start executing the command including any␍␊
1774 // data transfer.␍␊
1775␍␊
1776 // Data transfer...␍␊
1777 // read the BMIDE regs␍␊
1778 // enable/start the dma channel.␍␊
1779 // read the BMIDE regs again␍␊
1780␍␊
1781 pio_readBusMstrCmd();␍␊
1782 pio_readBusMstrStatus();␍␊
1783 pio_writeBusMstrCmd( (unsigned char) ( rwControl | BM_CR_MASK_START ) );␍␊
1784 pio_readBusMstrCmd();␍␊
1785 pio_readBusMstrStatus();␍␊
1786␍␊
1787 // Data transfer...␍␊
1788 // the device and dma channel transfer the data here while we start␍␊
1789 // checking for command completion...␍␊
1790 // wait for the PCI BM Interrupt=1 (see ATAIOINT.C)...␍␊
1791␍␊
1792 if ( tmr_chk_timeout() ) // time out ?␍␊
1793 {␍␊
1794 reg_cmd_info.to = 1;␍␊
1795 reg_cmd_info.ec = 73;␍␊
1796 }␍␊
1797␍␊
1798 // End of command...␍␊
1799 // disable/stop the dma channel␍␊
1800␍␊
1801 status = int_bmide_status; // read BM status␍␊
1802 status &= ~ BM_SR_MASK_ACT; // ignore Active bit␍␊
1803 pio_writeBusMstrCmd( BM_CR_MASK_STOP ); // shutdown DMA␍␊
1804 pio_readBusMstrCmd(); // read BM cmd (just for trace)␍␊
1805 status |= pio_readBusMstrStatus(); // read BM status again␍␊
1806␍␊
1807 if ( reg_cmd_info.ec == 0 )␍␊
1808 {␍␊
1809 if ( status & BM_SR_MASK_ERR ) // bus master error?␍␊
1810 {␍␊
1811 reg_cmd_info.ec = 78; // yes␍␊
1812 }␍␊
1813 }␍␊
1814 if ( reg_cmd_info.ec == 0 )␍␊
1815 {␍␊
1816 if ( status & BM_SR_MASK_ACT ) // end of PRD list?␍␊
1817 {␍␊
1818 reg_cmd_info.ec = 71; // no␍␊
1819 }␍␊
1820 }␍␊
1821␍␊
1822 // End of command...␍␊
1823 // If no error use the Status register value that was read␍␊
1824 // by the interrupt handler. If there was an error␍␊
1825 // read the Status register because it may not have been␍␊
1826 // read by the interrupt handler.␍␊
1827␍␊
1828 if ( reg_cmd_info.ec )␍␊
1829 status = pio_inbyte( CB_STAT );␍␊
1830 else␍␊
1831 status = int_ata_status;␍␊
1832␍␊
1833 // Final status check...␍␊
1834 // if no error, check final status...␍␊
1835 // Error if BUSY, DEVICE FAULT, DRQ or ERROR status now.␍␊
1836␍␊
1837 if ( reg_cmd_info.ec == 0 )␍␊
1838 {␍␊
1839 if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
1840 {␍␊
1841 reg_cmd_info.ec = 74;␍␊
1842 }␍␊
1843 }␍␊
1844␍␊
1845 // Final status check...␍␊
1846 // if any error, update total bytes transferred.␍␊
1847␍␊
1848 if ( reg_cmd_info.ec == 0 )␍␊
1849 reg_cmd_info.totalBytesXfer = numSect * 512L;␍␊
1850 else␍␊
1851 reg_cmd_info.totalBytesXfer = 0L;␍␊
1852␍␊
1853 // All done. The return values of this function are described in␍␊
1854 // MINDRVR.H.␍␊
1855␍␊
1856 if ( reg_cmd_info.ec )␍␊
1857 return 1;␍␊
1858 return 0;␍␊
1859}␍␊
1860␍␊
1861//***********************************************************␍␊
1862//␍␊
1863// dma_pci_lba28() - DMA in PCI Multiword for ATA R/W DMA␍␊
1864//␍␊
1865//***********************************************************␍␊
1866␍␊
1867int dma_pci_lba28( unsigned char dev, unsigned char cmd,␍␊
1868 unsigned int fr, unsigned int sc,␍␊
1869 unsigned long lba,␍␊
1870 unsigned char * bufAddr,␍␊
1871 long numSect )␍␊
1872␍␊
1873{␍␊
1874␍␊
1875 // Setup current command information.␍␊
1876␍␊
1877 reg_cmd_info.cmd = cmd;␍␊
1878 reg_cmd_info.fr = fr;␍␊
1879 reg_cmd_info.sc = sc;␍␊
1880 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
1881 reg_cmd_info.dc = 0x00; // nIEN=0 required on PCI !␍␊
1882 reg_cmd_info.ns = numSect;␍␊
1883 reg_cmd_info.lbaSize = LBA28;␍␊
1884 reg_cmd_info.lbaHigh = 0L;␍␊
1885 reg_cmd_info.lbaLow = lba;␍␊
1886␍␊
1887 // Execute the command.␍␊
1888␍␊
1889 return exec_pci_ata_cmd( dev, bufAddr, numSect );␍␊
1890}␍␊
1891␍␊
1892//***********************************************************␍␊
1893//␍␊
1894// dma_pci_lba48() - DMA in PCI Multiword for ATA R/W DMA␍␊
1895//␍␊
1896//***********************************************************␍␊
1897␍␊
1898int dma_pci_lba48( unsigned char dev, unsigned char cmd,␍␊
1899 unsigned int fr, unsigned int sc,␍␊
1900 unsigned long lbahi, unsigned long lbalo,␍␊
1901 unsigned char * bufAddr,␍␊
1902 long numSect )␍␊
1903␍␊
1904{␍␊
1905␍␊
1906 // Setup current command information.␍␊
1907␍␊
1908 reg_cmd_info.cmd = cmd;␍␊
1909 reg_cmd_info.fr = fr;␍␊
1910 reg_cmd_info.sc = sc;␍␊
1911 reg_cmd_info.dh = (unsigned char) ( CB_DH_LBA | ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
1912 reg_cmd_info.dc = 0x00; // nIEN=0 required on PCI !␍␊
1913 reg_cmd_info.ns = numSect;␍␊
1914 reg_cmd_info.lbaSize = LBA48;␍␊
1915 reg_cmd_info.lbaHigh = lbahi;␍␊
1916 reg_cmd_info.lbaLow = lbalo;␍␊
1917␍␊
1918 // Execute the command.␍␊
1919␍␊
1920 return exec_pci_ata_cmd( dev, bufAddr, numSect );␍␊
1921}␍␊
1922␍␊
1923#endif // INCLUDE_ATA_DMA␍␊
1924␍␊
1925#if INCLUDE_ATAPI_DMA␍␊
1926␍␊
1927//***********************************************************␍␊
1928//␍␊
1929// dma_pci_packet() - PCI Bus Master for ATAPI Packet command␍␊
1930//␍␊
1931//***********************************************************␍␊
1932␍␊
1933int dma_pci_packet( unsigned char dev,␍␊
1934 unsigned int cpbc,␍␊
1935 unsigned char * cdbBufAddr,␍␊
1936 int dir,␍␊
1937 long dpbc,␍␊
1938 unsigned char * dataBufAddr )␍␊
1939␍␊
1940{␍␊
1941 unsigned char status;␍␊
1942␍␊
1943 // Make sure the command packet size is either 12 or 16␍␊
1944 // and save the command packet size and data.␍␊
1945␍␊
1946 cpbc = cpbc < 12 ? 12 : cpbc;␍␊
1947 cpbc = cpbc > 12 ? 16 : cpbc;␍␊
1948␍␊
1949 // Setup current command information.␍␊
1950␍␊
1951 reg_cmd_info.cmd = CMD_PACKET;␍␊
1952 reg_cmd_info.fr = 0x01; // packet DMA mode !␍␊
1953 reg_cmd_info.sc = 0;␍␊
1954 reg_cmd_info.sn = 0;␍␊
1955 reg_cmd_info.cl = 0; // no Byte Count Limit in DMA !␍␊
1956 reg_cmd_info.ch = 0; // no Byte Count Limit in DMA !␍␊
1957 reg_cmd_info.dh = (unsigned char) ( dev ? CB_DH_DEV1 : CB_DH_DEV0 );␍␊
1958 reg_cmd_info.dc = 0x00; // nIEN=0 required on PCI !␍␊
1959␍␊
1960 // the data packet byte count must be even␍␊
1961 // and must not be zero␍␊
1962␍␊
1963 if ( dpbc & 1L )␍␊
1964 dpbc ++ ;␍␊
1965 if ( dpbc < 2L )␍␊
1966 dpbc = 2L;␍␊
1967␍␊
1968 // Set up the dma transfer␍␊
1969␍␊
1970 if ( set_up_xfer( dir, dpbc, dataBufAddr ) )␍␊
1971 {␍␊
1972 reg_cmd_info.ec = 61;␍␊
1973 return 1;␍␊
1974 }␍␊
1975␍␊
1976 // Set command time out.␍␊
1977␍␊
1978 tmr_set_timeout();␍␊
1979␍␊
1980 // Select the drive - call the reg_select function.␍␊
1981 // Quit now if this fails.␍␊
1982␍␊
1983 if ( sub_select( dev ) )␍␊
1984 {␍␊
1985 return 1;␍␊
1986 }␍␊
1987␍␊
1988 // Set up all the registers except the command register.␍␊
1989␍␊
1990 sub_setup_command();␍␊
1991␍␊
1992 // Start the command by setting the Command register. The drive␍␊
1993 // should immediately set BUSY status.␍␊
1994␍␊
1995 pio_outbyte( CB_CMD, CMD_PACKET );␍␊
1996␍␊
1997 // Waste some time by reading the alternate status a few times.␍␊
1998 // This gives the drive time to set BUSY in the status register on␍␊
1999 // really fast systems. If we don't do this, a slow drive on a fast␍␊
2000 // system may not set BUSY fast enough and we would think it had␍␊
2001 // completed the command when it really had not started the␍␊
2002 // command yet.␍␊
2003␍␊
2004 DELAY400NS;␍␊
2005␍␊
2006 // Command packet transfer...␍␊
2007 // Poll Alternate Status for BSY=0.␍␊
2008␍␊
2009 while ( 1 )␍␊
2010 {␍␊
2011 status = pio_inbyte( CB_ASTAT ); // poll for not busy␍␊
2012 if ( ( status & CB_STAT_BSY ) == 0 )␍␊
2013 break;␍␊
2014 if ( tmr_chk_timeout() ) // time out yet ?␍␊
2015 {␍␊
2016 reg_cmd_info.to = 1;␍␊
2017 reg_cmd_info.ec = 75;␍␊
2018 break;␍␊
2019 }␍␊
2020 }␍␊
2021␍␊
2022 // Command packet transfer...␍␊
2023 // Check for protocol failures... no interrupt here please!␍␊
2024␍␊
2025 // Command packet transfer...␍␊
2026 // If no error, transfer the command packet.␍␊
2027␍␊
2028 if ( reg_cmd_info.ec == 0 )␍␊
2029 {␍␊
2030␍␊
2031 // Command packet transfer...␍␊
2032 // Read the primary status register and the other ATAPI registers.␍␊
2033␍␊
2034 status = pio_inbyte( CB_STAT );␍␊
2035␍␊
2036 // Command packet transfer...␍␊
2037 // check status: must have BSY=0, DRQ=1 now␍␊
2038␍␊
2039 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
2040 != CB_STAT_DRQ␍␊
2041 )␍␊
2042 {␍␊
2043 reg_cmd_info.ec = 76;␍␊
2044 }␍␊
2045 else␍␊
2046 {␍␊
2047␍␊
2048 // Command packet transfer...␍␊
2049 // xfer the command packet (the cdb)␍␊
2050␍␊
2051 pio_drq_block_out( CB_DATA, cdbBufAddr, cpbc >> 1 );␍␊
2052 }␍␊
2053 }␍␊
2054␍␊
2055 // Data transfer...␍␊
2056 // The drive should start executing the command␍␊
2057 // including any data transfer.␍␊
2058 // If no error, set up and start the DMA,␍␊
2059 // and wait for the DMA to complete.␍␊
2060␍␊
2061 if ( reg_cmd_info.ec == 0 )␍␊
2062 {␍␊
2063␍␊
2064 // Data transfer...␍␊
2065 // read the BMIDE regs␍␊
2066 // enable/start the dma channel.␍␊
2067 // read the BMIDE regs again␍␊
2068␍␊
2069 pio_readBusMstrCmd();␍␊
2070 pio_readBusMstrStatus();␍␊
2071 pio_writeBusMstrCmd( (unsigned char) ( rwControl | BM_CR_MASK_START ) );␍␊
2072 pio_readBusMstrCmd();␍␊
2073 pio_readBusMstrStatus();␍␊
2074␍␊
2075 // Data transfer...␍␊
2076 // the device and dma channel transfer the data here while we start␍␊
2077 // checking for command completion...␍␊
2078 // wait for the PCI BM Active=0 and Interrupt=1 or PCI BM Error=1...␍␊
2079␍␊
2080 if ( tmr_chk_timeout() ) // time out ?␍␊
2081 {␍␊
2082 reg_cmd_info.to = 1;␍␊
2083 reg_cmd_info.ec = 73;␍␊
2084 }␍␊
2085␍␊
2086 // End of command...␍␊
2087 // disable/stop the dma channel␍␊
2088␍␊
2089 status = int_bmide_status; // read BM status␍␊
2090 status &= ~ BM_SR_MASK_ACT; // ignore Active bit␍␊
2091 pio_writeBusMstrCmd( BM_CR_MASK_STOP ); // shutdown DMA␍␊
2092 pio_readBusMstrCmd(); // read BM cmd (just for trace)␍␊
2093 status |= pio_readBusMstrStatus(); // read BM statu again␍␊
2094 }␍␊
2095␍␊
2096 if ( reg_cmd_info.ec == 0 )␍␊
2097 {␍␊
2098 if ( status & ( BM_SR_MASK_ERR ) ) // bus master error?␍␊
2099 {␍␊
2100 reg_cmd_info.ec = 78; // yes␍␊
2101 }␍␊
2102 if ( ( status & BM_SR_MASK_ACT ) ) // end of PRD list?␍␊
2103 {␍␊
2104 reg_cmd_info.ec = 71; // no␍␊
2105 }␍␊
2106 }␍␊
2107␍␊
2108 // End of command...␍␊
2109 // If no error use the Status register value that was read␍␊
2110 // by the interrupt handler. If there was an error␍␊
2111 // read the Status register because it may not have been␍␊
2112 // read by the interrupt handler.␍␊
2113␍␊
2114 if ( reg_cmd_info.ec )␍␊
2115 status = pio_inbyte( CB_STAT );␍␊
2116 else␍␊
2117 status = int_ata_status;␍␊
2118␍␊
2119 // Final status check...␍␊
2120 // if no error, check final status...␍␊
2121 // Error if BUSY, DRQ or ERROR status now.␍␊
2122␍␊
2123 if ( reg_cmd_info.ec == 0 )␍␊
2124 {␍␊
2125 if ( status & ( CB_STAT_BSY | CB_STAT_DRQ | CB_STAT_ERR ) )␍␊
2126 {␍␊
2127 reg_cmd_info.ec = 74;␍␊
2128 }␍␊
2129 }␍␊
2130␍␊
2131␍␊
2132 // Final status check...␍␊
2133 // if any error, update total bytes transferred.␍␊
2134␍␊
2135 if ( reg_cmd_info.ec == 0 )␍␊
2136 reg_cmd_info.totalBytesXfer = dpbc;␍␊
2137 else␍␊
2138 reg_cmd_info.totalBytesXfer = 0L;␍␊
2139␍␊
2140 // All done. The return values of this function are described in␍␊
2141 // MINDRVR.H.␍␊
2142␍␊
2143 if ( reg_cmd_info.ec )␍␊
2144 return 1;␍␊
2145 return 0;␍␊
2146}␍␊
2147␍␊
2148#endif // INCLUDE_ATAPI_DMA␍␊
2149␍␊
2150//*************************************************************␍␊
2151//␍␊
2152// sub_setup_command() -- setup the command parameters␍␊
2153// in FR, SC, SN, CL, CH and DH.␍␊
2154//␍␊
2155//*************************************************************␍␊
2156␍␊
2157static void sub_setup_command( void )␍␊
2158␍␊
2159{␍␊
2160␍␊
2161 // output DevCtrl - same for all devices and commands␍␊
2162 pio_outbyte( CB_DC, reg_cmd_info.dc );␍␊
2163␍␊
2164 // output command parameters␍␊
2165 if ( reg_cmd_info.lbaSize == LBA28 )␍␊
2166 {␍␊
2167 // in ATA LBA28 mode␍␊
2168 pio_outbyte( CB_FR, (unsigned char) reg_cmd_info.fr );␍␊
2169 pio_outbyte( CB_SC, (unsigned char) reg_cmd_info.sc );␍␊
2170 pio_outbyte( CB_SN, (unsigned char) reg_cmd_info.lbaLow );␍␊
2171 pio_outbyte( CB_CL, (unsigned char) ( reg_cmd_info.lbaLow >> 8 ) );␍␊
2172 pio_outbyte( CB_CH, (unsigned char) ( reg_cmd_info.lbaLow >> 16 ) );␍␊
2173 pio_outbyte( CB_DH, (unsigned char) ( ( reg_cmd_info.dh & 0xf0 )␍␊
2174 | ( ( reg_cmd_info.lbaLow >> 24 ) & 0x0f ) ) );␍␊
2175 }␍␊
2176 else␍␊
2177 if ( reg_cmd_info.lbaSize == LBA48 )␍␊
2178 {␍␊
2179 // in ATA LBA48 mode␍␊
2180 pio_outbyte( CB_FR, (unsigned char) ( reg_cmd_info.fr >> 8 ) );␍␊
2181 pio_outbyte( CB_SC, (unsigned char) ( reg_cmd_info.sc >> 8 ) );␍␊
2182 pio_outbyte( CB_SN, (unsigned char) ( reg_cmd_info.lbaLow >> 24 ) );␍␊
2183 pio_outbyte( CB_CL, (unsigned char) reg_cmd_info.lbaHigh );␍␊
2184 pio_outbyte( CB_CH, (unsigned char) ( reg_cmd_info.lbaHigh >> 8 ) );␍␊
2185 pio_outbyte( CB_FR, (unsigned char) reg_cmd_info.fr );␍␊
2186 pio_outbyte( CB_SC, (unsigned char) reg_cmd_info.sc );␍␊
2187 pio_outbyte( CB_SN, (unsigned char) reg_cmd_info.lbaLow );␍␊
2188 pio_outbyte( CB_CL, (unsigned char) ( reg_cmd_info.lbaLow >> 8 ) );␍␊
2189 pio_outbyte( CB_CH, (unsigned char) ( reg_cmd_info.lbaLow >> 16 ) );␍␊
2190 pio_outbyte( CB_DH, reg_cmd_info.dh );␍␊
2191 }␍␊
2192 else␍␊
2193 {␍␊
2194 // for ATAPI PACKET command␍␊
2195 pio_outbyte( CB_FR, (unsigned char) reg_cmd_info.fr );␍␊
2196 pio_outbyte( CB_SC, (unsigned char) reg_cmd_info.sc );␍␊
2197 pio_outbyte( CB_SN, (unsigned char) reg_cmd_info.sn );␍␊
2198 pio_outbyte( CB_CL, (unsigned char) reg_cmd_info.cl );␍␊
2199 pio_outbyte( CB_CH, (unsigned char) reg_cmd_info.ch );␍␊
2200 pio_outbyte( CB_DH, reg_cmd_info.dh );␍␊
2201 }␍␊
2202}␍␊
2203␍␊
2204//*************************************************************␍␊
2205//␍␊
2206// sub_trace_command() -- trace the end of a command.␍␊
2207//␍␊
2208//*************************************************************␍␊
2209␍␊
2210static void sub_trace_command( void )␍␊
2211␍␊
2212{␍␊
2213␍␊
2214 reg_cmd_info.st = pio_inbyte( CB_STAT );␍␊
2215 reg_cmd_info.as = pio_inbyte( CB_ASTAT );␍␊
2216 reg_cmd_info.er = pio_inbyte( CB_ERR );␍␊
2217␍␊
2218// !!! if you want to read back the other device registers␍␊
2219// !!! at the end of a command then this is the place to do␍␊
2220// !!! it. The code here is just and example of out this is␍␊
2221// !!! done on a little endian system like an x86.␍␊
2222␍␊
2223#if 0 // read back other registers␍␊
2224␍␊
2225 {␍␊
2226 unsigned long lbaHigh;␍␊
2227 unsigned long lbaLow;␍␊
2228 unsigned char sc48[2];␍␊
2229 unsigned char lba48[8];␍␊
2230␍␊
2231 lbaHigh = 0;␍␊
2232 lbaLow = 0;␍␊
2233 if ( reg_cmd_info.lbaSize == LBA48 )␍␊
2234 {␍␊
2235 // read back ATA LBA48...␍␊
2236 sc48[0] = pio_inbyte( CB_SC );␍␊
2237 lba48[0] = pio_inbyte( CB_SN );␍␊
2238 lba48[1] = pio_inbyte( CB_CL );␍␊
2239 lba48[2] = pio_inbyte( CB_CH );␍␊
2240 pio_outbyte( CB_DC, CB_DC_HOB );␍␊
2241 sc48[1] = pio_inbyte( CB_SC );␍␊
2242 lba48[3] = pio_inbyte( CB_SN );␍␊
2243 lba48[4] = pio_inbyte( CB_CL );␍␊
2244 lba48[5] = pio_inbyte( CB_CH );␍␊
2245 lba48[6] = 0;␍␊
2246 lba48[7] = 0;␍␊
2247 lbaHigh = * (unsigned long *) ( lba48 + 4 );␍␊
2248 lbaLow = * (unsigned long *) ( lba48 + 0 );␍␊
2249 }␍␊
2250 else␍␊
2251 if ( reg_cmd_info.lbaSize == LBA28 )␍␊
2252 {␍␊
2253 // read back ATA LBA28␍␊
2254 lbaLow = pio_inbyte( CB_DH );␍␊
2255 lbaLow = lbaLow << 8;␍␊
2256 lbaLow = lbaLow | pio_inbyte( CB_CH );␍␊
2257 lbaLow = lbaLow << 8;␍␊
2258 lbaLow = lbaLow | pio_inbyte( CB_CL );␍␊
2259 lbaLow = lbaLow << 8;␍␊
2260 lbaLow = lbaLow | pio_inbyte( CB_SN );␍␊
2261 }␍␊
2262 else␍␊
2263 {␍␊
2264 // really no reason to read back for ATAPI␍␊
2265 }␍␊
2266 }␍␊
2267␍␊
2268#endif // read back other registers␍␊
2269␍␊
2270}␍␊
2271␍␊
2272//*************************************************************␍␊
2273//␍␊
2274// sub_select() - function used to select a drive.␍␊
2275//␍␊
2276// Function to select a drive making sure that BSY=0 and DRQ=0.␍␊
2277//␍␊
2278//**************************************************************␍␊
2279␍␊
2280static int sub_select( unsigned char dev )␍␊
2281␍␊
2282{␍␊
2283 unsigned char status;␍␊
2284␍␊
2285 // PAY ATTENTION HERE␍␊
2286 // The caller may want to issue a command to a device that doesn't␍␊
2287 // exist (for example, Exec Dev Diag), so if we see this,␍␊
2288 // just select that device, skip all status checking and return.␍␊
2289 // We assume the caller knows what they are doing!␍␊
2290␍␊
2291 if ( reg_config_info[dev] < REG_CONFIG_TYPE_ATA )␍␊
2292 {␍␊
2293 // select the device and return␍␊
2294␍␊
2295 pio_outbyte( CB_DH, (unsigned char) ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
2296 DELAY400NS;␍␊
2297 return 0;␍␊
2298 }␍␊
2299␍␊
2300 // The rest of this is the normal ATA stuff for device selection␍␊
2301 // and we don't expect the caller to be selecting a device that␍␊
2302 // does not exist.␍␊
2303 // We don't know which drive is currently selected but we should␍␊
2304 // wait BSY=0 and DRQ=0. Normally both BSY=0 and DRQ=0␍␊
2305 // unless something is very wrong!␍␊
2306␍␊
2307 while ( 1 )␍␊
2308 {␍␊
2309 status = pio_inbyte( CB_STAT );␍␊
2310 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) == 0 )␍␊
2311 break;␍␊
2312 if ( tmr_chk_timeout() )␍␊
2313 {␍␊
2314 reg_cmd_info.to = 1;␍␊
2315 reg_cmd_info.ec = 11;␍␊
2316 reg_cmd_info.st = status;␍␊
2317 reg_cmd_info.as = pio_inbyte( CB_ASTAT );␍␊
2318 reg_cmd_info.er = pio_inbyte( CB_ERR );␍␊
2319 return 1;␍␊
2320 }␍␊
2321 }␍␊
2322␍␊
2323 // Here we select the drive we really want to work with by␍␊
2324 // setting the DEV bit in the Drive/Head register.␍␊
2325␍␊
2326 pio_outbyte( CB_DH, (unsigned char) ( dev ? CB_DH_DEV1 : CB_DH_DEV0 ) );␍␊
2327 DELAY400NS;␍␊
2328␍␊
2329 // Wait for the selected device to have BSY=0 and DRQ=0.␍␊
2330 // Normally the drive should be in this state unless␍␊
2331 // something is very wrong (or initial power up is still in␍␊
2332 // progress).␍␊
2333␍␊
2334 while ( 1 )␍␊
2335 {␍␊
2336 status = pio_inbyte( CB_STAT );␍␊
2337 if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) == 0 )␍␊
2338 break;␍␊
2339 if ( tmr_chk_timeout() )␍␊
2340 {␍␊
2341 reg_cmd_info.to = 1;␍␊
2342 reg_cmd_info.ec = 12;␍␊
2343 reg_cmd_info.st = status;␍␊
2344 reg_cmd_info.as = pio_inbyte( CB_ASTAT );␍␊
2345 reg_cmd_info.er = pio_inbyte( CB_ERR );␍␊
2346 return 1;␍␊
2347 }␍␊
2348 }␍␊
2349␍␊
2350 // All done. The return values of this function are described in␍␊
2351 // ATAIO.H.␍␊
2352␍␊
2353 if ( reg_cmd_info.ec )␍␊
2354 return 1;␍␊
2355 return 0;␍␊
2356}␍␊
2357␍␊
2358//*************************************************************␍␊
2359//␍␊
2360// sub_wait_poll() - wait for interrupt or poll for BSY=0␍␊
2361//␍␊
2362//*************************************************************␍␊
2363␍␊
2364static void sub_wait_poll( unsigned char we, unsigned char pe )␍␊
2365␍␊
2366{␍␊
2367 unsigned char status;␍␊
2368␍␊
2369 // Wait for interrupt -or- wait for not BUSY -or- wait for time out.␍␊
2370␍␊
2371 if ( we && int_use_intr_flag )␍␊
2372 {␍␊
2373 if ( tmr_chk_timeout() ) // time out ?␍␊
2374 {␍␊
2375 reg_cmd_info.to = 1;␍␊
2376 reg_cmd_info.ec = we;␍␊
2377 }␍␊
2378 }␍␊
2379 else␍␊
2380 {␍␊
2381 while ( 1 )␍␊
2382 {␍␊
2383 status = pio_inbyte( CB_ASTAT ); // poll for not busy␍␊
2384 if ( ( status & CB_STAT_BSY ) == 0 )␍␊
2385 break;␍␊
2386 if ( tmr_chk_timeout() ) // time out yet ?␍␊
2387 {␍␊
2388 reg_cmd_info.to = 1;␍␊
2389 reg_cmd_info.ec = pe;␍␊
2390 break;␍␊
2391 }␍␊
2392 }␍␊
2393 }␍␊
2394}␍␊
2395␍␊
2396//***********************************************************␍␊
2397//␍␊
2398// functions used to read/write the BMIDE registers␍␊
2399//␍␊
2400//***********************************************************␍␊
2401␍␊
2402static unsigned char pio_readBusMstrCmd( void )␍␊
2403␍␊
2404{␍␊
2405 unsigned char x;␍␊
2406␍␊
2407 if ( ! pio_bmide_base_addr )␍␊
2408 return 0;␍␊
2409 x = inb (pio_bmide_base_addr + BM_COMMAND_REG );␍␊
2410 return x;␍␊
2411}␍␊
2412␍␊
2413␍␊
2414static unsigned char pio_readBusMstrStatus( void )␍␊
2415␍␊
2416{␍␊
2417 unsigned char x;␍␊
2418␍␊
2419 if ( ! pio_bmide_base_addr )␍␊
2420 return 0;␍␊
2421 x = inb( pio_bmide_base_addr + BM_STATUS_REG );␍␊
2422 return x;␍␊
2423}␍␊
2424␍␊
2425␍␊
2426static void pio_writeBusMstrCmd( unsigned char x )␍␊
2427␍␊
2428{␍␊
2429␍␊
2430 if ( ! pio_bmide_base_addr )␍␊
2431 return;␍␊
2432 outb(( pio_bmide_base_addr + BM_COMMAND_REG ), x);␍␊
2433}␍␊
2434␍␊
2435␍␊
2436static void pio_writeBusMstrStatus( unsigned char x )␍␊
2437␍␊
2438{␍␊
2439␍␊
2440 if ( ! pio_bmide_base_addr )␍␊
2441 return;␍␊
2442 outb(( pio_bmide_base_addr + BM_STATUS_REG ), x);␍␊
2443}␍␊
2444␍␊
2445//*************************************************************␍␊
2446//␍␊
2447// These functions do basic IN/OUT of byte and word values:␍␊
2448//␍␊
2449// pio_inbyte()␍␊
2450// pio_outbyte()␍␊
2451// pio_inword()␍␊
2452// pio_outword()␍␊
2453//␍␊
2454//*************************************************************␍␊
2455/*␍␊
2456static unsigned char pio_inbyte( unsigned char addr )␍␊
2457␍␊
2458{␍␊
2459␍␊
2460 //!!! read an 8-bit ATA register␍␊
2461␍␊
2462 return * pio_reg_addrs[ addr ];␍␊
2463}␍␊
2464␍␊
2465//*************************************************************␍␊
2466␍␊
2467static void pio_outbyte( int addr, unsigned char data )␍␊
2468␍␊
2469{␍␊
2470␍␊
2471 //!!! write an 8-bit ATA register␍␊
2472␍␊
2473 * pio_reg_addrs[ addr ] = data;␍␊
2474}␍␊
2475␍␊
2476//*************************************************************␍␊
2477␍␊
2478static unsigned int pio_inword( unsigned char addr )␍␊
2479␍␊
2480{␍␊
2481␍␊
2482 //!!! read an 8-bit ATA register (usually the ATA Data register)␍␊
2483␍␊
2484 return * ( (unsigned int *) pio_reg_addrs[ addr ] );␍␊
2485}␍␊
2486␍␊
2487//*************************************************************␍␊
2488␍␊
2489static void pio_outword( int addr, unsigned int data )␍␊
2490␍␊
2491{␍␊
2492␍␊
2493 //!!! Write an 8-bit ATA register (usually the ATA Data register)␍␊
2494␍␊
2495 * ( (unsigned int *) pio_reg_addrs[ addr ] ) = data;␍␊
2496}␍␊
2497␍␊
2498//*************************************************************␍␊
2499␍␊
2500static unsigned long pio_indword( unsigned char addr )␍␊
2501␍␊
2502{␍␊
2503␍␊
2504 //!!! read an 8-bit ATA register (usually the ATA Data register)␍␊
2505␍␊
2506 return * ( (unsigned long *) pio_reg_addrs[ addr ] );␍␊
2507}␍␊
2508␍␊
2509//*************************************************************␍␊
2510␍␊
2511static void pio_outdword( int addr, unsigned long data )␍␊
2512␍␊
2513{␍␊
2514␍␊
2515 //!!! Write an 8-bit ATA register (usually the ATA Data register)␍␊
2516␍␊
2517 * ( (unsigned long *) pio_reg_addrs[ addr ] ) = data;␍␊
2518}␍␊
2519␍␊
2520␍␊
2521*/␍␊
2522unsigned char pio_inbyte( unsigned char addr )␍␊
2523␍␊
2524{␍␊
2525␍␊
2526 //!!! read an 8-bit ATA register␍␊
2527␍␊
2528 return inb((unsigned int)pio_reg_addrs[ addr ]);␍␊
2529}␍␊
2530␍␊
2531//*************************************************************␍␊
2532␍␊
2533void pio_outbyte( int addr, unsigned char data )␍␊
2534␍␊
2535{␍␊
2536␍␊
2537 //!!! write an 8-bit ATA register␍␊
2538␍␊
2539 outb((unsigned int)pio_reg_addrs[ addr ], data);␍␊
2540}␍␊
2541␍␊
2542//*************************************************************␍␊
2543␍␊
2544static unsigned int pio_inword( unsigned char addr )␍␊
2545␍␊
2546{␍␊
2547␍␊
2548 //!!! read an 8-bit ATA register (usually the ATA Data register)␍␊
2549␍␊
2550 return inw((unsigned int)pio_reg_addrs[ addr ] );␍␊
2551}␍␊
2552␍␊
2553//*************************************************************␍␊
2554␍␊
2555static void pio_outword( int addr, unsigned int data )␍␊
2556␍␊
2557{␍␊
2558␍␊
2559 //!!! Write an 8-bit ATA register (usually the ATA Data register)␍␊
2560␍␊
2561 outw((unsigned int)pio_reg_addrs[ addr ], data);␍␊
2562}␍␊
2563␍␊
2564//*************************************************************␍␊
2565␍␊
2566static unsigned long pio_indword( unsigned char addr )␍␊
2567␍␊
2568{␍␊
2569␍␊
2570 //!!! read an 8-bit ATA register (usually the ATA Data register)␍␊
2571␍␊
2572 return inl((unsigned int)pio_reg_addrs[ addr ] );␍␊
2573}␍␊
2574␍␊
2575//*************************************************************␍␊
2576␍␊
2577static void pio_outdword( int addr, unsigned long data )␍␊
2578␍␊
2579{␍␊
2580␍␊
2581 //!!! Write an 8-bit ATA register (usually the ATA Data register)␍␊
2582␍␊
2583 outl((unsigned int)pio_reg_addrs[ addr ], data);␍␊
2584}␍␊
2585␍␊
2586//*************************************************************␍␊
2587//␍␊
2588// These functions are normally used to transfer DRQ blocks:␍␊
2589//␍␊
2590// pio_drq_block_in()␍␊
2591// pio_drq_block_out()␍␊
2592//␍␊
2593//*************************************************************␍␊
2594␍␊
2595// Note: pio_drq_block_in() is the primary way perform PIO␍␊
2596// Data In transfers. It will handle 8-bit, 16-bit and 32-bit␍␊
2597// I/O based data transfers.␍␊
2598␍␊
2599static void pio_drq_block_in( unsigned char addrDataReg,␍␊
2600 unsigned char * bufAddr,␍␊
2601 long wordCnt )␍␊
2602␍␊
2603{␍␊
2604␍␊
2605 // NOTE: wordCnt is the size of a DRQ data block/packet␍␊
2606 // in words. The maximum value of wordCnt is normally:␍␊
2607 // a) For ATA, 16384 words or 32768 bytes (64 sectors,␍␊
2608 // only with READ/WRITE MULTIPLE commands),␍␊
2609 // b) For ATAPI, 32768 words or 65536 bytes␍␊
2610 // (actually 65535 bytes plus a pad byte).␍␊
2611␍␊
2612 {␍␊
2613 int pxw;␍␊
2614 long wc;␍␊
2615␍␊
2616 // adjust pio_xfer_width - don't use DWORD if wordCnt is odd.␍␊
2617␍␊
2618 pxw = pio_xfer_width;␍␊
2619 if ( ( pxw == 32 ) && ( wordCnt & 0x00000001L ) )␍␊
2620 pxw = 16;␍␊
2621␍␊
2622 // Data transfer using INS instruction.␍␊
2623 // Break the transfer into chunks of 32768 or fewer bytes.␍␊
2624␍␊
2625 while ( wordCnt > 0 )␍␊
2626 {␍␊
2627 if ( wordCnt > 16384L )␍␊
2628 wc = 16384;␍␊
2629 else␍␊
2630 wc = wordCnt;␍␊
2631 if ( pxw == 8 )␍␊
2632 {␍␊
2633 // do REP INS␍␊
2634 pio_rep_inbyte( addrDataReg, bufAddr, wc * 2L );␍␊
2635 }␍␊
2636 else␍␊
2637 if ( pxw == 32 )␍␊
2638 {␍␊
2639 // do REP INSD␍␊
2640 pio_rep_indword( addrDataReg, bufAddr, wc / 2L );␍␊
2641 }␍␊
2642 else␍␊
2643 {␍␊
2644 // do REP INSW␍␊
2645 pio_rep_inword( addrDataReg, bufAddr, wc );␍␊
2646 }␍␊
2647 bufAddr = bufAddr + ( wc * 2 );␍␊
2648 wordCnt = wordCnt - wc;␍␊
2649 }␍␊
2650 }␍␊
2651␍␊
2652 return;␍␊
2653}␍␊
2654␍␊
2655//*************************************************************␍␊
2656␍␊
2657// Note: pio_drq_block_out() is the primary way perform PIO␍␊
2658// Data Out transfers. It will handle 8-bit, 16-bit and 32-bit␍␊
2659// I/O based data transfers.␍␊
2660␍␊
2661static void pio_drq_block_out( unsigned char addrDataReg,␍␊
2662 unsigned char * bufAddr,␍␊
2663 long wordCnt )␍␊
2664␍␊
2665{␍␊
2666␍␊
2667 // NOTE: wordCnt is the size of a DRQ data block/packet␍␊
2668 // in words. The maximum value of wordCnt is normally:␍␊
2669 // a) For ATA, 16384 words or 32768 bytes (64 sectors,␍␊
2670 // only with READ/WRITE MULTIPLE commands),␍␊
2671 // b) For ATAPI, 32768 words or 65536 bytes␍␊
2672 // (actually 65535 bytes plus a pad byte).␍␊
2673␍␊
2674 {␍␊
2675 int pxw;␍␊
2676 long wc;␍␊
2677␍␊
2678 // adjust pio_xfer_width - don't use DWORD if wordCnt is odd.␍␊
2679␍␊
2680 pxw = pio_xfer_width;␍␊
2681 if ( ( pxw == 32 ) && ( wordCnt & 0x00000001L ) )␍␊
2682 pxw = 16;␍␊
2683␍␊
2684 // Data transfer using OUTS instruction.␍␊
2685 // Break the transfer into chunks of 32768 or fewer bytes.␍␊
2686␍␊
2687 while ( wordCnt > 0 )␍␊
2688 {␍␊
2689 if ( wordCnt > 16384L )␍␊
2690 wc = 16384;␍␊
2691 else␍␊
2692 wc = wordCnt;␍␊
2693 if ( pxw == 8 )␍␊
2694 {␍␊
2695 // do REP OUTS␍␊
2696 pio_rep_outbyte( addrDataReg, bufAddr, wc * 2L );␍␊
2697 }␍␊
2698 else␍␊
2699 if ( pxw == 32 )␍␊
2700 {␍␊
2701 // do REP OUTSD␍␊
2702 pio_rep_outdword( addrDataReg, bufAddr, wc / 2L );␍␊
2703 }␍␊
2704 else␍␊
2705 {␍␊
2706 // do REP OUTSW␍␊
2707 pio_rep_outword( addrDataReg, bufAddr, wc );␍␊
2708 }␍␊
2709 bufAddr = bufAddr + ( wc * 2 );␍␊
2710 wordCnt = wordCnt - wc;␍␊
2711 }␍␊
2712 }␍␊
2713␍␊
2714 return;␍␊
2715}␍␊
2716␍␊
2717//*************************************************************␍␊
2718//␍␊
2719// These functions transfer PIO DRQ data blocks through the ATA␍␊
2720// Data register. On an x86 these functions would use the␍␊
2721// REP INS and REP OUTS instructions.␍␊
2722//␍␊
2723// pio_rep_inbyte()␍␊
2724// pio_rep_outbyte()␍␊
2725// pio_rep_inword()␍␊
2726// pio_rep_outword()␍␊
2727// pio_rep_indword()␍␊
2728// pio_rep_outdword()␍␊
2729//␍␊
2730// These functions can be called directly but usually they␍␊
2731// are called by the pio_drq_block_in() and pio_drq_block_out()␍␊
2732// functions to perform I/O mode transfers. See the␍␊
2733// pio_xfer_width variable!␍␊
2734//␍␊
2735//*************************************************************␍␊
2736␍␊
2737static void pio_rep_inbyte( unsigned char addrDataReg,␍␊
2738 unsigned char * bufAddr,␍␊
2739 long byteCnt )␍␊
2740␍␊
2741{␍␊
2742␍␊
2743 // Warning: Avoid calling this function with␍␊
2744 // byteCnt > 32768 (transfers 32768 bytes).␍␊
2745 // that bufOff is a value between 0 and 15 (0xf).␍␊
2746␍␊
2747 //!!! repeat read an 8-bit register (ATA Data register when␍␊
2748 //!!! ATA status is BSY=0 DRQ=1). For example:␍␊
2749␍␊
2750 while ( byteCnt > 0 )␍␊
2751 {␍␊
2752 * bufAddr = pio_inbyte( addrDataReg );␍␊
2753 bufAddr ++ ;␍␊
2754 byteCnt -- ;␍␊
2755 }␍␊
2756}␍␊
2757␍␊
2758//*************************************************************␍␊
2759␍␊
2760static void pio_rep_outbyte( unsigned char addrDataReg,␍␊
2761 unsigned char * bufAddr,␍␊
2762 long byteCnt )␍␊
2763␍␊
2764{␍␊
2765␍␊
2766 // Warning: Avoid calling this function with␍␊
2767 // byteCnt > 32768 (transfers 32768 bytes).␍␊
2768 // that bufOff is a value between 0 and 15 (0xf).␍␊
2769␍␊
2770 //!!! repeat write an 8-bit register (ATA Data register when␍␊
2771 //!!! ATA status is BSY=0 DRQ=1). For example:␍␊
2772␍␊
2773 while ( byteCnt > 0 )␍␊
2774 {␍␊
2775 pio_outbyte( addrDataReg, * bufAddr );␍␊
2776 bufAddr ++ ;␍␊
2777 byteCnt -- ;␍␊
2778 }␍␊
2779}␍␊
2780␍␊
2781//*************************************************************␍␊
2782␍␊
2783static void pio_rep_inword( unsigned char addrDataReg,␍␊
2784 unsigned char * bufAddr,␍␊
2785 long wordCnt )␍␊
2786␍␊
2787{␍␊
2788␍␊
2789 // Warning: Avoid calling this function with␍␊
2790 // wordCnt > 16384 (transfers 32768 bytes).␍␊
2791␍␊
2792 //!!! repeat read a 16-bit register (ATA Data register when␍␊
2793 //!!! ATA status is BSY=0 DRQ=1). For example:␍␊
2794␍␊
2795 while ( wordCnt > 0 )␍␊
2796 {␍␊
2797 * (unsigned int *) bufAddr = pio_inword( addrDataReg );␍␊
2798 bufAddr += 2;␍␊
2799 wordCnt -- ;␍␊
2800 }␍␊
2801}␍␊
2802␍␊
2803//*************************************************************␍␊
2804␍␊
2805static void pio_rep_outword( unsigned char addrDataReg,␍␊
2806 unsigned char * bufAddr,␍␊
2807 long wordCnt )␍␊
2808␍␊
2809{␍␊
2810␍␊
2811 // Warning: Avoid calling this function with␍␊
2812 // wordCnt > 16384 (transfers 32768 bytes).␍␊
2813␍␊
2814 //!!! repeat write a 16-bit register (ATA Data register when␍␊
2815 //!!! ATA status is BSY=0 DRQ=1). For example:␍␊
2816␍␊
2817 while ( wordCnt > 0 )␍␊
2818 {␍␊
2819 pio_outword( addrDataReg, * (unsigned int *) bufAddr );␍␊
2820 bufAddr += 2;␍␊
2821 wordCnt -- ;␍␊
2822 }␍␊
2823}␍␊
2824␍␊
2825//*************************************************************␍␊
2826␍␊
2827static void pio_rep_indword( unsigned char addrDataReg,␍␊
2828 unsigned char * bufAddr,␍␊
2829 long dwordCnt )␍␊
2830␍␊
2831{␍␊
2832␍␊
2833 // Warning: Avoid calling this function with␍␊
2834 // dwordCnt > 8192 (transfers 32768 bytes).␍␊
2835␍␊
2836 //!!! repeat read a 32-bit register (ATA Data register when␍␊
2837 //!!! ATA status is BSY=0 DRQ=1). For example:␍␊
2838␍␊
2839 while ( dwordCnt > 0 )␍␊
2840 {␍␊
2841 * (unsigned long *) bufAddr = pio_indword( addrDataReg );␍␊
2842 bufAddr += 4;␍␊
2843 dwordCnt -- ;␍␊
2844 }␍␊
2845}␍␊
2846␍␊
2847//*************************************************************␍␊
2848␍␊
2849static void pio_rep_outdword( unsigned char addrDataReg,␍␊
2850 unsigned char * bufAddr,␍␊
2851 long dwordCnt )␍␊
2852␍␊
2853{␍␊
2854␍␊
2855 // Warning: Avoid calling this function with␍␊
2856 // dwordCnt > 8192 (transfers 32768 bytes).␍␊
2857␍␊
2858 //!!! repeat write a 32-bit register (ATA Data register when␍␊
2859 //!!! ATA status is BSY=0 DRQ=1). For example:␍␊
2860␍␊
2861 while ( dwordCnt > 0 )␍␊
2862 {␍␊
2863 pio_outdword( addrDataReg, * (unsigned long *) bufAddr );␍␊
2864 bufAddr += 4;␍␊
2865 dwordCnt -- ;␍␊
2866 }␍␊
2867}␍␊
2868␍␊
2869␍␊
2870//*************************************************************␍␊
2871//␍␊
2872// Command timing functions␍␊
2873//␍␊
2874//**************************************************************␍␊
2875␍␊
2876␍␊
2877//static long tmr_cmd_start_time; // command start time - see the␍␊
2878 // tmr_set_timeout() and␍␊
2879 // tmr_chk_timeout() functions.␍␊
2880␍␊
2881//*************************************************************␍␊
2882//␍␊
2883// tmr_set_timeout() - get the command start time␍␊
2884//␍␊
2885//**************************************************************␍␊
2886␍␊
2887static void tmr_set_timeout( void )␍␊
2888␍␊
2889{␍␊
2890␍␊
2891 // get the command start time␍␊
2892 tmr_cmd_start_time = time18();␍␊
2893}␍␊
2894␍␊
2895//*************************************************************␍␊
2896//␍␊
2897// tmr_chk_timeout() - check for command timeout.␍␊
2898//␍␊
2899// Gives non-zero return if command has timed out.␍␊
2900//␍␊
2901//**************************************************************␍␊
2902␍␊
2903static int tmr_chk_timeout( void )␍␊
2904␍␊
2905{␍␊
2906 long curTime;␍␊
2907␍␊
2908 // get current time␍␊
2909 curTime = time18();␍␊
2910␍␊
2911 // timed out yet ?␍␊
2912 if ( curTime >= ( tmr_cmd_start_time␍␊
2913 + ( TMR_TIME_OUT * SYSTEM_TIMER_TICKS_PER_SECOND ) ) )␍␊
2914 return 1; // yes␍␊
2915␍␊
2916 // no timeout yet␍␊
2917 return 0;␍␊
2918}␍␊
2919␍␊
2920// end mindrvr.c␍␊
2921␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀

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