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Root/branches/meklort/i386/libsaio/resolution.c

Source at commit 519 created 13 years 7 months ago.
By meklort, Moved GraphicsEnabler into a module. Untested
1/*␊
2 * resolution.h␊
3 * ␊
4 *␉NOTE: I don't beleive this code is production ready / should be in trunk␊
5 * Atleast, not in it's current state. ␊
6 *␊
7 * Created by Evan Lojewski on 3/4/10.␊
8 * Copyright 2009. All rights reserved.␊
9 *␊
10 */␊
11#ifndef _RESOLUTION_H_␊
12#define _RESOLUTION_H_␊
13␊
14#include "libsaio.h"␊
15#include "edid.h"␊
16#include "resolution.h"␊
17␊
18␊
19void patchVideoBios()␊
20{␉␉␊
21␉UInt32 x = 0, y = 0, bp = 0;␊
22␉␊
23␉getResolution(&x, &y, &bp);␊
24␉␊
25␉␊
26␉if (x != 0 &&␊
27␉␉y != 0 && ␊
28␉␉bp != 0)␊
29␉{␊
30␉␉vbios_map * map;␊
31␉␉␊
32␉␉map = open_vbios(CT_UNKWN);␊
33␉␉if(map)␊
34␉␉{␊
35␉␉␉unlock_vbios(map);␊
36␉␉␉␊
37␉␉␉set_mode(map, x, y, bp, 0, 0);␊
38␉␉␉␊
39␉␉␉relock_vbios(map);␊
40␉␉␉␊
41␉␉␉close_vbios(map);␊
42␉␉}␊
43␉}␉␉␊
44␉␊
45}␊
46␊
47␊
48/* Copied from 915 resolution created by steve tomljenovic␊
49 *␊
50 * This code is based on the techniques used in :␊
51 *␊
52 * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊
53 * for demonstrating how to shadow the VBIOS into system RAM␊
54 * and then modify it.␊
55 *␊
56 * - 1280patch by Andrew Tipton (andrewtipton null li).␊
57 *␊
58 * - 855resolution by Alain Poirier␊
59 *␊
60 * This source code is into the public domain.␊
61 */␊
62␊
63/**␊
64 **␊
65 **/␊
66␊
67#define CONFIG_MECH_ONE_ADDR␉0xCF8␊
68#define CONFIG_MECH_ONE_DATA␉0xCFC␊
69␊
70int freqs[] = { 60, 75, 85 };␊
71␊
72UInt32 get_chipset_id(void)␊
73{␊
74␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊
75␉return inl(CONFIG_MECH_ONE_DATA);␊
76}␊
77␊
78chipset_type get_chipset(UInt32 id)␊
79{␊
80␉chipset_type type;␊
81␉␉␊
82␉switch (id) {␊
83␉␉case 0x35758086:␊
84␉␉␉type = CT_830;␊
85␉␉␉break;␊
86␉␉␉␊
87␉␉case 0x25608086:␊
88␉␉␉type = CT_845G;␊
89␉␉␉break;␊
90␉␉␉␊
91␉␉case 0x35808086:␊
92␉␉␉type = CT_855GM;␊
93␉␉␉break;␊
94␉␉␉␊
95␉␉case 0x25708086:␊
96␉␉␉type = CT_865G;␊
97␉␉␉break;␊
98␉␉␉␊
99␉␉case 0x25808086:␊
100␉␉␉type = CT_915G;␊
101␉␉␉break;␊
102␉␉␉␊
103␉␉case 0x25908086:␊
104␉␉␉type = CT_915GM;␊
105␉␉␉break;␊
106␉␉␉␊
107␉␉case 0x27708086:␊
108␉␉␉type = CT_945G;␊
109␉␉␉break;␊
110␉␉␉␊
111␉␉case 0x27a08086:␊
112␉␉␉type = CT_945GM;␊
113␉␉␉break;␊
114␉␉␉␊
115␉␉case 0x27ac8086:␊
116␉␉␉type = CT_945GME;␊
117␉␉␉break;␊
118␉␉␉␊
119␉␉case 0x29708086:␊
120␉␉␉type = CT_946GZ;␊
121␉␉␉break;␊
122␉␉␉␊
123␉␉case 0x27748086:␊
124␉␉␉type = CT_955X;␊
125␉␉␉break;␊
126␉␉␉␊
127␉␉case 0x277c8086:␊
128␉␉␉type = CT_975X;␊
129␉␉␉break;␊
130␊
131␉␉case 0x29a08086:␊
132␉␉␉type = CT_G965;␊
133␉␉␉break;␊
134␉␉␉␊
135␉␉case 0x29908086:␊
136␉␉␉type = CT_Q965;␊
137␉␉␉break;␊
138␉␉␉␊
139␉␉case 0x81008086:␊
140␉␉␉type = CT_500;␊
141␉␉␉break;␊
142␉␉␉␊
143␉␉case 0x2e108086:␊
144␉␉case 0X2e908086:␊
145␉␉␉type = CT_B43;␊
146␉␉␉break;␊
147␊
148␉␉case 0x2e208086:␊
149␉␉␉type = CT_P45;␊
150␉␉␉break;␊
151␊
152␉␉case 0x2e308086:␊
153␉␉␉type = CT_G41;␊
154␉␉␉break;␊
155␉␉␉␉␉␊
156␉␉case 0x29c08086:␊
157␉␉␉type = CT_G31;␊
158␉␉␉break;␊
159␉␉␉␊
160␉␉case 0x29208086:␊
161␉␉␉type = CT_G45;␊
162␉␉␉break;␊
163␉␉␉␊
164␉␉case 0xA0108086:␊
165␉␉␉type = CT_3150;␊
166␉␉␉break;␊
167␉␉␉␊
168␉␉case 0x2a008086:␊
169␉␉␉type = CT_965GM;␊
170␉␉␉break;␊
171␉␉␉␊
172␉␉case 0x29e08086:␊
173␉␉␉type = CT_X48;␊
174␉␉␉break;␉␉␉␊
175␉␉␉␉␊
176␉␉case 0x2a408086:␊
177␉␉␉type = CT_GM45;␊
178␉␉␉break;␊
179␉␉␉␊
180␉␉␉␊
181␉␉default:␊
182␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊
183␉␉␉{␊
184␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊
185␉␉␉␉//getc();␊
186␉␉␉␉type = CT_UNKWN_INTEL;␊
187␊
188␉␉␉}␊
189␉␉␉type = CT_UNKWN;␊
190␉␉␉break;␊
191␉}␊
192␉return type;␊
193}␊
194␊
195vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊
196{␊
197␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊
198␉return ptr;␊
199}␊
200␊
201vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊
202{␊
203␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊
204␉return ptr;␊
205}␊
206␊
207vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊
208{␊
209␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊
210␉return ptr;␊
211}␊
212␊
213char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊
214{␊
215␉UInt32 i;␊
216␉UInt16 r1, r2;␊
217␉␊
218␉r1 = r2 = 32000;␊
219␉␊
220␉for (i=0; i < map->mode_table_size; i++)␊
221␉{␊
222␉␉if (map->mode_table[i].resolution <= r1)␊
223␉␉{␊
224␉␉␉r1 = map->mode_table[i].resolution;␊
225␉␉}␊
226␉␉else␊
227␉␉{␊
228␉␉␉if (map->mode_table[i].resolution <= r2)␊
229␉␉␉{␊
230␉␉␉␉r2 = map->mode_table[i].resolution;␊
231␉␉␉}␊
232␉␉}␊
233␉␉␊
234␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊
235␉}␊
236␉␊
237␉return (r2-r1-6) % entry_size == 0;␊
238}␊
239␊
240void close_vbios(vbios_map * map);␊
241␊
242char detect_ati_bios_type(vbios_map * map)␊
243{␉␊
244␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊
245}␊
246␊
247␊
248vbios_map * open_vbios(chipset_type forced_chipset)␊
249{␊
250␉UInt32 z;␊
251␉vbios_map * map = malloc(sizeof(vbios_map));␊
252␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊
253␉/*␊
254␉ * Determine chipset␊
255␉ */␊
256␉␊
257␉if (forced_chipset == CT_UNKWN)␊
258␉{␊
259␉␉map->chipset_id = get_chipset_id();␊
260␉␉map->chipset = get_chipset(map->chipset_id);␊
261␉}␊
262␉else if (forced_chipset != CT_UNKWN)␊
263␉{␊
264␉␉map->chipset = forced_chipset;␊
265␉}␊
266␉␊
267␉␊
268␉if (map->chipset == CT_UNKWN)␊
269␉{␊
270␉␉//verbose("Unknown chipset type.\n");␊
271␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊
272␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊
273␉␉close_vbios(map);␊
274␉␉return 0;␊
275␉}␊
276␉␊
277␉␊
278␉/*␊
279␉ * Map the video bios to memory␊
280␉ */␊
281␉map->bios_ptr=(char*)VBIOS_START;␊
282␉␊
283␉/*␊
284␉ * check if we have ATI Radeon␊
285␉ */␊
286␉map->ati_tables.base = map->bios_ptr;␊
287␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊
288␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊
289␉{␊
290␉␉// ATI Radeon Card␊
291␉␉map->bios = BT_ATI_1;␊
292␉␉␊
293␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊
294␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊
295␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊
296␉␉␊
297␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊
298␉␉if (map->ati_mode_table == 0)␊
299␉␉{␊
300␉␉␉printf("Unable to locate the mode table.\n");␊
301␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
302␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
303␉␉␉printf("Chipset: %d\n", map->chipset);␊
304␉␉␉close_vbios(map);␊
305␉␉␉return 0;␊
306␉␉}␊
307␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊
308␉␉␊
309␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊
310␉␉␊
311␉}␊
312␉else {␊
313␉␉␊
314␉␉/*␊
315␉␉ * check if we have NVIDIA␊
316␉␉ */␊
317␊
318␉␉int i = 0;␊
319␉␉while (i < 512)␊
320␉␉{ // we don't need to look through the whole bios, just the firs 512 bytes␊
321␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊
322␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊
323␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊
324␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊
325␉␉␉{␊
326␉␉␉␉map->bios = BT_NVDA;␊
327␉␉␉␉unsigned short nv_data_table_offset = 0;␊
328␉␉␉␉unsigned short * nv_data_table;␊
329␉␉␉␉NV_VESA_TABLE * std_vesa;␊
330␉␉␉␉␊
331␉␉␉␉int i = 0;␊
332␉␉␉␉␊
333␉␉␉␉while (i < 0x300)␊
334␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊
335␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊
336␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊
337␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊
338␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊
339␉␉␉␉␉{␊
340␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊
341␉␉␉␉␉␉break;␊
342␉␉␉␉␉}␊
343␉␉␉␉␉i++;␊
344␉␉␉␉}␊
345␉␉␉␉␊
346␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊
347␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊
348␉␉␉␉␊
349␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊
350␉␉␉␉if (map->nv_mode_table == 0)␊
351␉␉␉␉{␊
352␉␉␉␉␉printf("Unable to locate the mode table.\n");␊
353␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
354␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
355␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊
356␉␉␉␉␉close_vbios(map);␊
357␉␉␉␉␉return 0;␊
358␉␉␉␉}␊
359␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊
360␉␉␉␉␊
361␉␉␉␉break;␊
362␉␉␉}␊
363␉␉␉i++;␊
364␉␉}␊
365␉}␊
366␉␊
367␉␊
368␉/*␊
369␉ * check if we have Intel␊
370␉ */␊
371␉␊
372␉/*if (map->chipset == CT_UNKWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊
373␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊
374␉ ␊
375␉ printf("Chipset Id: %x\n", map->chipset_id);␊
376␉ ␊
377␉ printf("Please report this problem to stomljen@yahoo.com\n");␊
378␉ ␊
379␉ close_vbios(map);␊
380␉ return 0;␊
381␉ }*/␊
382␉␊
383␉/*␊
384␉ * check for others␊
385␉ */␊
386␉␊
387␊
388␉␊
389␉/*␊
390␉ * Figure out where the mode table is ␊
391␉ */␊
392␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊
393␉{␊
394␉␉char* p = map->bios_ptr + 16;␊
395␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊
396␉␉␊
397␉␉while (p < limit && map->mode_table == 0)␊
398␉␉{␊
399␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊
400␉␉␉␊
401␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊
402␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊
403␉␉␉{␊
404␉␉␉␉map->mode_table = mode_ptr;␊
405␉␉␉}␊
406␉␉␉␊
407␉␉␉p++;␊
408␉␉}␊
409␉␉␊
410␉␉if (map->mode_table == 0) ␊
411␉␉{␊
412␉␉␉close_vbios(map);␊
413␉␉␉return 0;␊
414␉␉}␊
415␉}␊
416␉␊
417␉␊
418␉/*␊
419␉ * Determine size of mode table␊
420␉ */␊
421␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
422␉{␊
423␉␉vbios_mode * mode_ptr = map->mode_table;␊
424␉␉␊
425␉␉while (mode_ptr->mode != 0xff)␊
426␉␉{␊
427␉␉␉map->mode_table_size++;␊
428␉␉␉mode_ptr++;␊
429␉␉}␊
430␉}␊
431␉␊
432␉/*␊
433␉ * Figure out what type of bios we have␊
434␉ * order of detection is important␊
435␉ */␊
436␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
437␉{␊
438␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊
439␉␉{␊
440␉␉␉map->bios = BT_3;␊
441␉␉}␊
442␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊
443␉␉{␊
444␉␉␉map->bios = BT_2;␊
445␉␉}␊
446␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊
447␉␉{␊
448␉␉␉map->bios = BT_1;␊
449␉␉}␊
450␉␉else {␊
451␉␉␉return 0;␊
452␉␉}␊
453␉}␊
454␉␊
455␉return map;␊
456}␊
457␊
458void close_vbios(vbios_map * map)␊
459{␊
460␉free(map);␊
461}␊
462␊
463void unlock_vbios(vbios_map * map)␊
464{␊
465␉␊
466␉map->unlocked = TRUE;␊
467␊
468␉switch (map->chipset) {␊
469␉␉case CT_UNKWN:␊
470␉␉␉break;␊
471␉␉case CT_830:␊
472␉␉case CT_855GM:␊
473␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
474␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊
475␉␉␉␊
476␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
477␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
478␉␉␉break;␊
479␉␉case CT_845G:␊
480␉␉case CT_865G:␊
481␉␉case CT_915G:␊
482␉␉case CT_915GM:␊
483␉␉case CT_945G:␊
484␉␉case CT_945GM:␊
485␉␉case CT_945GME:␊
486␉␉case CT_946GZ:␊
487␉␉case CT_G965:␊
488␉␉case CT_Q965:␊
489␉␉case CT_965GM:␊
490␉␉case CT_975X:␊
491␉␉case CT_P35:␊
492␉␉case CT_955X:␊
493␉␉case CT_X48:␊
494␉␉case CT_B43:␊
495␉␉case CT_Q45:␊
496␉␉case CT_P45:␊
497␉␉case CT_GM45:␊
498␉␉case CT_G45:␊
499␉␉case CT_G41:␊
500␉␉case CT_G31:␊
501␉␉case CT_500:␊
502␉␉case CT_3150:␊
503␉␉case CT_UNKWN_INTEL:␉// Assume newer intel chipset is the same as before␊
504␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
505␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊
506␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊
507␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
508␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊
509␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
510␉␉␉break;␊
511␉}␊
512␉␊
513#if DEBUG␊
514␉{␊
515␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
516␉␉verbose("unlock PAM: (0x%08x)\n", t);␊
517␉}␊
518#endif␊
519}␊
520␊
521void relock_vbios(vbios_map * map)␊
522{␊
523␉␊
524␉map->unlocked = FALSE;␊
525␉␊
526␉switch (map->chipset)␊
527␉{␊
528␉␉case CT_UNKWN:␊
529␉␉␉break;␊
530␉␉case CT_830:␊
531␉␉case CT_855GM:␊
532␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
533␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊
534␉␉␉break;␊
535␉␉case CT_845G:␊
536␉␉case CT_865G:␊
537␉␉case CT_915G:␊
538␉␉case CT_915GM:␊
539␉␉case CT_945G:␊
540␉␉case CT_945GM:␊
541␉␉case CT_945GME:␊
542␉␉case CT_946GZ:␊
543␉␉case CT_G965:␊
544␉␉case CT_955X:␊
545␉␉case CT_G45:␊
546␉␉case CT_Q965:␊
547␉␉case CT_965GM:␊
548␉␉case CT_975X:␊
549␉␉case CT_P35:␊
550␉␉case CT_X48:␊
551␉␉case CT_B43:␊
552␉␉case CT_Q45:␊
553␉␉case CT_P45:␊
554␉␉case CT_GM45:␊
555␉␉case CT_G41:␊
556␉␉case CT_G31:␊
557␉␉case CT_500:␊
558␉␉case CT_3150:␊
559␉␉case CT_UNKWN_INTEL:␊
560␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
561␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊
562␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊
563␉␉␉break;␊
564␉}␊
565␉␊
566#if DEBUG␊
567␉{␊
568 UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
569␉␉verbose("relock PAM: (0x%08x)\n", t);␊
570␉}␊
571#endif␊
572}␊
573␊
574␊
575int getMode(edid_mode *mode)␊
576{␊
577␉char* edidInfo = readEDID();␊
578␉␉␉␊
579␉if(!edidInfo) return 1;␊
580␉␉␊
581␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊
582␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊
583␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊
584␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊
585␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊
586␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊
587␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊
588␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊
589␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊
590␉␉␊
591␉␉␊
592␉free( edidInfo );␊
593␉␉␊
594␉if(!mode->h_active) return 1;␊
595␉␊
596␉return 0;␊
597␉␉␊
598}␊
599␊
600␊
601static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊
602␉␉␉␉␉␉unsigned long *clock,␊
603␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊
604␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊
605{␊
606␉UInt32 hbl, vbl, vfreq;␊
607␉␊
608␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊
609␉vfreq = vbl * freq;␊
610␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊
611␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊
612␉␊
613␉*vsyncstart = y;␊
614␉*vsyncend = y + 3;␊
615␉*vblank = vbl - 1;␊
616␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊
617␉*hsyncend = x + hbl / 2 - 1;␊
618␉*hblank = x + hbl - 1;␊
619␉*clock = (x + hbl) * vfreq / 1000;␊
620}␊
621␊
622void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊
623␉UInt32 xprev, yprev;␊
624␉UInt32 i = 0, j;␊
625␉// patch first available mode␊
626␉␊
627␉//␉for (i=0; i < map->mode_table_size; i++) {␊
628␉//␉␉if (map->mode_table[0].mode == mode) {␊
629␉switch(map->bios) {␊
630␉␉case BT_1:␊
631␉␉{␊
632␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊
633␉␉␉␊
634␉␉␉if (bp) {␊
635␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊
636␉␉␉}␊
637␉␉␉␊
638␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊
639␉␉␉res->x1 = (x & 0xff);␊
640␉␉␉␊
641␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊
642␉␉␉res->y1 = (y & 0xff);␊
643␉␉␉if (htotal)␊
644␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊
645␉␉␉␊
646␉␉␉if (vtotal)␊
647␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊
648␉␉␉␊
649␉␉␉break;␊
650␉␉}␊
651␉␉case BT_2:␊
652␉␉{␊
653␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊
654␉␉␉␊
655␉␉␉res->xchars = x / 8;␊
656␉␉␉res->ychars = y / 16 - 1;␊
657␉␉␉xprev = res->modelines[0].x1;␊
658␉␉␉yprev = res->modelines[0].y1;␊
659␉␉␉␊
660␉␉␉for(j=0; j < 3; j++) {␊
661␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊
662␉␉␉␉␊
663␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
664␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
665␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
666␉␉␉␉␉␊
667␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
668␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
669␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
670␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
671␉␉␉␉␉␊
672␉␉␉␉␉if (htotal)␊
673␉␉␉␉␉␉modeline->htotal = htotal;␊
674␉␉␉␉␉else␊
675␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
676␉␉␉␉␉␊
677␉␉␉␉␉if (vtotal)␊
678␉␉␉␉␉␉modeline->vtotal = vtotal;␊
679␉␉␉␉␉else␊
680␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
681␉␉␉␉}␊
682␉␉␉}␊
683␉␉␉break;␊
684␉␉}␊
685␉␉case BT_3:␊
686␉␉{␊
687␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊
688␉␉␉␊
689␉␉␉xprev = res->modelines[0].x1;␊
690␉␉␉yprev = res->modelines[0].y1;␊
691␉␉␉␊
692␉␉␉for (j=0; j < 3; j++) {␊
693␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊
694␉␉␉␉␊
695␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
696␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
697␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
698␉␉␉␉␉␊
699␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
700␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
701␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
702␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
703␉␉␉␉␉if (htotal)␊
704␉␉␉␉␉␉modeline->htotal = htotal;␊
705␉␉␉␉␉else␊
706␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
707␉␉␉␉␉if (vtotal)␊
708␉␉␉␉␉␉modeline->vtotal = vtotal;␊
709␉␉␉␉␉else␊
710␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
711␉␉␉␉␉␊
712␉␉␉␉␉modeline->timing_h = y-1;␊
713␉␉␉␉␉modeline->timing_v = x-1;␊
714␉␉␉␉}␊
715␉␉␉}␊
716␉␉␉break;␊
717␉␉}␊
718␉␉case BT_ATI_1:␊
719␉␉{␊
720␉␉␉edid_mode mode;␊
721␉␉␉␉␊
722␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊
723␊
724␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊
725␉␉␉if (!getMode(&mode)) {␊
726␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊
727␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊
728␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊
729␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊
730␉␉␉␉␉␊
731␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊
732␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊
733␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊
734␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊
735␊
736␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊
737␉␉␉}␊
738␉␉␉/*else␊
739␉␉␉{␊
740␉␉␉␉vbios_modeline_type2 modeline;␊
741␊
742␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
743␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
744␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
745␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
746␊
747␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊
748␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊
749␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊
750␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
751␊
752␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊
753␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊
754␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊
755␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊
756␉␉␉␉␉␉␉␉␉␉␉␉␊
757␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊
758␉␉␉ }*/␊
759␉␊
760␉␉␉break;␊
761␉␉}␊
762␉␉case BT_ATI_2:␊
763␉␉{␊
764␉␉␉edid_mode mode;␊
765␉␉␉␉␉␉␊
766␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊
767␉␉␉␊
768␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
769␉␉␉if (!getMode(&mode)) {␊
770␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊
771␉␉␉␉mode_timing->usHActive = mode.h_active;␊
772␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊
773␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊
774␉␉␉␉␉␉␉␉␉␉␊
775␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊
776␉␉␉␉mode_timing->usVActive = mode.v_active;␊
777␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊
778␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊
779␉␉␉␉␉␉␉␉␉␉␊
780␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊
781␉␉␉}␊
782␉␉␉/*else␊
783␉␉␉{␊
784␉␉␉␉vbios_modeline_type2 modeline;␊
785␉␉␉␊
786␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
787␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
788␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
789␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
790␉␉␉␉␉␉␉␉␉␉␉␊
791␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊
792␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊
793␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊
794␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
795␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
796␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊
797␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊
798␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊
799␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
800␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
801␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊
802␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊
803␉␉␉␉␊
804␉␉␉␊
805␉␉␉break;␊
806␉␉}␊
807␉␉case BT_NVDA:␊
808␉␉{␊
809␉␉␉edid_mode mode;␊
810␉␉␉␊
811␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊
812␉␉␉␊
813␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
814␉␉␉if (!getMode(&mode)) {␊
815␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊
816␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊
817␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊
818␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊
819␉␉␉␉␊
820␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊
821␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊
822␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊
823␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊
824␉␉␉␉␊
825␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊
826␉␉␉}␊
827␉␉␉/*else␊
828␉␉␉ {␊
829␉␉␉ vbios_modeline_type2 modeline;␊
830␉␉␉ ␊
831␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊
832␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊
833␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊
834␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊
835␉␉␉ ␊
836␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊
837␉␉␉ mode_timing[i].usH_Active = x;␊
838␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊
839␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊
840␉␉␉ ␊
841␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊
842␉␉␉ mode_timing[i].usV_Active = y;␊
843␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊
844␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊
845␉␉␉ ␊
846␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊
847␉␉␉ }*/␊
848␉␉␉break;␊
849␉␉}␊
850␉␉case BT_UNKWN:␊
851␉␉{␊
852␉␉␉break;␊
853␉␉}␊
854␉}␊
855␉//␉␉}␊
856␉//␉}␊
857}␊
858␊
859#endif // _RESOLUTION_H_

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