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Root/branches/meklort/i386/modules/HPET/HPET.c

Source at commit 543 created 13 years 6 months ago.
By meklort, Chameleon code shrinkage. Also moved a few things to modules.
1/*␊
2 * Copyright (c) 2009 Evan Lojewski. All rights reserved.␊
3 *␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "modules.h"␊
8#include "boot.h"␊
9#include "bootstruct.h"␊
10#include "pci.h"␊
11#include "hpet.h"␊
12␊
13#ifndef DEBUG_HPET␊
14#define DEBUG_HPET 0␊
15#endif␊
16␊
17#if DEBUG_HPET␊
18#define DBG(x...) printf(x)␊
19#else␊
20#define DBG(x...)␊
21#endif␊
22␊
23void force_enable_hpet_intel(pci_dt_t *lpc_dev);␊
24void force_enable_hpet_via(pci_dt_t *lpc_dev);␊
25␊
26␊
27void HPET_hook(void* arg1, void* arg2, void* arg3, void* arg4)␊
28{␊
29␉pci_dt_t* current = arg1;␊
30␉␊
31␉if(current->class_id != PCI_CLASS_BRIDGE_ISA) return;␊
32␉␊
33␉␊
34␉bool do_enable_hpet = false;␊
35␉getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->bootConfig);␊
36␊
37␉if (do_enable_hpet)␊
38␉␉force_enable_hpet(current);␊
39}␊
40␊
41void HPET_start()␊
42{␊
43␉register_hook_callback("PCIDevice", &HPET_hook);␊
44}␊
45␊
46/*␊
47 * Force HPET enabled␊
48 *␊
49 * via fix from http://forum.voodooprojects.org/index.php/topic,1596.0.html␊
50 */␊
51␊
52static struct lpc_controller_t lpc_controllers_intel[] = {␊
53␉␊
54␉// Default unknown chipset␊
55␉{ 0, 0, "" },␊
56␉␊
57␉// Intel␊
58␉{ 0x8086, 0x24dc, "ICH5" },␊
59␉{ 0x8086, 0x2640, "ICH6" },␊
60␉{ 0x8086, 0x2641, "ICH6M" },␊
61␉␊
62␉{ 0x8086, 0x27b0, "ICH7 DH" },␊
63␉{ 0x8086, 0x27b8, "ICH7" },␊
64␉{ 0x8086, 0x27b9, "ICH7M" },␊
65␉{ 0x8086, 0x27bd, "ICH7M DH" },␊
66␉␊
67␉{ 0x8086, 0x2810, "ICH8R" },␊
68␉{ 0x8086, 0x2811, "ICH8M-E" },␊
69␉{ 0x8086, 0x2812, "ICH8DH" },␊
70␉{ 0x8086, 0x2814, "ICH8DO" },␊
71␉{ 0x8086, 0x2815, "ICH8M" },␊
72␉␊
73␉{ 0x8086, 0x2912, "ICH9DH" },␊
74␉{ 0x8086, 0x2914, "ICH9DO" },␊
75␉{ 0x8086, 0x2916, "ICH9R" },␊
76␉{ 0x8086, 0x2917, "ICH9M-E" },␊
77␉{ 0x8086, 0x2918, "ICH9" },␊
78␉{ 0x8086, 0x2919, "ICH9M" },␊
79␉␊
80␉{ 0x8086, 0x3a14, "ICH10DO" },␊
81␉{ 0x8086, 0x3a16, "ICH10R" },␊
82␉{ 0x8086, 0x3a18, "ICH10" },␊
83␉{ 0x8086, 0x3a1a, "ICH10D" },␊
84};␊
85␊
86static struct lpc_controller_t lpc_controllers_via[] = {␊
87␉// Default unknown chipset␊
88␉{ 0, 0, "" },␊
89␉␊
90␉{ 0x1106, 0x3372, "VT8237S" },␊
91};␊
92␊
93␊
94void force_enable_hpet(pci_dt_t *lpc_dev)␊
95{␊
96␉switch(lpc_dev->vendor_id)␊
97␉{␊
98␉␉case 0x8086:␊
99␉␉␉force_enable_hpet_intel(lpc_dev);␊
100␉␉␉break;␊
101␉␉␉␊
102␉␉case 0x1106:␊
103␉␉␉force_enable_hpet_via(lpc_dev);␊
104␉␉␉break;␊
105␉}␊
106␉␊
107␉␊
108#if DEBUG_HPET␊
109␉printf("Press [Enter] to continue...\n");␊
110␉getc();␊
111#endif␊
112}␊
113␊
114void force_enable_hpet_via(pci_dt_t *lpc_dev)␊
115{␊
116␉uint32_t␉val, hpet_address = 0xFED00000;␊
117␉int i;␊
118␉␊
119␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊
120␉for(i = 1; i < sizeof(lpc_controllers_via) / sizeof(lpc_controllers_via[0]); i++)␊
121␉{␊
122␉␉if (␉(lpc_controllers_via[i].vendor == lpc_dev->vendor_id) ␊
123␉␉␉&& (lpc_controllers_via[i].device == lpc_dev->device_id))␊
124␉␉{␉␊
125␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊
126␉␉␉␊
127␉␉␉DBG("VIA %s LPC Interface [%04x:%04x], MMIO\n", ␊
128␉␉␉␉lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id);␊
129␉␉␉␊
130␉␉␉if (val & 0x80) {␊
131␉␉␉␉hpet_address = (val & ~0x3ff);␊
132␉␉␉␉DBG("HPET at 0x%lx\n", hpet_address);␊
133␉␉␉}␊
134␉␉␉else ␊
135␉␉␉{␊
136␉␉␉␉val = 0xfed00000 | 0x80;␊
137␉␉␉␉pci_config_write32(lpc_dev->dev.addr, 0x68, val);␊
138␉␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊
139␉␉␉␉if (val & 0x80) {␊
140␉␉␉␉␉hpet_address = (val & ~0x3ff);␊
141␉␉␉␉␉DBG("Force enabled HPET at 0x%lx\n", hpet_address);␊
142␉␉␉␉}␊
143␉␉␉␉else {␊
144␉␉␉␉␉DBG("Unable to enable HPET");␊
145␉␉␉␉}␊
146␉␉␉}␊
147␉␉}␊
148␉}␊
149}␊
150␊
151␊
152␊
153void force_enable_hpet_intel(pci_dt_t *lpc_dev)␊
154{␊
155␉uint32_t␉val, hpet_address = 0xFED00000;␊
156␉int i;␊
157␉void␉␉*rcba;␊
158␉␊
159␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊
160␉for(i = 1; i < sizeof(lpc_controllers_intel) / sizeof(lpc_controllers_intel[0]); i++)␊
161␉{␊
162␉␉if (␉(lpc_controllers_intel[i].vendor == lpc_dev->vendor_id) ␊
163␉␉␉&& (lpc_controllers_intel[i].device == lpc_dev->device_id))␊
164␉␉{␉␊
165␉␉␉␊
166␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊
167␉␉␉␊
168␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊
169␉␉␉␉lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊
170␉␉␉␊
171␉␉␉if (rcba == 0)␊
172␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊
173␉␉␉else␊
174␉␉␉{␊
175␉␉␉␉val = REG32(rcba, 0x3404);␊
176␉␉␉␉if (val & 0x80)␊
177␉␉␉␉{␊
178␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊
179␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊
180␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
181␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊
182␉␉␉␉}␊
183␉␉␉␉else␊
184␉␉␉␉{␊
185␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊
186␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊
187␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊
188␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
189␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊
190␉␉␉␉}␊
191␉␉␉␉␊
192␉␉␉␉// verify if the job is done␊
193␉␉␉␉val = REG32(rcba, 0x3404);␊
194␉␉␉␉if (!(val & 0x80))␊
195␉␉␉␉␉printf(" Failed to force enable HPET\n");␊
196␉␉␉}␊
197␉␉␉break;␊
198␉␉␉␊
199␉␉}␊
200␉}␊
201}

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