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Source at commit 546 created 13 years 7 months ago.
By meklort, More code shrinkage
1/*
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>
3 * AsereBLN: 2009: cleanup and bugfix
4 */
5
6#include "libsaio.h"
7#include "platform.h"
8#include "cpu.h"
9
10#ifndef DEBUG_CPU
11#define DEBUG_CPU 0
12#endif
13
14#if DEBUG_CPU
15#define DBG(x...)printf(x)
16#else
17#define DBG(x...)msglog(x)
18#endif
19
20/*
21 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer
22 */
23static uint64_t measure_tsc_frequency(void)
24{
25 uint64_t tscStart;
26 uint64_t tscEnd;
27 uint64_t tscDelta = 0xffffffffffffffffULL;
28 unsigned long pollCount;
29 uint64_t retval = 0;
30 int i;
31
32 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT
33 * counter 2. We run this loop 3 times to make sure the cache
34 * is hot and we take the minimum delta from all of the runs.
35 * That is to say that we're biased towards measuring the minimum
36 * number of TSC ticks that occur while waiting for the timer to
37 * expire. That theoretically helps avoid inconsistencies when
38 * running under a VM if the TSC is not virtualized and the host
39 * steals time. The TSC is normally virtualized for VMware.
40 */
41 for(i = 0; i < 10; ++i)
42 {
43 enable_PIT2();
44 set_PIT2_mode0(CALIBRATE_LATCH);
45 tscStart = rdtsc64();
46 pollCount = poll_PIT2_gate();
47 tscEnd = rdtsc64();
48 /* The poll loop must have run at least a few times for accuracy */
49 if(pollCount <= 1)
50 continue;
51 /* The TSC must increment at LEAST once every millisecond. We
52 * should have waited exactly 30 msec so the TSC delta should
53 * be >= 30. Anything less and the processor is way too slow.
54 */
55 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)
56 continue;
57 // tscDelta = min(tscDelta, (tscEnd - tscStart))
58 if( (tscEnd - tscStart) < tscDelta )
59 tscDelta = tscEnd - tscStart;
60 }
61 /* tscDelta is now the least number of TSC ticks the processor made in
62 * a timespan of 0.03 s (e.g. 30 milliseconds)
63 * Linux thus divides by 30 which gives the answer in kiloHertz because
64 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses
65 * Hz so we need to convert our milliseconds to seconds. Since we're
66 * dividing by the milliseconds, we simply multiply by 1000.
67 */
68
69 /* Unlike linux, we're not limited to 32-bit, but we do need to take care
70 * that we're going to multiply by 1000 first so we do need at least some
71 * arithmetic headroom. For now, 32-bit should be enough.
72 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.
73 */
74 if(tscDelta > (1ULL<<32))
75 retval = 0;
76 else
77 {
78 retval = tscDelta * 1000 / 30;
79 }
80 disable_PIT2();
81 return retval;
82}
83
84/*
85 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU
86 * - multi. is read from a specific MSR. In the case of Intel, there is:
87 * a max multi. (used to calculate the FSB freq.),
88 * and a current multi. (used to calculate the CPU freq.)
89 * - fsbFrequency = tscFrequency / multi
90 * - cpuFrequency = fsbFrequency * multi
91 */
92
93void scan_cpu(PlatformInfo_t *p)
94{
95int i = 0;
96uint64_ttscFrequency, fsbFrequency, cpuFrequency;
97uint64_tmsr, flex_ratio;
98uint8_tmaxcoef, maxdiv, currcoef, currdiv;
99
100maxcoef = maxdiv = currcoef = currdiv = 0;
101
102/* get cpuid values */
103for( ; i < 3; i++)
104{
105do_cpuid(i, p->CPU.CPUID[i]);
106}
107
108do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);
109do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);
110if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {
111do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);
112}
113#if DEBUG_CPU
114{
115inti;
116printf("CPUID Raw Values:\n");
117for (i=0; i<CPUID_MAX; i++) {
118printf("%02d: %08x-%08x-%08x-%08x\n", i,
119p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],
120p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);
121}
122}
123#endif
124p->CPU.Vendor= p->CPU.CPUID[CPUID_0][1];
125p->CPU.Signature= p->CPU.CPUID[CPUID_1][0];
126p->CPU.Stepping= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);
127p->CPU.Model= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);
128p->CPU.Family= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);
129p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);
130p->CPU.ExtFamily= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);
131p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
132p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
133
134p->CPU.Model += (p->CPU.ExtModel << 4);
135
136/* get brand string (if supported) */
137/* Copyright: from Apple's XNU cpuid.c */
138if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {
139uint32_treg[4];
140 char str[128], *s;
141/*
142 * The brand string 48 bytes (max), guaranteed to
143 * be NUL terminated.
144 */
145do_cpuid(0x80000002, reg);
146bcopy((char *)reg, &str[0], 16);
147do_cpuid(0x80000003, reg);
148bcopy((char *)reg, &str[16], 16);
149do_cpuid(0x80000004, reg);
150bcopy((char *)reg, &str[32], 16);
151for (s = str; *s != '\0'; s++) {
152if (*s != ' ') break;
153}
154
155strlcpy(p->CPU.BrandString,s, sizeof(p->CPU.BrandString));
156
157if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {
158 /*
159 * This string means we have a firmware-programmable brand string,
160 * and the firmware couldn't figure out what sort of CPU we have.
161 */
162 p->CPU.BrandString[0] = '\0';
163 }
164}
165
166/* setup features */
167p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR) & p->CPU.CPUID[CPUID_1][3];
168p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42) & p->CPU.CPUID[CPUID_1][2];
169p->CPU.Features |= (CPU_FEATURE_EM64T) & p->CPU.CPUID[CPUID_81][3];
170
171
172//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {
173if (p->CPU.NoThreads > p->CPU.NoCores) {
174p->CPU.Features |= CPU_FEATURE_HTT;
175}
176
177
178tscFrequency = measure_tsc_frequency();
179fsbFrequency = 0;
180cpuFrequency = 0;
181
182if ((p->CPU.Vendor == 0x756E6547 /* Intel */) &&
183((p->CPU.Family == 0x06) ||
184 (p->CPU.Family == 0x0f)))
185{
186if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) ||
187(p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))
188{
189/* Nehalem CPU model */
190if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e ||
191 p->CPU.Model == 0x1f || p->CPU.Model == 0x25 ||
192 p->CPU.Model == 0x2c))
193{
194msr = rdmsr64(MSR_PLATFORM_INFO);
195DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);
196currcoef = (msr >> 8) & 0xff;
197msr = rdmsr64(MSR_FLEX_RATIO);
198DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);
199if ((msr >> 16) & 0x01)
200{
201flex_ratio = (msr >> 8) & 0xff;
202if (currcoef > flex_ratio)
203{
204currcoef = flex_ratio;
205}
206}
207
208if (currcoef) {
209fsbFrequency = (tscFrequency / currcoef);
210}
211cpuFrequency = tscFrequency;
212}
213else
214{
215msr = rdmsr64(MSR_IA32_PERF_STATUS);
216DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);
217currcoef = (msr >> 8) & 0x1f;
218/* Non-integer bus ratio for the max-multi*/
219maxdiv = (msr >> 46) & 0x01;
220/* Non-integer bus ratio for the current-multi (undocumented)*/
221currdiv = (msr >> 14) & 0x01;
222
223if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) ||
224(p->CPU.Family == 0x0f)) // This will always be model >= 3
225{
226/* On these models, maxcoef defines TSC freq */
227maxcoef = (msr >> 40) & 0x1f;
228}
229else
230{
231/* On lower models, currcoef defines TSC freq */
232/* XXX */
233maxcoef = currcoef;
234}
235
236if (maxcoef)
237{
238if (maxdiv)
239{
240fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));
241}
242else
243{
244fsbFrequency = (tscFrequency / maxcoef);
245}
246
247if (currdiv)
248{
249cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);
250}
251else
252{
253cpuFrequency = (fsbFrequency * currcoef);
254}
255DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");
256}
257}
258}
259/* Mobile CPU ? */
260if (rdmsr64(0x17) & (1<<28))
261{
262p->CPU.Features |= CPU_FEATURE_MOBILE;
263}
264}
265#if 0
266else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f))
267{
268if(p->CPU.ExtFamily == 0x00 /* K8 */)
269{
270msr = rdmsr64(K8_FIDVID_STATUS);
271currcoef = (msr & 0x3f) / 2 + 4;
272currdiv = (msr & 0x01) * 2;
273}
274else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)
275{
276msr = rdmsr64(K10_COFVID_STATUS);
277if(p->CPU.ExtFamily == 0x01 /* K10 */)
278currcoef = (msr & 0x3f) + 0x10;
279else /* K11+ */
280currcoef = (msr & 0x3f) + 0x08;
281currdiv = (2 << ((msr >> 6) & 0x07));
282}
283
284if (currcoef)
285{
286if (currdiv)
287{
288fsbFrequency = ((tscFrequency * currdiv) / currcoef);
289DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);
290}
291else
292{
293fsbFrequency = (tscFrequency / currcoef);
294DBG("%d\n", currcoef);
295}
296fsbFrequency = (tscFrequency / currcoef);
297cpuFrequency = tscFrequency;
298}
299}
300
301if (!fsbFrequency)
302{
303fsbFrequency = (DEFAULT_FSB * 1000);
304cpuFrequency = tscFrequency;
305DBG("0 ! using the default value for FSB !\n");
306}
307#endif
308
309p->CPU.MaxCoef = maxcoef;
310p->CPU.MaxDiv = maxdiv;
311p->CPU.CurrCoef = currcoef;
312p->CPU.CurrDiv = currdiv;
313p->CPU.TSCFrequency = tscFrequency;
314p->CPU.FSBFrequency = fsbFrequency;
315p->CPU.CPUFrequency = cpuFrequency;
316
317DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);
318DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);
319DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);
320DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);
321DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);
322DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);
323DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);
324DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);
325DBG("CPU: Features: 0x%08x\n", p->CPU.Features);
326#if DEBUG_CPU
327pause();
328#endif
329}
330

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