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Root/branches/meklort/i386/modules/Memory/spd.c

Source at commit 558 created 13 years 6 months ago.
By meklort, Disable debug messages.
1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "saio_internal.h"␊
14#include "bootstruct.h"␊
15#include "memvendors.h"␊
16␊
17#ifndef DEBUG_SPD␊
18#define DEBUG_SPD 0␊
19#endif␊
20␊
21#if DEBUG_SPD␊
22#define DBG(x...)␉printf(x)␊
23#else␊
24#define DBG(x...)␊
25#endif␊
26␊
27const char *spd_memory_types[] =␊
28{␊
29␉"RAM", /* 00h Undefined */␊
30␉"FPM", /* 01h FPM */␊
31␉"EDO", /* 02h EDO */␊
32␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
33␉"SDRAM", /* 04h SDRAM */␊
34␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
35␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
36␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
37␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
38␉"",␉␉␉␉/* 09h Undefined */␊
39␉"",␉␉␉␉/* 0Ah Undefined */␊
40␉"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */␊
41};␊
42␊
43#define UNKNOWN_MEM_TYPE 2␊
44uint8_t spd_mem_to_smbios[] =␊
45{␊
46␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
47␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
48␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
49␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
50␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
51␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
52␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
53␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
54␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
55␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
56␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
57␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
58};␊
59#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
60␊
61#define rdtsc(low,high) \␊
62__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
63␊
64#define SMBHSTSTS 0␊
65#define SMBHSTCNT 2␊
66#define SMBHSTCMD 3␊
67#define SMBHSTADD 4␊
68#define SMBHSTDAT 5␊
69#define SBMBLKDAT 7␊
70␊
71/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
72unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
73{␊
74 int l1 = 0;␊
75␉int l2 = 0;␊
76␉int h1 = 0;␊
77␉int h2 = 0;␊
78 unsigned long long t;␊
79␉␊
80 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
81 outb(base + SMBHSTDAT, 0xff);␊
82␉␊
83 while( inb(base + SMBHSTSTS) & 0x01)␊
84␉{␊
85␉␉rdtsc(l2, h2);␊
86␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform->CPU.TSCFrequency / 100);␊
87␉␉if(t > 50) return 0xFF;␉// hack, exit if unresponsive.␊
88␉}␊
89␉␊
90 outb(base + SMBHSTCMD, cmd);␊
91 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
92 outb(base + SMBHSTCNT, 0x48 );␊
93␉␊
94 rdtsc(l1, h1);␊
95␉␊
96 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
97␉{␉␊
98␉␉rdtsc(l2, h2);␊
99␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform->CPU.TSCFrequency / 100);␊
100␉␉if (t > 5)␊
101␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
102 }␊
103 return inb(base + SMBHSTDAT);␊
104}␊
105␊
106/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
107#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
108␊
109int spd_indexes[] = {␊
110␉SPD_MEMORY_TYPE,␊
111␉SPD_DDR3_MEMORY_BANK,␊
112␉SPD_DDR3_MEMORY_CODE,␊
113␉SPD_NUM_ROWS,␊
114␉SPD_NUM_COLUMNS,␊
115␉SPD_NUM_DIMM_BANKS,␊
116␉SPD_NUM_BANKS_PER_SDRAM,␊
117␉4,7,8,9,12,64, /* TODO: give names to these values */␊
118␉95,96,97,98, 122,123,124,125 /* UIS */␊
119};␊
120#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
121␊
122/** Read from spd *used* values only*/␊
123static void init_spd(char * spd, uint32_t base, int slot)␊
124{␊
125␉int i;␊
126␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
127␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
128␉}␊
129}␊
130␊
131/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
132 have different formats, always return a valid ptr.*/␊
133const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
134{␊
135 uint8_t bank = 0;␊
136 uint8_t code = 0;␊
137 int i = 0;␊
138 uint8_t * spd = (uint8_t *) slot->spd;␊
139␉␊
140 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
141 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
142 code = spd[SPD_DDR3_MEMORY_CODE];␊
143 for (i=0; i < VEN_MAP_SIZE; i++)␊
144 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
145 return vendorMap[i].name;␊
146 }␊
147 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
148 if(spd[64]==0x7f) {␊
149 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
150␉␉␉␉bank++;␊
151␉␉␉␉READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
152␉␉␉}␊
153␉␉␉READ_SPD(spd, base, slot_num,i);␊
154 code = spd[i];␊
155 } else {␊
156 code = spd[64]; ␊
157 bank = 0;␊
158 }␊
159 for (i=0; i < VEN_MAP_SIZE; i++)␊
160 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
161 return vendorMap[i].name;␊
162 }␊
163 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
164 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
165 return "Unifosa";␊
166 return "NoName";␊
167}␊
168␊
169/** Get Default Memory Module Speed (no overclocking handled) */␊
170int getDDRspeedMhz(const char * spd)␊
171{␊
172 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
173 switch(spd[12]) {␊
174␉␉␉case 0x0f:␊
175␉␉␉␉return 1066;␊
176␉␉␉case 0x0c:␊
177␉␉␉␉return 1333;␊
178␉␉␉case 0x0a:␊
179␉␉␉␉return 1600;␊
180␉␉␉case 0x14:␊
181␉␉␉default:␊
182␉␉␉␉return 800;␊
183 }␊
184 } ␊
185 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
186 switch(spd[9]) {␊
187␉␉␉case 0x50:␊
188␉␉␉␉return 400;␊
189␉␉␉case 0x3d:␊
190␉␉␉␉return 533;␊
191␉␉␉case 0x30:␊
192␉␉␉␉return 667;␊
193␉␉␉case 0x25:␊
194␉␉␉default:␊
195␉␉␉␉return 800;␊
196 }␊
197 }␊
198 return 800; // default freq for unknown types␊
199}␊
200␊
201#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
202#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
203␊
204/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
205char asciiSerial[16];␊
206const char *getDDRSerial(const char* spd)␊
207{␊
208 ␊
209 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
210 {␊
211␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
212 }␊
213 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR␊
214 { ␊
215␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
216 }␊
217␉␊
218 return strdup(asciiSerial);␊
219}␊
220␊
221/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
222char asciiPartNo[32];␊
223const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
224{␊
225␉int i, start=0, index = 0;␊
226␉␊
227 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
228␉␉start = 128;␊
229␉}␊
230 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
231␉␉start = 73;␊
232␉}␊
233␉␊
234 // Check that the spd part name is zero terminated and that it is ascii:␊
235 bzero(asciiPartNo, sizeof(asciiPartNo));␊
236␉char c;␊
237␉for (i=start; i < start + sizeof(asciiPartNo); i++) {␊
238␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
239␉␉c = spd[i];␊
240␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
241␉␉␉asciiPartNo[index++] = c;␊
242␉␉else if (!isascii(c))␊
243␉␉␉break;␊
244␉}␊
245␉␊
246␉return strdup(asciiPartNo);␊
247 return NULL;␊
248}␊
249␊
250int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
251␊
252␊
253/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
254static void read_smb_intel(pci_dt_t *smbus_dev)␊
255{ ␊
256 int i, speed;␊
257 uint8_t spd_size, spd_type;␊
258 uint32_t base;␊
259 bool dump = false;␊
260 RamSlotInfo_t* slot;␊
261␉␊
262 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
263 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
264␉␊
265 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
266 bool fullBanks = // needed at least for laptops␊
267␉Platform->DMI.MemoryModules == Platform->DMI.MaxMemorySlots;␊
268␉// Search MAX_RAM_SLOTS slots␊
269␉char spdbuf[256];␊
270␉␊
271 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
272␉␉DBG("Scanning slot %d\n", i);␊
273 slot = &Platform->RAM.DIMM[i];␊
274 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
275 // Check spd is present␊
276 if (spd_size && (spd_size != 0xff) ) {␊
277␉␉␉slot->spd = spdbuf;␊
278 slot->InUse = true;␊
279␉␉␉␊
280 bzero(slot->spd, spd_size);␊
281 ␊
282 // Copy spd data into buffer␊
283 ␊
284␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
285 init_spd(slot->spd, base, i);␊
286␉␉␉␊
287 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
288␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
289␉␉␉␉␉␊
290␉␉␉␉␉slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
291␉␉␉␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
292␉␉␉␉␉break;␊
293␉␉␉␉␉␊
294␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
295␉␉␉␉␉␊
296␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
297␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
298␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
299␉␉␉␉␉␊
300␉␉␉␉␉break;␊
301 }␊
302 ␊
303 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
304 slot->Type = spd_mem_to_smbios[spd_type];␊
305 slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
306 slot->Vendor = getVendorName(slot, base, i);␊
307 slot->SerialNo = getDDRSerial(slot->spd);␊
308␉␉␉␊
309 // determine spd speed␊
310 speed = getDDRspeedMhz(slot->spd);␊
311 if (slot->Frequency<speed) slot->Frequency = speed;␊
312␉␉␉␊
313␉␉␉// pci memory controller if available, is more reliable␊
314␉␉␉if (Platform->RAM.Frequency > 0) {␊
315␉␉␉␉uint32_t freq = (uint32_t)Platform->RAM.Frequency / 500000;␊
316␉␉␉␉// now round off special cases␊
317␉␉␉␉uint32_t fmod100 = freq %100;␊
318␉␉␉␉switch(fmod100) {␊
319␉␉␉␉␉case 1:␉freq--;␉break;␊
320␉␉␉␉␉case 32:␉freq++;␉break;␊
321␉␉␉␉␉case 65:␉freq++; break;␊
322␉␉␉␉␉case 98:␉freq+=2;break;␊
323␉␉␉␉␉case 99:␉freq++; break;␊
324␉␉␉␉}␊
325␉␉␉␉slot->Frequency = freq;␊
326␉␉␉}␊
327␉␉␉␊
328␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
329␉␉␉␉␉i, ␊
330␉␉␉␉␉(int)slot->Type,␊
331␉␉␉␉␉slot->ModuleSize, ␊
332␉␉␉␉␉spd_memory_types[spd_type],␊
333␉␉␉␉␉slot->Frequency,␊
334␉␉␉␉␉slot->Vendor,␊
335␉␉␉␉␉slot->PartNo,␊
336␉␉␉␉␉slot->SerialNo); ␊
337␉␉␉if(DEBUG_SPD) {␊
338␉␉␉␉dumpPhysAddr("spd content: ",slot->spd, spd_size);␊
339␉␉␉␉getc();␊
340 }␊
341 }␊
342 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
343 Platform->DMI.DIMM[i]= ␊
344␉␉i>0 && Platform->RAM.DIMM[1].InUse==false && fullBanks && Platform->DMI.MaxMemorySlots==2 ? ␊
345␉␉mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
346 ␊
347␉␉slot->spd = NULL;␊
348␉␉␊
349 } // for␊
350}␊
351␊
352struct smbus_controllers_t smbus_controllers[] = {␊
353␉␊
354␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
355␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
356␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
357␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
358␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
359␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
360␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
361␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
362␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
363␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
364␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
365␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
366␉␊
367};␊
368␊
369␊
370bool is_smbus_controller(pci_dt_t* pci_dt)␊
371{␊
372␉int i = 0;␊
373␉for ( ; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
374␉{␊
375␉␉if (pci_dt->vendor_id == smbus_controllers[i].vendor &&␊
376␉␉␉pci_dt->device_id == smbus_controllers[i].device)␊
377␉␉{␊
378␉␉␉return true;␊
379␉␉} ␊
380␉}␊
381␉return false;␊
382}␉␊
383␊
384void scan_spd(PlatformInfo_t *p, pci_dt_t* smbus_controller_dev)␊
385{␊
386␉int i = 0;␊
387␉for ( ; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
388␉{␊
389␉␉if (smbus_controller_dev->vendor_id == smbus_controllers[i].vendor &&␊
390␉␉␉smbus_controller_dev->device_id == smbus_controllers[i].device)␊
391␉␉{␊
392␉␉␉smbus_controllers[i].read_smb(smbus_controller_dev); // read smb␊
393␉␉} ␊
394␉}␊
395}␊
396

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