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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9␊
10#ifndef DEBUG_SMBIOS␊
11#define DEBUG_SMBIOS 0␊
12#endif␊
13␊
14#if DEBUG_SMBIOS␊
15#define DBG(x...)␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20␊
21bool getProcessorInformationExternalClock(returnType *value)␊
22{␊
23␉value->word = Platform.CPU.FSBFrequency/1000000;␊
24␉return true;␊
25}␊
26␊
27bool getProcessorInformationMaximumClock(returnType *value)␊
28{␊
29␉value->word = Platform.CPU.CPUFrequency/1000000;␊
30␉return true;␊
31}␊
32␊
33bool getSMBOemProcessorBusSpeed(returnType *value)␊
34{␊
35␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
36␉{␉␉␊
37␉␉switch (Platform.CPU.Family) ␊
38␉␉{␊
39␉␉␉case 0x06:␊
40␉␉␉{␊
41␉␉␉␉switch (Platform.CPU.Model)␊
42␉␉␉␉{␊
43␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊
44␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊
45␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊
46␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊
47␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊
48␉␉␉␉␉␉value->word = 0;␉␉// TODO: populate bus speed for these processors␊
49␉␉␉␉␉␉␊
50//␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
51//␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
52//␉␉␉␉␉␉␉return 2500;␉␉// Core i5␊
53//␉␉␉␉␉␉return 4800;␉␉␉// Core i7␊
54␉␉␉␉␉␉␊
55//␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
56//␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
57//␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
58//␉␉␉␉␉␉return 4800;␉␉␉// GT/s / 1000␊
59//␉␉␉␉␉␉␊
60␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
61␉␉␉␉␉␉value->word = 0;␉␉// TODO: populate bus speed for these processors␊
62␉␉␉␉␉␉␊
63//␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
64//␉␉␉␉␉␉return 2500;␉␉␉// why? Intel spec says 2.5GT/s ␊
65␊
66␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
67␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
68␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
69␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
70␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
71␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
72␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
73␉␉␉␉␉{␊
74␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
75␉␉␉␉␉␉int nhm_bus = 0x3F;␊
76␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
77␉␉␉␉␉␉unsigned long did, vid;␊
78␉␉␉␉␉␉int i;␊
79␉␉␉␉␉␉␊
80␉␉␉␉␉␉// Nehalem supports Scrubbing␊
81␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
82␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
83␉␉␉␉␉␉{␊
84␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
85␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
86␉␉␉␉␉␉␉vid &= 0xFFFF;␊
87␉␉␉␉␉␉␉did &= 0xFF00;␊
88␉␉␉␉␉␉␉␊
89␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
90␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
91␉␉␉␉␉␉}␊
92␉␉␉␉␉␉␊
93␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
94␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
95␉␉␉␉␉␉qpimult &= 0x7F;␊
96␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
97␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
98␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
99␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
100␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
101␉␉␉␉␉␉value->word = qpibusspeed;␊
102␉␉␉␉␉}␊
103␉␉␉␉}␊
104␉␉␉}␊
105␉␉}␊
106␉}␊
107␉return true;␊
108}␊
109␊
110uint16_t simpleGetSMBOemProcessorType(void)␊
111{␊
112␉if (Platform.CPU.NoCores >= 4) ␊
113␉{␊
114␉␉return 0x0501;␉// Quad-Core Xeon␊
115␉}␊
116␉else if (Platform.CPU.NoCores == 1) ␊
117␉{␊
118␉␉return 0x0201;␉// Core Solo␊
119␉};␊
120␉␊
121␉return 0x0301;␉␉// Core 2 Duo␊
122}␊
123␊
124bool getSMBOemProcessorType(returnType *value)␊
125{␊
126␉static bool done = false;␉␉␊
127␉␉␊
128␉value->word = simpleGetSMBOemProcessorType();␊
129␊
130␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
131␉{␊
132␉␉if (!done)␊
133␉␉{␊
134␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
135␉␉␉done = true;␊
136␉␉}␊
137␉␉␊
138␉␉switch (Platform.CPU.Family) ␊
139␉␉{␊
140␉␉␉case 0x06:␊
141␉␉␉{␊
142␉␉␉␉switch (Platform.CPU.Model)␊
143␉␉␉␉{␊
144␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊
145␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊
146␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊
147␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊
148␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
149␉␉␉␉␉␉return true;␊
150␊
151␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊
152␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
153␉␉␉␉␉␉return true;␊
154␊
155␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
156␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
157␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
158␉␉␉␉␉␉else␊
159␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
160␉␉␉␉␉␉return true;␊
161␊
162␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
163␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
164␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
165␉␉␉␉␉␉else␊
166␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
167␉␉␉␉␉␉return true;␊
168␊
169␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
170␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
171␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
172␉␉␉␉␉␉else␊
173␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
174␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊
175␉␉␉␉␉␉␉else␊
176␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊
177␉␉␉␉␉␉return true;␊
178␊
179␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊
180␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
181␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
182␉␉␉␉␉␉return true;␊
183␊
184␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
185␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
186␉␉␉␉␉␉return true;␊
187␉␉␉␉}␊
188␉␉␉}␊
189␉␉}␊
190␉}␊
191␉␊
192␉return false;␊
193}␊
194␊
195bool getSMBMemoryDeviceMemoryType(returnType *value)␊
196{␊
197␉static int idx = -1;␊
198␉int␉map;␊
199␊
200␉idx++;␊
201␉if (idx < MAX_RAM_SLOTS)␊
202␉{␊
203␉␉map = Platform.DMI.DIMM[idx];␊
204␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
205␉␉{␊
206␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
207␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
208␉␉␉return true;␊
209␉␉}␊
210␉}␊
211␉␊
212␉return false;␊
213//␉value->byte = SMB_MEM_TYPE_DDR2;␊
214//␉return true;␊
215}␊
216␊
217bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
218{␊
219␉static int idx = -1;␊
220␉int␉map;␊
221␊
222␉idx++;␊
223␉if (idx < MAX_RAM_SLOTS)␊
224␉{␊
225␉␉map = Platform.DMI.DIMM[idx];␊
226␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
227␉␉{␊
228␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
229␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
230␉␉␉return true;␊
231␉␉}␊
232␉}␊
233␊
234␉return false;␊
235//␉value->dword = 800;␊
236//␉return true;␊
237}␊
238␊
239bool getSMBMemoryDeviceManufacturer(returnType *value)␊
240{␊
241␉static int idx = -1;␊
242␉int␉map;␊
243␊
244␉idx++;␊
245␉if (idx < MAX_RAM_SLOTS)␊
246␉{␊
247␉␉map = Platform.DMI.DIMM[idx];␊
248␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
249␉␉{␊
250␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
251␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
252␉␉␉return true;␊
253␉␉}␊
254␉}␊
255␊
256␉return false;␊
257//␉value->string = "N/A";␊
258//␉return true;␊
259}␊
260␉␊
261bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
262{␊
263␉static int idx = -1;␊
264␉int␉map;␊
265␊
266␉idx++;␊
267␉if (idx < MAX_RAM_SLOTS)␊
268␉{␊
269␉␉map = Platform.DMI.DIMM[idx];␊
270␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
271␉␉{␊
272␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊
273␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊
274␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
275␉␉␉return true;␊
276␉␉}␊
277␉}␊
278␊
279␉return false;␊
280//␉value->string = "N/A";␊
281//␉return true;␊
282}␊
283␊
284bool getSMBMemoryDevicePartNumber(returnType *value)␊
285{␊
286␉static int idx = -1;␊
287␉int␉map;␊
288␊
289␉idx++;␊
290␉if (idx < MAX_RAM_SLOTS)␊
291␉{␊
292␉␉map = Platform.DMI.DIMM[idx];␊
293␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
294␉␉{␊
295␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊
296␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
297␉␉␉return true;␊
298␉␉}␊
299␉}␊
300␊
301␉return false;␊
302//␉value->string = "N/A";␊
303//␉return true;␊
304}␊
305␊
306␊
307// getting smbios addr with fast compare ops, late checksum testing ...␊
308#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
309static const char * const SMTAG = "_SM_";␊
310static const char* const DMITAG = "_DMI_";␊
311␊
312SMBEntryPoint *getAddressOfSmbiosTable(void)␊
313{␊
314␉SMBEntryPoint␉*smbios;␊
315␉/* ␊
316␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
317␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
318␉ */␊
319␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
320␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
321␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
322␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
323␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
324␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
325␉ {␊
326␉␉␉return smbios;␊
327␉ }␊
328␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
329␉}␊
330␉printf("ERROR: Unable to find SMBIOS!\n");␊
331␉pause();␊
332␉return NULL;␊
333}␊
334␊
335

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