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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * valv: 2010: fine-tuning and additions␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "boot.h"␊
11#include "bootstruct.h"␊
12␊
13#ifndef DEBUG_CPU␊
14#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18#define DBG(x...)␉␉printf(x)␊
19#else␊
20#define DBG(x...)␉␉msglog(x)␊
21#endif␊
22␊
23/*␊
24 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
25 */␊
26static uint64_t measure_tsc_frequency(void)␊
27{␊
28 uint64_t tscStart;␊
29 uint64_t tscEnd;␊
30 uint64_t tscDelta = 0xffffffffffffffffULL;␊
31 unsigned long pollCount;␊
32 uint64_t retval = 0;␊
33 int i;␊
34␊
35 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
36 * counter 2. We run this loop 3 times to make sure the cache␊
37 * is hot and we take the minimum delta from all of the runs.␊
38 * That is to say that we're biased towards measuring the minimum␊
39 * number of TSC ticks that occur while waiting for the timer to␊
40 * expire. That theoretically helps avoid inconsistencies when␊
41 * running under a VM if the TSC is not virtualized and the host␊
42 * steals time. The TSC is normally virtualized for VMware.␊
43 */␊
44 for(i = 0; i < 10; ++i)␊
45 {␊
46 enable_PIT2();␊
47 set_PIT2_mode0(CALIBRATE_LATCH);␊
48 tscStart = rdtsc64();␊
49 pollCount = poll_PIT2_gate();␊
50 tscEnd = rdtsc64();␊
51 /* The poll loop must have run at least a few times for accuracy */␊
52 if(pollCount <= 1)␊
53 continue;␊
54 /* The TSC must increment at LEAST once every millisecond. We␊
55 * should have waited exactly 30 msec so the TSC delta should␊
56 * be >= 30. Anything less and the processor is way too slow.␊
57 */␊
58 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
59 continue;␊
60 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
61 if( (tscEnd - tscStart) < tscDelta )␊
62 tscDelta = tscEnd - tscStart;␊
63 }␊
64 /* tscDelta is now the least number of TSC ticks the processor made in␊
65 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
66 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
67 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
68 * Hz so we need to convert our milliseconds to seconds. Since we're␊
69 * dividing by the milliseconds, we simply multiply by 1000.␊
70 */␊
71␊
72 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
73 * that we're going to multiply by 1000 first so we do need at least some␊
74 * arithmetic headroom. For now, 32-bit should be enough.␊
75 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
76 */␊
77 if(tscDelta > (1ULL<<32))␊
78 retval = 0;␊
79 else␊
80 {␊
81 retval = tscDelta * 1000 / 30;␊
82 }␊
83 disable_PIT2();␊
84 return retval;␊
85}␊
86␊
87␊
88/*␊
89 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
90 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
91 * a max multi. (used to calculate the FSB freq.),␊
92 * and a current multi. (used to calculate the CPU freq.)␊
93 * - fsbFrequency = tscFrequency / multi␊
94 * - cpuFrequency = fsbFrequency * multi␊
95 */␊
96␊
97void scan_cpu(PlatformInfo_t *p)␊
98{␊
99␉const char␉*newratio, *newfsb;␊
100␉int␉␉␉len, myfsb, i;␊
101␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
102␉uint64_t␉msr, flex_ratio = 0;␊
103␉uint32_t␉tms, ida, max_ratio, min_ratio;␊
104␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊
105␉bool␉␉fix_fsb, did, core_i, turbo;␊
106␊
107␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊
108␊
109␉/* get cpuid values */␊
110␉for( ; i <= 3; i++)␊
111␉{␊
112␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
113␉}␊
114␉␊
115␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
116␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
117␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
118␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
119␉}␊
120#if DEBUG_CPU␊
121␉{␊
122␉␉int␉␉i;␊
123␉␉printf("CPUID Raw Values:\n");␊
124␉␉for (i=0; i<CPUID_MAX; i++) {␊
125␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
126␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
127␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
128␉␉}␊
129␉}␊
130#endif␊
131␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
132␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
133␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
134␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
135␉p->CPU.Type␉␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊
136␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
137␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
138␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
139␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
140␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
141␊
142␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
143␊
144␉/* get brand string (if supported) */␊
145␉/* Copyright: from Apple's XNU cpuid.c */␊
146␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
147␉␉uint32_t␉reg[4];␊
148 char str[128], *s;␊
149␉␉/*␊
150␉␉ * The brand string 48 bytes (max), guaranteed to␊
151␉␉ * be NUL terminated.␊
152␉␉ */␊
153␉␉do_cpuid(0x80000002, reg);␊
154␉␉bcopy((char *)reg, &str[0], 16);␊
155␉␉do_cpuid(0x80000003, reg);␊
156␉␉bcopy((char *)reg, &str[16], 16);␊
157␉␉do_cpuid(0x80000004, reg);␊
158␉␉bcopy((char *)reg, &str[32], 16);␊
159␉␉for (s = str; *s != '\0'; s++) {␊
160␉␉␉if (*s != ' ') break;␊
161␉␉}␊
162␉␉␊
163␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
164␉␉␊
165␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
166␉␉␉ /*␊
167␉␉␉ * This string means we have a firmware-programmable brand string,␊
168␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
169␉␉␉ */␊
170␉␉␉ p->CPU.BrandString[0] = '\0';␊
171␉␉ }␊
172␉}␊
173␉␊
174␉/* setup features */␊
175␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊
176␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊
177␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊
178␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊
179␊
180␊
181␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
182␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
183␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
184␉}␊
185␉ ␊
186␊
187␉tscFrequency = measure_tsc_frequency();␊
188␉fsbFrequency = 0;␊
189␉cpuFrequency = 0;␊
190␉fix_fsb = false;␊
191␉did = false;␊
192␉core_i = false;␊
193␉turbo = false;␊
194␊
195␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
196␉{␊
197␉␉verbose("CPU: ");␊
198␉␉int tjmax = 0;␊
199␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
200␉␉if (((msr >> 50) & 0x01) == 1)␊
201␉␉{␊
202␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
203␉␉␉verbose("Mobile ");␊
204␉␉}␊
205␉␉verbose("%s\n", p->CPU.BrandString);␊
206␉␉␊
207␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
208␉␉{␊
209␉␉␉if (p->CPU.Family == 0x06)␊
210␉␉␉{␊
211␉␉␉␉int intelCPU = p->CPU.Model;␊
212␉␉␉␉int Stepp = p->CPU.Stepping;␊
213␉␉␉␉int bus;␊
214␊
215␉␉␉␉switch (intelCPU)␊
216␉␉␉␉{␊
217␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊
218␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊
219␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊
220␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm␊
221␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm␊
222␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex Xeon, "Beckton"␊
223␉␉␉␉␉case 0x2f:␉␉// Core i7, Nehalem-Ex Xeon, "Eagleton"␊
224␉␉␉␉␉␉core_i = true;␊
225␉␉␉␉␉␉tjmax = (rdmsr64(MSR_THERMAL_TARGET) >> 16) & 0xff;␊
226␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
227␉␉␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
228␉␉␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
229␉␉␉␉␉␉verbose("Flex: %d ", bus_ratio_max);␊
230␉␉␉␉␉␉min_ratio = bus_ratio_min * 10;␊
231␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
232␉␉␉␉␉␉if ((msr >> 16) & 0x01)␊
233␉␉␉␉␉␉{␊
234␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
235␉␉␉␉␉␉␉verbose(">> %d", flex_ratio);␊
236␉␉␉␉␉␉␉if(bus_ratio_max > flex_ratio) bus_ratio_max = flex_ratio;␊
237␉␉␉␉␉␉}␊
238␉␉␉␉␉␉verbose("\n");␊
239␉␉␉␉␉␉if(bus_ratio_max) fsbFrequency = (tscFrequency / bus_ratio_max);␊
240␊
241␉␉␉␉␉␉//valv: Turbo Ratio Limit␊
242␉␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
243␉␉␉␉␉␉{␊
244␉␉␉␉␉␉␉turbo = true;␊
245␉␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
246␉␉␉␉␉␉␉␊
247␉␉␉␉␉␉␉p->CPU.Tone = (msr >> 0) & 0xff;␊
248␉␉␉␉␉␉␉p->CPU.Ttwo = (msr >> 8) & 0xff;␊
249␉␉␉␉␉␉␉p->CPU.Tthr = (msr >> 16) & 0xff;␊
250␉␉␉␉␉␉␉p->CPU.Tfor = (msr >> 24) & 0xff;␊
251␊
252␉␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
253␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
254␉␉␉␉␉␉}␊
255␉␉␉␉␉␉else cpuFrequency = tscFrequency;␊
256␊
257␉␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
258␉␉␉␉␉␉{␊
259␉␉␉␉␉␉␉max_ratio = atoi(newratio);␊
260␉␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
261␉␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
262␊
263␉␉␉␉␉␉␉verbose("Bus-Ratio: min=%d%s, max=%d%s\n", bus_ratio_min, bus_ratio_max);␊
264␊
265␉␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
266␉␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
267␉␉␉␉␉␉␉{␊
268␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
269␉␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
270␉␉␉␉␉␉␉␉else maxdiv = 0;␊
271␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
272␉␉␉␉␉␉␉}␊
273␉␉␉␉␉␉␉else max_ratio = (bus_ratio_max * 10);␊
274␉␉␉␉␉␉}␊
275␉␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
276␉␉␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
277␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
278␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
279␉␉␉␉␉␉␊
280␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊
281␉␉␉␉␉␉break;␊
282␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊
283␉␉␉␉␉␉goto teleport;␊
284␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊
285␉␉␉␉␉␉switch (Stepp)␊
286␉␉␉␉␉␉{␊
287␉␉␉␉␉␉␉case 0x2:␊
288␉␉␉␉␉␉␉␉tjmax = 95;␊
289␉␉␉␉␉␉␉␉break;␊
290␉␉␉␉␉␉␉case 0x6:␊
291␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 2) tjmax = 80;␊
292␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 4) tjmax = 90;␊
293␉␉␉␉␉␉␉␉else tjmax = 85;␊
294␉␉␉␉␉␉␉␉break;␊
295␉␉␉␉␉␉␉case 0xb:␊
296␉␉␉␉␉␉␉␉tjmax = 90;␊
297␉␉␉␉␉␉␉␉break;␊
298␉␉␉␉␉␉␉case 0xd:␊
299␉␉␉␉␉␉␉default:␊
300␉␉␉␉␉␉␉teleport:␊
301␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊
302␉␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊
303␉␉␉␉␉␉␉␉break;␊
304␉␉␉␉␉␉}␊
305␉␉␉␉␉case 0x1c:␉␉// Atom :)␊
306␉␉␉␉␉␉switch (Stepp)␊
307␉␉␉␉␉␉{␊
308␉␉␉␉␉␉␉case 0xa:␊
309␉␉␉␉␉␉␉␉tjmax = 100;␊
310␉␉␉␉␉␉␉␉break;␊
311␉␉␉␉␉␉␉case 0x2:␊
312␉␉␉␉␉␉␉default:␊
313␉␉␉␉␉␉␉␉tjmax = 90;␊
314␉␉␉␉␉␉␉␉break;␊
315␉␉␉␉␉␉}␊
316␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊
317␉␉␉␉␉␉switch (Stepp)␊
318␉␉␉␉␉␉{␊
319␉␉␉␉␉␉␉case 0x6:␉␉// Mobile Core2 Duo␊
320␉␉␉␉␉␉␉␉tjmax = 104;␊
321␉␉␉␉␉␉␉␉break;␊
322␉␉␉␉␉␉␉case 0xa:␉␉// Mobile Centrino 2␊
323␉␉␉␉␉␉␉␉tjmax = 105;␊
324␉␉␉␉␉␉␉␉break;␊
325␉␉␉␉␉␉␉default:␊
326␉␉␉␉␉␉␉␉if (platformCPUFeature(CPU_FEATURE_MOBILE)) tjmax = 105;␊
327␉␉␉␉␉␉␉␉break;␊
328␉␉␉␉␉␉}␊
329␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊
330␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊
331␉␉␉␉␉␉core_i = false;␊
332␉␉␉␉␉␉␊
333␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM1))␊
334␉␉␉␉␉␉{␊
335␉␉␉␉␉␉␉msr_t msr32;␊
336␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
337␊
338␉␉␉␉␉␉␉if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);␊
339␉␉␉␉␉␉␉verbose("Thermal Monitor: TM, ");␊
340␉␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM2))␊
341␉␉␉␉␉␉␉{␊
342␉␉␉␉␉␉␉␉msr32.lo |= (1 << 13);␊
343␉␉␉␉␉␉␉␉verbose("TM2, ");␊
344␉␉␉␉␉␉␉}␊
345␉␉␉␉␉␉␉msr32.lo |= (1 << 17);␊
346␉␉␉␉␉␉␉verbose("PROCHOT, ");␊
347␉␉␉␉␉␉␉msr32.lo |= (1 << 10);␊
348␉␉␉␉␉␉␉verbose("FERR\n");␊
349␉␉␉␉␉␉␉␊
350␉␉␉␉␉␉␉bool oem_ssdt, tmpval;␊
351␉␉␉␉␉␉␉oem_ssdt = false;␊
352␉␉␉␉␉␉␉␊
353␉␉␉␉␉␉␉oem_ssdt = getBoolForKey(kOEMSSDT, &tmpval, &bootInfo->bootConfig)&&tmpval;␊
354␉␉␉␉␉␉␉if(oem_ssdt)␊
355␉␉␉␉␉␉␉{␊
356␉␉␉␉␉␉␉␉bool c2e, c4e, hc4e;␊
357␉␉␉␉␉␉␉␉c2e = c4e = hc4e = false;␊
358␊
359␉␉␉␉␉␉␉␉getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig);␊
360␉␉␉␉␉␉␉␉if(c2e) msr32.lo |= (1 << 26);␊
361␉␉␉␉␉␉␉␊
362␉␉␉␉␉␉␉␉getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig);␊
363␉␉␉␉␉␉␉␉if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));␊
364␉␉␉␉␉␉␉␉getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);␊
365␉␉␉␉␉␉␉␉if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));␊
366␉␉␉␉␉␉␉}␊
367␉␉␉␉␉␉␉␊
368␉␉␉␉␉␉␉msr32.hi |= (1 << (36 - 32)); // EMTTM␊
369␊
370␉␉␉␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
371␉␉␉␉␉␉}␊
372␉␉␉␉␉␉␊
373␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊
374␉␉␉␉␉␉{␊
375␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));␊
376␉␉␉␉␉␉␉delay(1);␊
377␉␉␉␉␉␉␉did = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊
378␉␉␉␉␉␉}␊
379␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
380␉␉␉␉␉␉if(fix_fsb)␊
381␉␉␉␉␉␉{␊
382␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
383␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊
384␉␉␉␉␉␉␉switch (bus)␊
385␉␉␉␉␉␉␉{␊
386␉␉␉␉␉␉␉␉case 0:␊
387␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
388␉␉␉␉␉␉␉␉␉myfsb = 266;␊
389␉␉␉␉␉␉␉␉␉break;␊
390␉␉␉␉␉␉␉␉case 1:␊
391␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
392␉␉␉␉␉␉␉␉␉myfsb = 133;␊
393␉␉␉␉␉␉␉␉␉break;␊
394␉␉␉␉␉␉␉␉case 3:␊
395␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
396␉␉␉␉␉␉␉␉␉myfsb = 166;␊
397␉␉␉␉␉␉␉␉␉break;␊
398␉␉␉␉␉␉␉␉case 4:␊
399␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
400␉␉␉␉␉␉␉␉␉myfsb = 333;␊
401␉␉␉␉␉␉␉␉␉break;␊
402␉␉␉␉␉␉␉␉case 5:␊
403␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
404␉␉␉␉␉␉␉␉␉myfsb = 100;␊
405␉␉␉␉␉␉␉␉␉break;␊
406␉␉␉␉␉␉␉␉case 6:␊
407␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
408␉␉␉␉␉␉␉␉␉myfsb = 400;␊
409␉␉␉␉␉␉␉␉␉break;␊
410␉␉␉␉␉␉␉␉case 2:␊
411␉␉␉␉␉␉␉␉default:␊
412␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
413␉␉␉␉␉␉␉␉␉myfsb = 200;␊
414␉␉␉␉␉␉␉␉␉break;␊
415␉␉␉␉␉␉␉}␊
416␉␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
417␉␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency)) fsbFrequency = 200000000;␊
418␉␉␉␉␉␉␉goto ratio;␊
419␉␉␉␉␉␉}␊
420␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊
421␉␉␉␉␉// for 0x2a & 0x2b turbo is true;␊
422␉␉␉␉␉//case 0x2a:␉␉// SNB␊
423␉␉␉␉␉//case 0x2b:␉␉// SNB Xeon␊
424␉␉␉␉␉default:␊
425␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig))␊
426␉␉␉␉␉␉{␊
427␉␉␉␉␉␉␉forcefsb:␊
428␉␉␉␉␉␉␉switch(myfsb)␊
429␉␉␉␉␉␉␉{␊
430␉␉␉␉␉␉␉␉case 133:␊
431␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
432␉␉␉␉␉␉␉␉␉break;␊
433␉␉␉␉␉␉␉␉case 166:␊
434␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
435␉␉␉␉␉␉␉␉␉break;␊
436␉␉␉␉␉␉␉␉case 233:␊
437␉␉␉␉␉␉␉␉␉fsbFrequency = 233333333;␊
438␉␉␉␉␉␉␉␉␉break;␊
439␉␉␉␉␉␉␉␉case 266:␊
440␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
441␉␉␉␉␉␉␉␉␉break;␊
442␉␉␉␉␉␉␉␉case 333:␊
443␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
444␉␉␉␉␉␉␉␉␉break;␊
445␉␉␉␉␉␉␉␉case 100:␊
446␉␉␉␉␉␉␉␉case 200:␊
447␉␉␉␉␉␉␉␉case 400:␊
448␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
449␉␉␉␉␉␉␉␉␉break;␊
450␉␉␉␉␉␉␉␉default:␊
451␉␉␉␉␉␉␉␉␉getValueForKey(kForceFSB, &newfsb, &len, &bootInfo->bootConfig);␊
452␉␉␉␉␉␉␉␉␉if((len <= 3) && (myfsb < 400))␊
453␉␉␉␉␉␉␉␉␉{␊
454␉␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
455␉␉␉␉␉␉␉␉␉␉verbose("Specified FSB: %dMhz. Assuming you know what you 're doing !\n", myfsb);␊
456␉␉␉␉␉␉␉␉␉}␊
457␉␉␉␉␉␉␉␉␉else if(core_i) fsbFrequency = 133333333;␊
458␉␉␉␉␉␉␉␉␉else fsbFrequency = 200000000;␊
459␉␉␉␉␉␉␉␉␉break;␊
460␉␉␉␉␉␉␉}␊
461␉␉␉␉␉␉␉if(core_i)␊
462␉␉␉␉␉␉␉{␊
463␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
464␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
465␉␉␉␉␉␉␉␉break;␊
466␉␉␉␉␉␉␉}␊
467␉␉␉␉␉␉␉fix_fsb = true;␊
468␉␉␉␉␉␉}␊
469␉␉␉␉␉␉goto ratio;␊
470␉␉␉␉␉␉break;␊
471␉␉␉␉}␊
472␉␉␉}␊
473␉␉␉else␊
474␉␉␉{␊
475␉␉␉␉ratio:␊
476␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
477␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
478␉␉␉␉//valv: this seems to be bit 15 instead of 14.␊
479␉␉␉␉currdiv = (msr >> 15) & 0x01;␊
480␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊
481␊
482␉␉␉␉msr_t msr;␊
483␉␉␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊
484␉␉␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊
485␉␉␉␉min_ratio = bus_ratio_min * 10;␊
486␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊
487␉␉␉␉␊
488␉␉␉␉if(XE) bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊
489␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊
490␊
491␉␉␉␉if(fix_fsb)␊
492␉␉␉␉{␊
493␉␉␉␉␉ratio_gn:␊
494␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
495␉␉␉␉␉{␊
496␉␉␉␉␉␉max_ratio = atoi(newratio);␊
497␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
498␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
499␊
500␉␉␉␉␉␉verbose("Bus-Ratio defaults: min=%d%s, max=%d%s\n", bus_ratio_min, currdiv ? ".5" : "", bus_ratio_max, maxdiv ? ".5" : "");␊
501␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio < 200))␊
502␉␉␉␉␉␉{␊
503␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
504␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
505␉␉␉␉␉␉␉else maxdiv = 0;␊
506␉␉␉␉␉␉␉verbose("Sticking with [FSB: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
507␉␉␉␉␉␉}␊
508␉␉␉␉␉␉else␊
509␉␉␉␉␉␉{␊
510␉␉␉␉␉␉␉printf("Bus-Ratio: Lowest allowed = %d%s. ", bus_ratio_min, currdiv ? ".5" : "");␊
511␉␉␉␉␉␉␉goto ratio_vldt;␊
512␉␉␉␉␉␉}␊
513␉␉␉␉␉}␊
514␉␉␉␉␉else ␊
515␉␉␉␉␉{␊
516␉␉␉␉␉␉ratio_vldt:␊
517␉␉␉␉␉␉if (maxdiv)␊
518␉␉␉␉␉␉{␊
519␉␉␉␉␉␉␉cpuFrequency = ((fsbFrequency * ((bus_ratio_max * 2) + 1)) / 2);␊
520␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10) + 5;␊
521␉␉␉␉␉␉}␊
522␉␉␉␉␉␉else␊
523␉␉␉␉␉␉{␊
524␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * bus_ratio_max);␊
525␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
526␉␉␉␉␉␉}␊
527␉␉␉␉␉␉verbose("CPU: Sticking with [FSB: %dMhz, Bus-Ratio: %d%s] %s\n", myfsb, bus_ratio_max, maxdiv ? ".5" : "", newratio ? "instead" : "");␊
528␉␉␉␉␉}␊
529␉␉␉␉}␊
530␉␉␉␉else␊
531␉␉␉␉{␊
532␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
533␉␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊
534␊
535␉␉␉␉␉if (bus_ratio_max)␊
536␉␉␉␉␉{␊
537␉␉␉␉␉␉if (maxdiv)␊
538␉␉␉␉␉␉{␊
539␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
540␉␉␉␉␉␉␉max_ratio = ((bus_ratio_max * 10) + 5);␊
541␉␉␉␉␉␉}␊
542␉␉␉␉␉␉else␊
543␉␉␉␉␉␉{␊
544␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
545␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
546␉␉␉␉␉␉}␊
547␊
548␉␉␉␉␉␉myfsb = (fsbFrequency / 1000000);␊
549␉␉␉␉␉␉if (getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) goto ratio_gn;␊
550␉␉␉␉␉␉else cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
551␊
552␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", bus_ratio_max, maxdiv ? ".5" : "", bus_ratio_min, currdiv ? ".5" : "");␊
553␉␉␉␉␉}␊
554␉␉␉␉}␊
555␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
556␉␉␉␉p->CPU.MinRatio = min_ratio;␊
557␉␉␉}␊
558␉␉}␊
559␊
560␉␉// on-die sensor␊
561␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x6)␊
562␉␉{␊
563␉␉␉// Highest Basic Functions Number␊
564␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_81]);␊
565␉␉␉tms = bitfield(p->CPU.CPUID[CPUID_81][0], 0, 0);␊
566␉␉␉ida = bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1);␊
567␉␉␉if(tms != 0)␊
568␉␉␉{␊
569␉␉␉␉int temp, utjmax;␊
570␉␉␉␉if (tjmax == 0) tjmax = 100;␊
571␉␉␉␉if((getIntForKey(kTjmax, &utjmax, &bootInfo->bootConfig)) && ((70 <= utjmax) && (utjmax <= 110))) tjmax = utjmax;␊
572␉␉␉␉msr = rdmsr64(MSR_THERMAL_STATUS);␊
573␉␉␉␉//if ((msr & 0x3) == 0x3)␊
574␉␉␉␉if (((msr >> 31) & 0x1) == 1)␊
575␉␉␉␉{␊
576␉␉␉␉␉temp = tjmax - ((msr >> 16) & 0x7F);␊
577␉␉␉␉␉verbose("CPU: Tjmax ~ %d°C ␉ Temperature= ~ %d°C\n", tjmax, temp);␊
578␉␉␉␉}␊
579␉␉␉␉else temp = -1;␊
580␉␉␉}␊
581␉␉␉if(ida == 0)␊
582␉␉␉{␊
583␉␉␉␉verbose("CPU: Attempting to enable IDA ");␊
584␉␉␉␉msr_t msr;␊
585␉␉␉␉msr = rdmsr(MSR_IA32_MISC_ENABLE);␊
586␉␉␉␉msr.hi |= (0 << (38-32));␊
587␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr);␊
588␉␉␉␉delay(1);␊
589␉␉␉␉if(bitfield(p->CPU.CPUID[CPUID_81][0], 0, 1) == 0) verbose("Failed!\n");␊
590␉␉␉␉else verbose("Succeded!\n");␊
591␉␉␉}␊
592␉␉␉else verbose("CPU: Intel Dynamic Acceleration Enabled!\n");␊
593␉␉}␊
594␉}␊
595#if 0␊
596␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f))␊
597␉{␊
598␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
599␉␉{␊
600␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
601␉␉␉bus_ratio_max = (msr & 0x3f) / 2 + 4;␊
602␉␉␉currdiv = (msr & 0x01) * 2;␊
603␉␉}␊
604␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
605␉␉{␊
606␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
607␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
608␉␉␉␉bus_ratio_max = (msr & 0x3f) + 0x10;␊
609␉␉␉else /* K11+ */␊
610␉␉␉␉bus_ratio_max = (msr & 0x3f) + 0x08;␊
611␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
612␉␉}␊
613␊
614␉␉p->CPU.MaxRatio = bus_ratio_max * 10;␊
615␊
616␉␉if (bus_ratio_max)␊
617␉␉{␊
618␉␉␉if (currdiv)␊
619␉␉␉{␊
620␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max);␊
621␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊
622␉␉␉}␊
623␉␉␉else␊
624␉␉␉{␊
625␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
626␉␉␉␉DBG("%d\n", bus_ratio_max);␊
627␉␉␉}␊
628␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
629␉␉␉cpuFrequency = tscFrequency;␊
630␉␉}␊
631␉}␊
632␊
633␉if (!fsbFrequency)␊
634␉{␊
635␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
636␉␉cpuFrequency = tscFrequency;␊
637␉␉DBG("0 ! using the default value for FSB !\n");␊
638␉}␊
639#endif␊
640␊
641␉p->CPU.MaxDiv = maxdiv;␊
642␉p->CPU.CurrDiv = currdiv;␊
643␉p->CPU.TSCFrequency = tscFrequency;␊
644␉p->CPU.FSBFrequency = fsbFrequency;␊
645␉p->CPU.CPUFrequency = cpuFrequency;␊
646␉p->CPU.ISerie = false;␊
647␉p->CPU.Turbo = false;␊
648␊
649␉if (platformCPUFeature(CPU_FEATURE_EST))␊
650␉{␊
651␉␉msr_t msr32;␊
652␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
653␉␉if (!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16)))␊
654␉␉{␉//valv: we can also attempt to enable␊
655␉␉␉msr32.lo |= (1 << 16);␊
656␉␉␉// Lock till next reset!␊
657␉␉␉msr32.lo |= (1 << 20);␊
658␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
659␉␉␉delay(1);␊
660␉␉␉if(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16))␊
661␉␉␉{␊
662␉␉␉␉p->CPU.EST = 1;␊
663␉␉␉␉verbose("EIST Successfully Enabled!");␊
664␉␉␉}␊
665␉␉␉else␊
666␉␉␉{␊
667␉␉␉␉p->CPU.EST = 0;␊
668␉␉␉␉verbose("EIST couldn't be enabled!");␊
669␉␉␉}␊
670␉␉}␊
671␊
672␉␉else p->CPU.EST = 1;␊
673␉}␊
674␉␊
675␉if(core_i) p->CPU.ISerie = true;␊
676␉␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
677␉␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
678␉␉DBG("CPU: Multipliers x10: max=%d, min=%d\n", p->CPU.MaxRatio, p->CPU.MinRatio);␊
679␉if(turbo)␊
680␉{␊
681␉␉DBG("Turbo Ratio: %d/%d/%d/%d\n", p->CPU.Tone, p->CPU.Ttwo, p->CPU.Tthr, p->CPU.Tfor);␊
682␉␉p->CPU.Turbo = true;␊
683␉}␊
684␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
685␉␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
686␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
687␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
688␉if(did)␊
689␉{␊
690␉␉p->CPU.SLFM = did;␊
691␉␉DBG("CPU: SLFM: %d\n", p->CPU.SLFM);␊
692␉}␊
693␉␉if(platformCPUFeature(CPU_FEATURE_EST))␊
694␉␉DBG("CPU: Enhanced SpeedStep: %d\n", p->CPU.EST);␊
695␉␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
696␉␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
697}␊
698

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