1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | * valv: 2010: fine-tuning and additions␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_CPU_H␊ |
8 | #define __LIBSAIO_CPU_H␊ |
9 | ␊ |
10 | #include "libsaio.h"␊ |
11 | ␊ |
12 | extern void scan_cpu(PlatformInfo_t *);␊ |
13 | ␊ |
14 | #define bit(n)␉␉␉(1UL << (n))␊ |
15 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
16 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
17 | ␊ |
18 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Typ"␊ |
19 | ␊ |
20 | #define MSR_FSB_FREQ 0xCD␊ |
21 | #define MSR_TURBO_RATIO_LIMIT 0x1AD␊ |
22 | #define MSR_IA32_PLATFORM_ID 0x17␊ |
23 | #define␉MSR_IA32_PERF_STATUS 0x198␊ |
24 | #define MSR_IA32_PERF_CONTROL 0x199␊ |
25 | #define MSR_IA32_EXT_CONFIG 0xEE␊ |
26 | #define MSR_FLEX_RATIO 0x194␊ |
27 | #define␉MSR_PLATFORM_INFO 0xCE␊ |
28 | #define MSR_IA32_MISC_ENABLE 0x1A0␊ |
29 | #define MSR_THERMAL_STATUS 0x19C␊ |
30 | #define MSR_THERMAL_TARGET 0x01A2␊ |
31 | #define K8_FIDVID_STATUS 0xC0010042␊ |
32 | #define K10_COFVID_STATUS 0xC0010071␊ |
33 | ␊ |
34 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
35 | ␊ |
36 | // DFE: This constant comes from older xnu:␊ |
37 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
38 | ␊ |
39 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
40 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
41 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
42 | ␊ |
43 | static inline uint64_t rdtsc64(void)␊ |
44 | {␊ |
45 | ␉uint64_t ret;␊ |
46 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
47 | ␉return ret;␊ |
48 | }␊ |
49 | ␊ |
50 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
51 | {␊ |
52 | uint64_t ret;␊ |
53 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
54 | return ret;␊ |
55 | }␊ |
56 | ␊ |
57 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
58 | {␊ |
59 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
60 | }␊ |
61 | ␊ |
62 | typedef struct msr_struct␊ |
63 | {␊ |
64 | ␉unsigned lo;␊ |
65 | ␉unsigned hi;␊ |
66 | } msr_t;␊ |
67 | ␊ |
68 | static inline __attribute__((always_inline)) msr_t rdmsr(unsigned val)␊ |
69 | {␊ |
70 | ␉msr_t ret;␊ |
71 | ␉__asm__ volatile(␊ |
72 | ␉␉"rdmsr"␊ |
73 | ␉␉: "=a" (ret.lo), "=d" (ret.hi)␊ |
74 | ␉␉: "c" (val)␊ |
75 | ␉␉);␊ |
76 | ␉return ret;␊ |
77 | }␊ |
78 | ␊ |
79 | static inline __attribute__((always_inline)) void wrmsr(unsigned val, msr_t msr)␊ |
80 | {␊ |
81 | ␉__asm__ __volatile__ (␊ |
82 | ␉␉"wrmsr"␊ |
83 | ␉␉: /* No outputs */␊ |
84 | ␉␉: "c" (val), "a" (msr.lo), "d" (msr.hi)␊ |
85 | ␉␉);␊ |
86 | }␊ |
87 | ␊ |
88 | static inline void intel_waitforsts(void) {␊ |
89 | ␉uint32_t inline_timeout = 100000;␊ |
90 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
91 | }␊ |
92 | ␊ |
93 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
94 | {␊ |
95 | ␉asm volatile ("cpuid"␊ |
96 | ␉␉␉␉ : "=a" (data[0]),␊ |
97 | ␉␉␉␉ "=b" (data[1]),␊ |
98 | ␉␉␉␉ "=c" (data[2]),␊ |
99 | ␉␉␉␉ "=d" (data[3])␊ |
100 | ␉␉␉␉ : "a" (selector));␊ |
101 | }␊ |
102 | ␊ |
103 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
104 | {␊ |
105 | ␉asm volatile ("cpuid"␊ |
106 | ␉␉␉␉ : "=a" (data[0]),␊ |
107 | ␉␉␉␉ "=b" (data[1]),␊ |
108 | ␉␉␉␉ "=c" (data[2]),␊ |
109 | ␉␉␉␉ "=d" (data[3])␊ |
110 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
111 | }␊ |
112 | ␊ |
113 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
114 | ␊ |
115 | /*␊ |
116 | * Enable or disable timer 2.␊ |
117 | * Port 0x61 controls timer 2:␊ |
118 | * bit 0 gates the clock,␊ |
119 | * bit 1 gates output to speaker.␊ |
120 | */␊ |
121 | static inline void enable_PIT2(void)␊ |
122 | {␊ |
123 | /* Enable gate, disable speaker */␊ |
124 | __asm__ volatile(␊ |
125 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
126 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
127 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
128 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
129 | ␉␉␉␉␉ : : : "%al" );␊ |
130 | }␊ |
131 | ␊ |
132 | static inline void disable_PIT2(void)␊ |
133 | {␊ |
134 | /* Disable gate and output to speaker */␊ |
135 | __asm__ volatile(␊ |
136 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
137 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
138 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
139 | ␉␉␉␉␉ : : : "%al" );␊ |
140 | }␊ |
141 | ␊ |
142 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
143 | // roughly based on Linux code␊ |
144 | ␊ |
145 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
146 | In mode 0, the counter will initially set its gate low when the␊ |
147 | timer expires. For this to be useful, you ought to set it high␊ |
148 | before calling this function. The enable_PIT2 function does this.␊ |
149 | */␊ |
150 | static inline void set_PIT2_mode0(uint16_t value)␊ |
151 | {␊ |
152 | __asm__ volatile(␊ |
153 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
154 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
155 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
156 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
157 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
158 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
159 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
160 | }␊ |
161 | ␊ |
162 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
163 | static inline unsigned long poll_PIT2_gate(void)␊ |
164 | {␊ |
165 | unsigned long count = 0;␊ |
166 | unsigned char nmi_sc_val;␊ |
167 | do {␊ |
168 | ++count;␊ |
169 | __asm__ volatile(␊ |
170 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
171 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
172 | } while( (nmi_sc_val & 0x20) == 0);␊ |
173 | return count;␊ |
174 | }␊ |
175 | ␊ |
176 | #endif /* !__LIBSAIO_CPU_H */␊ |
177 | |