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Root/branches/Kabyl/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71#if 0␊
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
73unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
74{␊
75 int l1, h1, l2, h2;␊
76 unsigned long long t;␊
77␉␊
78#define Reg32(reg)␉␉␉␉␉(*(volatile uint32_t *)(base + reg))␊
79#define RegRead32(reg)␉␉␉␉(Reg32(reg))␊
80#define RegWrite32(reg, value)␉␉(Reg32(reg) = value)␊
81␊
82 RegWrite32(SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
83 RegWrite32(SMBHSTDAT, 0xff);␊
84␉␊
85 while(RegRead32(SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
86␉␊
87 RegWrite32(SMBHSTCMD, cmd);␊
88 RegWrite32(SMBHSTADD, (adr << 1) | 0x01 );␊
89 RegWrite32(SMBHSTCNT, 0x48 );␊
90␉␊
91 rdtsc(l1, h1);␊
92␉␊
93 ␉while (!( RegRead32(SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
94␉{␉␊
95␉␉rdtsc(l2, h2);␊
96␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
97␉␉if (t > 5)␊
98␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
99 }␊
100 return RegRead32(SMBHSTDAT);␊
101}␊
102#endif␊
103//#if 0␊
104/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
105unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
106{␊
107 int l1, h1, l2, h2;␊
108 unsigned long long t;␊
109␉␊
110 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
111 outb(base + SMBHSTDAT, 0xff);␊
112␉␊
113 while( inb(base + SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
114␉␊
115 outb(base + SMBHSTCMD, cmd);␊
116 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
117 outb(base + SMBHSTCNT, 0x48 );␊
118␉␊
119 rdtsc(l1, h1);␊
120␉␊
121 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
122␉{␉␊
123␉␉rdtsc(l2, h2);␊
124␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
125␉␉if (t > 5)␊
126␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
127 }␊
128 return inb(base + SMBHSTDAT);␊
129}␊
130//#endif␊
131␊
132/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
133#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
134␊
135int spd_indexes[] = {␊
136␉SPD_MEMORY_TYPE,␊
137␉SPD_DDR3_MEMORY_BANK,␊
138␉SPD_DDR3_MEMORY_CODE,␊
139␉SPD_NUM_ROWS,␊
140␉SPD_NUM_COLUMNS,␊
141␉SPD_NUM_DIMM_BANKS,␊
142␉SPD_NUM_BANKS_PER_SDRAM,␊
143␉4,7,8,9,12,64, /* TODO: give names to these values */␊
144␉95,96,97,98, 122,123,124,125 /* UIS */␊
145};␊
146#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
147␊
148/** Read from spd *used* values only*/␊
149static void init_spd(char * spd, uint32_t base, int slot)␊
150{␊
151␉int i;␊
152␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
153␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
154␉}␊
155}␊
156␊
157/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
158 have different formats, always return a valid ptr.*/␊
159const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
160{␊
161 uint8_t bank = 0;␊
162 uint8_t code = 0;␊
163 int i = 0;␊
164 uint8_t * spd = (uint8_t *) slot->spd;␊
165␊
166 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
167 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
168 code = spd[SPD_DDR3_MEMORY_CODE];␊
169 for (i=0; i < VEN_MAP_SIZE; i++)␊
170 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
171 return vendorMap[i].name;␊
172 }␊
173 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
174 if(spd[64]==0x7f) {␊
175 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
176␉␉␉ bank++;␊
177␉␉␉ READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
178␉␉␉}␊
179␉␉␉READ_SPD(spd, base, slot_num,i);␊
180 code = spd[i];␊
181 } else {␊
182 code = spd[64]; ␊
183 bank = 0;␊
184 }␊
185 for (i=0; i < VEN_MAP_SIZE; i++)␊
186 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
187 return vendorMap[i].name;␊
188 }␊
189 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
190 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
191 return "Unifosa";␊
192 return "NoName";␊
193}␊
194␊
195/** Get Default Memory Module Speed (no overclocking handled) */␊
196int getDDRspeedMhz(const char * spd)␊
197{␊
198 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
199 switch(spd[12]) {␊
200 case 0x0f:␊
201 return 1066;␊
202 case 0x0c:␊
203 return 1333;␊
204 case 0x0a:␊
205 return 1600;␊
206 case 0x14:␊
207 default:␊
208 return 800;␊
209 }␊
210 } ␊
211 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
212 switch(spd[9]) {␊
213 case 0x50:␊
214 return 400;␊
215 case 0x3d:␊
216 return 533;␊
217 case 0x30:␊
218 return 667;␊
219 case 0x25:␊
220 default:␊
221 return 800;␊
222 }␊
223 }␊
224 return 800; // default freq for unknown types␊
225}␊
226␊
227#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
228#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
229␊
230/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
231const char *getDDRSerial(const char* spd)␊
232{␊
233 static char asciiSerial[16];␊
234 ␊
235 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
236 {␊
237␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
238 }␊
239 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR␊
240 { ␊
241␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
242 }␊
243␊
244 return strdup(asciiSerial);␊
245}␊
246␊
247/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
248const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
249{␊
250␉static char asciiPartNo[32];␊
251␉int i, start=0, index = 0;␊
252␊
253 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
254␉␉start = 128;␊
255␉}␊
256 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
257␉␉start = 73;␊
258␉}␊
259␉␊
260 // Check that the spd part name is zero terminated and that it is ascii:␊
261 bzero(asciiPartNo, sizeof(asciiPartNo));␊
262␉char c;␊
263␉for (i=start; i < start + sizeof(asciiPartNo); i++) {␊
264␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
265␉␉c = spd[i];␊
266␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
267␉␉␉asciiPartNo[index++] = c;␊
268␉␉else if (!isascii(c))␊
269␉␉␉break;␊
270␉}␊
271␉␊
272␉return strdup(asciiPartNo);␊
273 return NULL;␊
274}␊
275␊
276int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
277␊
278␊
279/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
280static void read_smb_intel(pci_dt_t *smbus_dev)␊
281{ ␊
282 int i, speed;␊
283 uint8_t spd_size, spd_type;␊
284 uint32_t base, mmio, hostc;␊
285 bool dump = false;␊
286 RamSlotInfo_t* slot;␊
287␊
288␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
289␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
290␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
291␊
292␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
293 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
294␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
295 verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
296␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
297␊
298 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
299␉// needed at least for laptops␊
300 bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
301␊
302␉char spdbuf[MAX_SPD_SIZE];␊
303 // Search MAX_RAM_SLOTS slots␊
304 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
305 slot = &Platform.RAM.DIMM[i];␊
306 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
307␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
308 // Check spd is present␊
309 if (spd_size && (spd_size != 0xff))␊
310 {␊
311␊
312␉␉␉slot->spd = spdbuf;␊
313 slot->InUse = true;␊
314␊
315 bzero(slot->spd, spd_size);␊
316 ␊
317 // Copy spd data into buffer␊
318 ␊
319␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
320 init_spd(slot->spd, base, i);␊
321␉␉␊
322 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
323 case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
324 ␊
325 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
326 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
327 break;␊
328 ␊
329 case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
330 ␊
331 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
332 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
333 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
334 ␊
335 break;␊
336 }␊
337 ␊
338 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
339 slot->Type = spd_mem_to_smbios[spd_type];␊
340 slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
341 slot->Vendor = getVendorName(slot, base, i);␊
342 slot->SerialNo = getDDRSerial(slot->spd);␊
343␊
344 // determine spd speed␊
345 speed = getDDRspeedMhz(slot->spd);␊
346 if (slot->Frequency<speed) slot->Frequency = speed;␊
347␉␉␉␊
348␉␉␉// pci memory controller if available, is more reliable␊
349␉␉␉if (Platform.RAM.Frequency > 0) {␊
350␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
351␉␉␉␉// now round off special cases␊
352␉␉␉␉uint32_t fmod100 = freq %100;␊
353␉␉␉␉switch(fmod100) {␊
354␉␉␉␉␉case 1:␉freq--;␉break;␊
355␉␉␉␉␉case 32:␉freq++;␉break;␊
356␉␉␉␉␉case 65:␉freq++; break;␊
357␉␉␉␉␉case 98:␉freq+=2;break;␊
358␉␉␉␉␉case 99:␉freq++; break;␊
359␉␉␉␉}␊
360␉␉␉␉slot->Frequency = freq;␊
361␉␉␉}␊
362␊
363␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
364 i, ␊
365 (int)slot->Type,␊
366 slot->ModuleSize, ␊
367 spd_memory_types[spd_type],␊
368 slot->Frequency,␊
369 slot->Vendor,␊
370 slot->PartNo,␊
371 slot->SerialNo); ␊
372␊
373#if DEBUG_SPD␊
374 dumpPhysAddr("spd content: ", slot->spd, spd_size);␊
375 getc();␊
376#endif␊
377 }␊
378␊
379 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
380 Platform.DMI.DIMM[i]= ␊
381 i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ? ␊
382 mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
383 ␊
384␉␉slot->spd = NULL;␊
385␊
386 } // for␊
387}␊
388␊
389static struct smbus_controllers_t smbus_controllers[] = {␊
390␊
391␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
392␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
393␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
394␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
395␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
396␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
397␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
398␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
399␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
400␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
401␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
402␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
403␊
404};␊
405␊
406// initial call : pci_dt = root_pci_dev;␊
407// find_and_read_smbus_controller(root_pci_dev);␊
408bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
409{␊
410 pci_dt_t␉*current = pci_dt;␊
411 int i;␊
412␊
413 while (current) {␊
414#if 0␊
415 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
416 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
417 current->class_id, current->vendor_id, current->device_id, ␊
418 get_pci_dev_path(current));␊
419#endif␊
420␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
421 {␊
422 if (current->vendor_id == smbus_controllers[i].vendor &&␊
423 current->device_id == smbus_controllers[i].device)␊
424 {␊
425 smbus_controllers[i].read_smb(current); // read smb␊
426 return true;␊
427 } ␊
428 }␊
429 find_and_read_smbus_controller(current->children);␊
430 current = current->next;␊
431 }␊
432 return false; // not found␊
433}␊
434␊
435void scan_spd(PlatformInfo_t *p)␊
436{␊
437 find_and_read_smbus_controller(root_pci_dev);␊
438}␊
439␊
440

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