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Root/branches/Kabyl/i386/libsaio/pci.h

1/*
2 *
3 * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.
4 *
5 */
6
7#ifndef __LIBSAIO_PCI_H
8#define __LIBSAIO_PCI_H
9
10typedef struct {
11uint32_t:2;
12uint32_treg:6;
13uint32_tfunc:3;
14uint32_tdev:5;
15uint32_tbus:8;
16uint32_t:7;
17uint32_teb:1;
18} pci_addr_t;
19
20typedef union {
21pci_addr_tbits;
22uint32_taddr;
23} pci_dev_t;
24
25typedef struct pci_dt_t {
26pci_dev_tdev;
27
28uint16_tvendor_id;
29uint16_tdevice_id;
30
31union {
32struct {
33uint16_tvendor_id;
34uint16_tdevice_id;
35}subsys;
36uint32_tsubsys_id;
37}subsys_id;
38
39uint16_tclass_id;
40
41struct pci_dt_t*parent;
42struct pci_dt_t*children;
43struct pci_dt_t*next;
44} pci_dt_t;
45
46#define PCIADDR(bus, dev, func)(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
47#define PCI_ADDR_REG0xcf8
48#define PCI_DATA_REG0xcfc
49
50extern pci_dt_t*root_pci_dev;
51extern uint8_tpci_config_read8(uint32_t, uint8_t);
52extern uint16_tpci_config_read16(uint32_t, uint8_t);
53extern uint32_tpci_config_read32(uint32_t, uint8_t);
54extern voidpci_config_write8(uint32_t, uint8_t, uint8_t);
55extern voidpci_config_write16(uint32_t, uint8_t, uint16_t);
56extern voidpci_config_write32(uint32_t, uint8_t, uint32_t);
57extern char*get_pci_dev_path(pci_dt_t *);
58extern voidbuild_pci_dt(void);
59extern voiddump_pci_dt(pci_dt_t *);
60
61/* Option ROM header */
62typedef struct {
63uint16_tsignature;// 0x55AA
64uint8_trom_size;
65uint32_tentry_point;
66uint8_treserved[17];
67uint16_tpci_header_offset;
68uint16_texpansion_header_offset;
69} option_rom_header_t;
70
71/* Option ROM PCI Data Structure */
72typedef struct {
73uint32_tsignature;// 0x50434952 'PCIR'
74uint16_tvendor_id;
75uint16_tdevice_id;
76uint16_tvital_product_data_offset;
77uint16_tstructure_length;
78uint8_tstructure_revision;
79uint8_tclass_code[3];
80uint16_timage_length;
81uint16_timage_revision;
82uint8_tcode_type;
83uint8_tindicator;
84uint16_treserved;
85} option_rom_pci_header_t;
86
87//-----------------------------------------------------------------------------
88// added by iNDi
89
90typedef struct {
91uint32_tsignature;// 0x24506E50 '$PnP'
92uint8_trevision;// 1
93uint8_tlength;//
94uint16_toffset;
95uint8_tchecksum;
96uint32_tidentifier;
97uint16_tmanufacturer;
98uint16_tproduct;
99uint8_tclass[3];
100uint8_tindicators;
101uint16_tboot_vector;
102uint16_tdisconnect_vector;
103uint16_tbootstrap_vector;
104uint16_treserved;
105uint16_tresource_vector;
106} option_rom_pnp_header_t;
107
108/*
109 * Under PCI, each device has 256 bytes of configuration address space,
110 * of which the first 64 bytes are standardized as follows:
111 */
112
113#define PCI_VENDOR_ID0x00/* 16 bits */
114#define PCI_DEVICE_ID0x02/* 16 bits */
115#define PCI_COMMAND0x04/* 16 bits */
116#define PCI_COMMAND_IO0x1/* Enable response in I/O space */
117#define PCI_COMMAND_MEMORY0x2/* Enable response in Memory space */
118#define PCI_COMMAND_MASTER0x4/* Enable bus mastering */
119#define PCI_COMMAND_SPECIAL0x8/* Enable response to special cycles */
120#define PCI_COMMAND_INVALIDATE0x10/* Use memory write and invalidate */
121#define PCI_COMMAND_VGA_PALETTE0x20/* Enable palette snooping */
122#define PCI_COMMAND_PARITY0x40/* Enable parity checking */
123#define PCI_COMMAND_WAIT0x80/* Enable address/data stepping */
124#define PCI_COMMAND_SERR0x100/* Enable SERR */
125#define PCI_COMMAND_FAST_BACK0x200/* Enable back-to-back writes */
126#define PCI_COMMAND_DISABLE_INTx0x400/* PCIE: Disable INTx interrupts */
127
128#define PCI_STATUS0x06/* 16 bits */
129#define PCI_STATUS_INTx0x08/* PCIE: INTx interrupt pending */
130#define PCI_STATUS_CAP_LIST0x10/* Support Capability List */
131#define PCI_STATUS_66MHZ0x20/* Support 66 Mhz PCI 2.1 bus */
132#define PCI_STATUS_UDF0x40/* Support User Definable Features [obsolete] */
133#define PCI_STATUS_FAST_BACK0x80/* Accept fast-back to back */
134#define PCI_STATUS_PARITY0x100/* Detected parity error */
135#define PCI_STATUS_DEVSEL_MASK0x600/* DEVSEL timing */
136#define PCI_STATUS_DEVSEL_FAST0x000
137#define PCI_STATUS_DEVSEL_MEDIUM0x200
138#define PCI_STATUS_DEVSEL_SLOW0x400
139#define PCI_STATUS_SIG_TARGET_ABORT 0x800/* Set on target abort */
140#define PCI_STATUS_REC_TARGET_ABORT 0x1000/* Master ack of " */
141#define PCI_STATUS_REC_MASTER_ABORT 0x2000/* Set on master abort */
142#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000/* Set when we drive SERR */
143#define PCI_STATUS_DETECTED_PARITY0x8000/* Set on parity error */
144
145#define PCI_CLASS_REVISION0x08/* High 24 bits are class, low 8 revision */
146#define PCI_REVISION_ID0x08 /* Revision ID */
147#define PCI_CLASS_PROG0x09 /* Reg. Level Programming Interface */
148#define PCI_CLASS_DEVICE0x0a /* Device class */
149
150#define PCI_CACHE_LINE_SIZE0x0c/* 8 bits */
151#define PCI_LATENCY_TIMER0x0d/* 8 bits */
152#define PCI_HEADER_TYPE0x0e/* 8 bits */
153#define PCI_HEADER_TYPE_NORMAL0
154#define PCI_HEADER_TYPE_BRIDGE1
155#define PCI_HEADER_TYPE_CARDBUS2
156
157#define PCI_BIST0x0f/* 8 bits */
158#define PCI_BIST_CODE_MASK0x0f/* Return result */
159#define PCI_BIST_START0x40/* 1 to start BIST, 2 secs or less */
160#define PCI_BIST_CAPABLE0x80/* 1 if BIST capable */
161
162/*
163 * Base addresses specify locations in memory or I/O space.
164 * Decoded size can be determined by writing a value of
165 * 0xffffffff to the register, and reading it back. Only
166 * 1 bits are decoded.
167 */
168#define PCI_BASE_ADDRESS_00x10/* 32 bits */
169#define PCI_BASE_ADDRESS_10x14/* 32 bits [htype 0,1 only] */
170#define PCI_BASE_ADDRESS_20x18/* 32 bits [htype 0 only] */
171#define PCI_BASE_ADDRESS_30x1c/* 32 bits */
172#define PCI_BASE_ADDRESS_40x20/* 32 bits */
173#define PCI_BASE_ADDRESS_50x24/* 32 bits */
174#define PCI_BASE_ADDRESS_SPACE0x01/* 0 = memory, 1 = I/O */
175#define PCI_BASE_ADDRESS_SPACE_IO0x01
176#define PCI_BASE_ADDRESS_SPACE_MEMORY0x00
177#define PCI_BASE_ADDRESS_MEM_TYPE_MASK0x06
178#define PCI_BASE_ADDRESS_MEM_TYPE_320x00/* 32 bit address */
179#define PCI_BASE_ADDRESS_MEM_TYPE_1M0x02/* Below 1M [obsolete] */
180#define PCI_BASE_ADDRESS_MEM_TYPE_640x04/* 64 bit address */
181#define PCI_BASE_ADDRESS_MEM_PREFETCH0x08/* prefetchable? */
182#define PCI_BASE_ADDRESS_MEM_MASK(~(pciaddr_t)0x0f)
183#define PCI_BASE_ADDRESS_IO_MASK(~(pciaddr_t)0x03)
184/* bit 1 is reserved if address_space = 1 */
185
186/* Header type 0 (normal devices) */
187#define PCI_CARDBUS_CIS0x28
188#define PCI_SUBSYSTEM_VENDOR_ID0x2c
189#define PCI_SUBSYSTEM_ID0x2e
190#define PCI_ROM_ADDRESS0x30/* Bits 31..11 are address, 10..1 reserved */
191#define PCI_ROM_ADDRESS_ENABLE0x01
192#define PCI_ROM_ADDRESS_MASK(~(pciaddr_t)0x7ff)
193
194#define PCI_CAPABILITY_LIST0x34/* Offset of first capability list entry */
195
196/* 0x35-0x3b are reserved */
197#define PCI_INTERRUPT_LINE0x3c/* 8 bits */
198#define PCI_INTERRUPT_PIN0x3d/* 8 bits */
199#define PCI_MIN_GNT0x3e/* 8 bits */
200#define PCI_MAX_LAT0x3f/* 8 bits */
201
202/* Header type 1 (PCI-to-PCI bridges) */
203#define PCI_PRIMARY_BUS0x18/* Primary bus number */
204#define PCI_SECONDARY_BUS0x19/* Secondary bus number */
205#define PCI_SUBORDINATE_BUS0x1a/* Highest bus number behind the bridge */
206#define PCI_SEC_LATENCY_TIMER0x1b/* Latency timer for secondary interface */
207#define PCI_IO_BASE0x1c/* I/O range behind the bridge */
208#define PCI_IO_LIMIT0x1d
209#define PCI_IO_RANGE_TYPE_MASK0x0f/* I/O bridging type */
210#define PCI_IO_RANGE_TYPE_160x00
211#define PCI_IO_RANGE_TYPE_320x01
212#define PCI_IO_RANGE_MASK~0x0f
213#define PCI_SEC_STATUS0x1e/* Secondary status register */
214#define PCI_MEMORY_BASE0x20/* Memory range behind */
215#define PCI_MEMORY_LIMIT0x22
216#define PCI_MEMORY_RANGE_TYPE_MASK0x0f
217#define PCI_MEMORY_RANGE_MASK~0x0f
218#define PCI_PREF_MEMORY_BASE0x24/* Prefetchable memory range behind */
219#define PCI_PREF_MEMORY_LIMIT0x26
220#define PCI_PREF_RANGE_TYPE_MASK0x0f
221#define PCI_PREF_RANGE_TYPE_320x00
222#define PCI_PREF_RANGE_TYPE_640x01
223#define PCI_PREF_RANGE_MASK~0x0f
224#define PCI_PREF_BASE_UPPER320x28/* Upper half of prefetchable memory range */
225#define PCI_PREF_LIMIT_UPPER320x2c
226#define PCI_IO_BASE_UPPER160x30/* Upper half of I/O addresses */
227#define PCI_IO_LIMIT_UPPER160x32
228/* 0x34 same as for htype 0 */
229/* 0x35-0x3b is reserved */
230#define PCI_ROM_ADDRESS10x38/* Same as PCI_ROM_ADDRESS, but for htype 1 */
231/* 0x3c-0x3d are same as for htype 0 */
232#define PCI_BRIDGE_CONTROL0x3e
233#define PCI_BRIDGE_CTL_PARITY0x01/* Enable parity detection on secondary interface */
234#define PCI_BRIDGE_CTL_SERR0x02/* The same for SERR forwarding */
235#define PCI_BRIDGE_CTL_NO_ISA0x04/* Disable bridging of ISA ports */
236#define PCI_BRIDGE_CTL_VGA0x08/* Forward VGA addresses */
237#define PCI_BRIDGE_CTL_MASTER_ABORT0x20/* Report master aborts */
238#define PCI_BRIDGE_CTL_BUS_RESET0x40/* Secondary bus reset */
239#define PCI_BRIDGE_CTL_FAST_BACK0x80/* Fast Back2Back enabled on secondary interface */
240#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100/* PCI-X? */
241#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200/* PCI-X? */
242#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400/* PCI-X? */
243#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800/* PCI-X? */
244
245/* Header type 2 (CardBus bridges) */
246/* 0x14-0x15 reserved */
247#define PCI_CB_SEC_STATUS0x16/* Secondary status */
248#define PCI_CB_PRIMARY_BUS0x18/* PCI bus number */
249#define PCI_CB_CARD_BUS0x19/* CardBus bus number */
250#define PCI_CB_SUBORDINATE_BUS0x1a/* Subordinate bus number */
251#define PCI_CB_LATENCY_TIMER0x1b/* CardBus latency timer */
252#define PCI_CB_MEMORY_BASE_00x1c
253#define PCI_CB_MEMORY_LIMIT_00x20
254#define PCI_CB_MEMORY_BASE_10x24
255#define PCI_CB_MEMORY_LIMIT_10x28
256#define PCI_CB_IO_BASE_00x2c
257#define PCI_CB_IO_BASE_0_HI0x2e
258#define PCI_CB_IO_LIMIT_00x30
259#define PCI_CB_IO_LIMIT_0_HI0x32
260#define PCI_CB_IO_BASE_10x34
261#define PCI_CB_IO_BASE_1_HI0x36
262#define PCI_CB_IO_LIMIT_10x38
263#define PCI_CB_IO_LIMIT_1_HI0x3a
264#define PCI_CB_IO_RANGE_MASK~0x03
265/* 0x3c-0x3d are same as for htype 0 */
266#define PCI_CB_BRIDGE_CONTROL0x3e
267#define PCI_CB_BRIDGE_CTL_PARITY0x01/* Similar to standard bridge control register */
268#define PCI_CB_BRIDGE_CTL_SERR0x02
269#define PCI_CB_BRIDGE_CTL_ISA0x04
270#define PCI_CB_BRIDGE_CTL_VGA0x08
271#define PCI_CB_BRIDGE_CTL_MASTER_ABORT0x20
272#define PCI_CB_BRIDGE_CTL_CB_RESET0x40/* CardBus reset */
273#define PCI_CB_BRIDGE_CTL_16BIT_INT0x80/* Enable interrupt for 16-bit cards */
274#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100/* Prefetch enable for both memory regions */
275#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
276#define PCI_CB_BRIDGE_CTL_POST_WRITES0x400
277#define PCI_CB_SUBSYSTEM_VENDOR_ID0x40
278#define PCI_CB_SUBSYSTEM_ID0x42
279#define PCI_CB_LEGACY_MODE_BASE0x44/* 16-bit PC Card legacy mode base address (ExCa) */
280/* 0x48-0x7f reserved */
281
282/* Capability lists */
283#define PCI_CAP_LIST_ID0/* Capability ID */
284#define PCI_CAP_ID_PM0x01/* Power Management */
285#define PCI_CAP_ID_AGP0x02/* Accelerated Graphics Port */
286#define PCI_CAP_ID_VPD0x03/* Vital Product Data */
287#define PCI_CAP_ID_SLOTID0x04/* Slot Identification */
288#define PCI_CAP_ID_MSI0x05/* Message Signaled Interrupts */
289#define PCI_CAP_ID_CHSWP0x06/* CompactPCI HotSwap */
290#define PCI_CAP_ID_PCIX0x07/* PCI-X */
291#define PCI_CAP_ID_HT0x08/* HyperTransport */
292#define PCI_CAP_ID_VNDR0x09/* Vendor specific */
293#define PCI_CAP_ID_DBG0x0A/* Debug port */
294#define PCI_CAP_ID_CCRC0x0B/* CompactPCI Central Resource Control */
295#define PCI_CAP_ID_HOTPLUG0x0C/* PCI hot-plug */
296#define PCI_CAP_ID_SSVID0x0D/* Bridge subsystem vendor/device ID */
297#define PCI_CAP_ID_AGP30x0E/* AGP 8x */
298#define PCI_CAP_ID_SECURE0x0F/* Secure device (?) */
299#define PCI_CAP_ID_EXP0x10/* PCI Express */
300#define PCI_CAP_ID_MSIX0x11/* MSI-X */
301#define PCI_CAP_ID_SATA0x12/* Serial-ATA HBA */
302#define PCI_CAP_ID_AF0x13/* Advanced features of PCI devices integrated in PCIe root cplx */
303#define PCI_CAP_LIST_NEXT1/* Next capability in the list */
304#define PCI_CAP_FLAGS2/* Capability defined flags (16 bits) */
305#define PCI_CAP_SIZEOF4
306
307/* Capabilities residing in the PCI Express extended configuration space */
308
309#define PCI_EXT_CAP_ID_AER0x01/* Advanced Error Reporting */
310#define PCI_EXT_CAP_ID_VC0x02/* Virtual Channel */
311#define PCI_EXT_CAP_ID_DSN0x03/* Device Serial Number */
312#define PCI_EXT_CAP_ID_PB0x04/* Power Budgeting */
313#define PCI_EXT_CAP_ID_RCLINK0x05/* Root Complex Link Declaration */
314#define PCI_EXT_CAP_ID_RCILINK0x06/* Root Complex Internal Link Declaration */
315#define PCI_EXT_CAP_ID_RCECOLL0x07/* Root Complex Event Collector */
316#define PCI_EXT_CAP_ID_MFVC0x08/* Multi-Function Virtual Channel */
317#define PCI_EXT_CAP_ID_RBCB0x0a/* Root Bridge Control Block */
318#define PCI_EXT_CAP_ID_VNDR0x0b/* Vendor specific */
319#define PCI_EXT_CAP_ID_ACS0x0d/* Access Controls */
320#define PCI_EXT_CAP_ID_ARI0x0e/* Alternative Routing-ID Interpretation */
321#define PCI_EXT_CAP_ID_ATS0x0f/* Address Translation Service */
322#define PCI_EXT_CAP_ID_SRIOV0x10/* Single Root I/O Virtualization */
323
324/* Power Management Registers */
325
326#define PCI_PM_CAP_VER_MASK0x0007/* Version (2=PM1.1) */
327#define PCI_PM_CAP_PME_CLOCK0x0008/* Clock required for PME generation */
328#define PCI_PM_CAP_DSI0x0020/* Device specific initialization required */
329#define PCI_PM_CAP_AUX_C_MASK0x01c0/* Maximum aux current required in D3cold */
330#define PCI_PM_CAP_D10x0200/* D1 power state support */
331#define PCI_PM_CAP_D20x0400/* D2 power state support */
332#define PCI_PM_CAP_PME_D00x0800/* PME can be asserted from D0 */
333#define PCI_PM_CAP_PME_D10x1000/* PME can be asserted from D1 */
334#define PCI_PM_CAP_PME_D20x2000/* PME can be asserted from D2 */
335#define PCI_PM_CAP_PME_D3_HOT0x4000/* PME can be asserted from D3hot */
336#define PCI_PM_CAP_PME_D3_COLD0x8000/* PME can be asserted from D3cold */
337#define PCI_PM_CTRL4/* PM control and status register */
338#define PCI_PM_CTRL_STATE_MASK0x0003/* Current power state (D0 to D3) */
339#define PCI_PM_CTRL_PME_ENABLE0x0100/* PME pin enable */
340#define PCI_PM_CTRL_DATA_SEL_MASK0x1e00/* PM table data index */
341#define PCI_PM_CTRL_DATA_SCALE_MASK0x6000/* PM table data scaling factor */
342#define PCI_PM_CTRL_PME_STATUS0x8000/* PME pin status */
343#define PCI_PM_PPB_EXTENSIONS6/* PPB support extensions */
344#define PCI_PM_PPB_B2_B30x40/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
345#define PCI_PM_BPCC_ENABLE0x80/* Secondary bus is power managed */
346#define PCI_PM_DATA_REGISTER7/* PM table contents read here */
347#define PCI_PM_SIZEOF8
348
349/* AGP registers */
350
351#define PCI_AGP_VERSION2/* BCD version number */
352#define PCI_AGP_RFU3/* Rest of capability flags */
353#define PCI_AGP_STATUS4/* Status register */
354#define PCI_AGP_STATUS_RQ_MASK0xff000000/* Maximum number of requests - 1 */
355#define PCI_AGP_STATUS_ISOCH0x10000/* Isochronous transactions supported */
356#define PCI_AGP_STATUS_ARQSZ_MASK0xe000/* log2(optimum async req size in bytes) - 4 */
357#define PCI_AGP_STATUS_CAL_MASK0x1c00/* Calibration cycle timing */
358#define PCI_AGP_STATUS_SBA0x0200/* Sideband addressing supported */
359#define PCI_AGP_STATUS_ITA_COH0x0100/* In-aperture accesses always coherent */
360#define PCI_AGP_STATUS_GART640x0080/* 64-bit GART entries supported */
361#define PCI_AGP_STATUS_HTRANS0x0040/* If 0, core logic can xlate host CPU accesses thru aperture */
362#define PCI_AGP_STATUS_64BIT0x0020/* 64-bit addressing cycles supported */
363#define PCI_AGP_STATUS_FW0x0010/* Fast write transfers supported */
364#define PCI_AGP_STATUS_AGP30x0008/* AGP3 mode supported */
365#define PCI_AGP_STATUS_RATE40x0004/* 4x transfer rate supported (RFU in AGP3 mode) */
366#define PCI_AGP_STATUS_RATE20x0002/* 2x transfer rate supported (8x in AGP3 mode) */
367#define PCI_AGP_STATUS_RATE10x0001/* 1x transfer rate supported (4x in AGP3 mode) */
368#define PCI_AGP_COMMAND8/* Control register */
369#define PCI_AGP_COMMAND_RQ_MASK0xff000000 /* Master: Maximum number of requests */
370#define PCI_AGP_COMMAND_ARQSZ_MASK0xe000/* log2(optimum async req size in bytes) - 4 */
371#define PCI_AGP_COMMAND_CAL_MASK0x1c00/* Calibration cycle timing */
372#define PCI_AGP_COMMAND_SBA0x0200/* Sideband addressing enabled */
373#define PCI_AGP_COMMAND_AGP0x0100/* Allow processing of AGP transactions */
374#define PCI_AGP_COMMAND_GART640x0080/* 64-bit GART entries enabled */
375#define PCI_AGP_COMMAND_64BIT0x0020/* Allow generation of 64-bit addr cycles */
376#define PCI_AGP_COMMAND_FW0x0010/* Enable FW transfers */
377#define PCI_AGP_COMMAND_RATE40x0004/* Use 4x rate (RFU in AGP3 mode) */
378#define PCI_AGP_COMMAND_RATE20x0002/* Use 2x rate (8x in AGP3 mode) */
379#define PCI_AGP_COMMAND_RATE10x0001/* Use 1x rate (4x in AGP3 mode) */
380#define PCI_AGP_SIZEOF12
381
382/* Vital Product Data */
383
384#define PCI_VPD_ADDR2/* Address to access (15 bits!) */
385#define PCI_VPD_ADDR_MASK0x7fff/* Address mask */
386#define PCI_VPD_ADDR_F0x8000/* Write 0, 1 indicates completion */
387#define PCI_VPD_DATA4/* 32-bits of data returned here */
388
389/* Slot Identification */
390
391#define PCI_SID_ESR2/* Expansion Slot Register */
392#define PCI_SID_ESR_NSLOTS0x1f/* Number of expansion slots available */
393#define PCI_SID_ESR_FIC0x20/* First In Chassis Flag */
394#define PCI_SID_CHASSIS_NR3/* Chassis Number */
395
396/* Message Signaled Interrupts registers */
397
398#define PCI_MSI_FLAGS2/* Various flags */
399#define PCI_MSI_FLAGS_MASK_BIT0x100/* interrupt masking & reporting supported */
400#define PCI_MSI_FLAGS_64BIT0x080/* 64-bit addresses allowed */
401#define PCI_MSI_FLAGS_QSIZE0x070/* Message queue size configured */
402#define PCI_MSI_FLAGS_QMASK0x00e/* Maximum queue size available */
403#define PCI_MSI_FLAGS_ENABLE0x001/* MSI feature enabled */
404#define PCI_MSI_RFU3/* Rest of capability flags */
405#define PCI_MSI_ADDRESS_LO4/* Lower 32 bits */
406#define PCI_MSI_ADDRESS_HI8/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
407#define PCI_MSI_DATA_328/* 16 bits of data for 32-bit devices */
408#define PCI_MSI_DATA_6412/* 16 bits of data for 64-bit devices */
409#define PCI_MSI_MASK_BIT_3212/* per-vector masking for 32-bit devices */
410#define PCI_MSI_MASK_BIT_6416/* per-vector masking for 64-bit devices */
411#define PCI_MSI_PENDING_3216/* per-vector interrupt pending for 32-bit devices */
412#define PCI_MSI_PENDING_6420/* per-vector interrupt pending for 64-bit devices */
413
414/* PCI-X */
415#define PCI_PCIX_COMMAND 2 /* Command register offset */
416#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
417#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
418#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
419#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
420#define PCI_PCIX_COMMAND_RESERVED 0xf80
421#define PCI_PCIX_STATUS 4 /* Status register offset */
422#define PCI_PCIX_STATUS_FUNCTION 0x00000007
423#define PCI_PCIX_STATUS_DEVICE 0x000000f8
424#define PCI_PCIX_STATUS_BUS 0x0000ff00
425#define PCI_PCIX_STATUS_64BIT 0x00010000
426#define PCI_PCIX_STATUS_133MHZ 0x00020000
427#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
428#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
429#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
430#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
431#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
432#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
433#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
434#define PCI_PCIX_STATUS_266MHZ0x40000000 /* 266 MHz capable */
435#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
436#define PCI_PCIX_SIZEOF4
437
438/* PCI-X Bridges */
439#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
440#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
441#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
442#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
443#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
444#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
445#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
446#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
447#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
448#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
449#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
450#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
451#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
452#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
453#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
454#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
455#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
456#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
457#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
458#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
459#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
460#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
461#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
462#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
463#define PCI_PCIX_BRIDGE_SIZEOF 12
464
465/* PCI Express */
466#define PCI_EXP_FLAGS0x2/* Capabilities register */
467#define PCI_EXP_FLAGS_VERS0x000f/* Capability version */
468#define PCI_EXP_FLAGS_TYPE0x00f0/* Device/Port type */
469#define PCI_EXP_TYPE_ENDPOINT0x0/* Express Endpoint */
470#define PCI_EXP_TYPE_LEG_END0x1/* Legacy Endpoint */
471#define PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
472#define PCI_EXP_TYPE_UPSTREAM0x5/* Upstream Port */
473#define PCI_EXP_TYPE_DOWNSTREAM 0x6/* Downstream Port */
474#define PCI_EXP_TYPE_PCI_BRIDGE 0x7/* PCI/PCI-X Bridge */
475#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8/* PCI/PCI-X to PCIE Bridge */
476#define PCI_EXP_TYPE_ROOT_INT_EP 0x9/* Root Complex Integrated Endpoint */
477#define PCI_EXP_TYPE_ROOT_EC 0xa/* Root Complex Event Collector */
478#define PCI_EXP_FLAGS_SLOT0x0100/* Slot implemented */
479#define PCI_EXP_FLAGS_IRQ0x3e00/* Interrupt message number */
480#define PCI_EXP_DEVCAP0x4/* Device capabilities */
481#define PCI_EXP_DEVCAP_PAYLOAD0x07/* Max_Payload_Size */
482#define PCI_EXP_DEVCAP_PHANTOM0x18/* Phantom functions */
483#define PCI_EXP_DEVCAP_EXT_TAG0x20/* Extended tags */
484#define PCI_EXP_DEVCAP_L0S0x1c0/* L0s Acceptable Latency */
485#define PCI_EXP_DEVCAP_L10xe00/* L1 Acceptable Latency */
486#define PCI_EXP_DEVCAP_ATN_BUT0x1000/* Attention Button Present */
487#define PCI_EXP_DEVCAP_ATN_IND0x2000/* Attention Indicator Present */
488#define PCI_EXP_DEVCAP_PWR_IND0x4000/* Power Indicator Present */
489#define PCI_EXP_DEVCAP_RBE0x8000/* Role-Based Error Reporting */
490#define PCI_EXP_DEVCAP_PWR_VAL0x3fc0000 /* Slot Power Limit Value */
491#define PCI_EXP_DEVCAP_PWR_SCL0xc000000 /* Slot Power Limit Scale */
492#define PCI_EXP_DEVCAP_FLRESET0x10000000 /* Function-Level Reset */
493#define PCI_EXP_DEVCTL0x8/* Device Control */
494#define PCI_EXP_DEVCTL_CERE0x0001/* Correctable Error Reporting En. */
495#define PCI_EXP_DEVCTL_NFERE0x0002/* Non-Fatal Error Reporting Enable */
496#define PCI_EXP_DEVCTL_FERE0x0004/* Fatal Error Reporting Enable */
497#define PCI_EXP_DEVCTL_URRE0x0008/* Unsupported Request Reporting En. */
498#define PCI_EXP_DEVCTL_RELAXED0x0010/* Enable Relaxed Ordering */
499#define PCI_EXP_DEVCTL_PAYLOAD0x00e0/* Max_Payload_Size */
500#define PCI_EXP_DEVCTL_EXT_TAG0x0100/* Extended Tag Field Enable */
501#define PCI_EXP_DEVCTL_PHANTOM0x0200/* Phantom Functions Enable */
502#define PCI_EXP_DEVCTL_AUX_PME0x0400/* Auxiliary Power PM Enable */
503#define PCI_EXP_DEVCTL_NOSNOOP0x0800/* Enable No Snoop */
504#define PCI_EXP_DEVCTL_READRQ0x7000/* Max_Read_Request_Size */
505#define PCI_EXP_DEVCTL_BCRE0x8000/* Bridge Configuration Retry Enable */
506#define PCI_EXP_DEVCTL_FLRESET0x8000/* Function-Level Reset [bit shared with BCRE] */
507#define PCI_EXP_DEVSTA0xa/* Device Status */
508#define PCI_EXP_DEVSTA_CED0x01/* Correctable Error Detected */
509#define PCI_EXP_DEVSTA_NFED0x02/* Non-Fatal Error Detected */
510#define PCI_EXP_DEVSTA_FED0x04/* Fatal Error Detected */
511#define PCI_EXP_DEVSTA_URD0x08/* Unsupported Request Detected */
512#define PCI_EXP_DEVSTA_AUXPD0x10/* AUX Power Detected */
513#define PCI_EXP_DEVSTA_TRPND0x20/* Transactions Pending */
514#define PCI_EXP_LNKCAP0xc/* Link Capabilities */
515#define PCI_EXP_LNKCAP_SPEED0x0000f/* Maximum Link Speed */
516#define PCI_EXP_LNKCAP_WIDTH0x003f0/* Maximum Link Width */
517#define PCI_EXP_LNKCAP_ASPM0x00c00/* Active State Power Management */
518#define PCI_EXP_LNKCAP_L0S0x07000/* L0s Acceptable Latency */
519#define PCI_EXP_LNKCAP_L10x38000/* L1 Acceptable Latency */
520#define PCI_EXP_LNKCAP_CLOCKPM0x40000/* Clock Power Management */
521#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
522#define PCI_EXP_LNKCAP_DLLA0x100000 /* Data Link Layer Active Reporting */
523#define PCI_EXP_LNKCAP_LBNC0x200000 /* Link Bandwidth Notification Capability */
524#define PCI_EXP_LNKCAP_PORT0xff000000 /* Port Number */
525#define PCI_EXP_LNKCTL0x10/* Link Control */
526#define PCI_EXP_LNKCTL_ASPM0x0003/* ASPM Control */
527#define PCI_EXP_LNKCTL_RCB0x0008/* Read Completion Boundary */
528#define PCI_EXP_LNKCTL_DISABLE0x0010/* Link Disable */
529#define PCI_EXP_LNKCTL_RETRAIN0x0020/* Retrain Link */
530#define PCI_EXP_LNKCTL_CLOCK0x0040/* Common Clock Configuration */
531#define PCI_EXP_LNKCTL_XSYNCH0x0080/* Extended Synch */
532#define PCI_EXP_LNKCTL_CLOCKPM0x0100/* Clock Power Management */
533#define PCI_EXP_LNKCTL_HWAUTWD0x0200/* Hardware Autonomous Width Disable */
534#define PCI_EXP_LNKCTL_BWMIE0x0400/* Bandwidth Mgmt Interrupt Enable */
535#define PCI_EXP_LNKCTL_AUTBWIE0x0800/* Autonomous Bandwidth Mgmt Interrupt Enable */
536#define PCI_EXP_LNKSTA0x12/* Link Status */
537#define PCI_EXP_LNKSTA_SPEED0x000f/* Negotiated Link Speed */
538#define PCI_EXP_LNKSTA_WIDTH0x03f0/* Negotiated Link Width */
539#define PCI_EXP_LNKSTA_TR_ERR0x0400/* Training Error (obsolete) */
540#define PCI_EXP_LNKSTA_TRAIN0x0800/* Link Training */
541#define PCI_EXP_LNKSTA_SL_CLK0x1000/* Slot Clock Configuration */
542#define PCI_EXP_LNKSTA_DL_ACT0x2000/* Data Link Layer in DL_Active State */
543#define PCI_EXP_LNKSTA_BWMGMT0x4000/* Bandwidth Mgmt Status */
544#define PCI_EXP_LNKSTA_AUTBW0x8000/* Autonomous Bandwidth Mgmt Status */
545#define PCI_EXP_SLTCAP0x14/* Slot Capabilities */
546#define PCI_EXP_SLTCAP_ATNB0x0001/* Attention Button Present */
547#define PCI_EXP_SLTCAP_PWRC0x0002/* Power Controller Present */
548#define PCI_EXP_SLTCAP_MRL0x0004/* MRL Sensor Present */
549#define PCI_EXP_SLTCAP_ATNI0x0008/* Attention Indicator Present */
550#define PCI_EXP_SLTCAP_PWRI0x0010/* Power Indicator Present */
551#define PCI_EXP_SLTCAP_HPS0x0020/* Hot-Plug Surprise */
552#define PCI_EXP_SLTCAP_HPC0x0040/* Hot-Plug Capable */
553#define PCI_EXP_SLTCAP_PWR_VAL0x00007f80 /* Slot Power Limit Value */
554#define PCI_EXP_SLTCAP_PWR_SCL0x00018000 /* Slot Power Limit Scale */
555#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
556#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
557#define PCI_EXP_SLTCAP_PSN0xfff80000 /* Physical Slot Number */
558#define PCI_EXP_SLTCTL0x18/* Slot Control */
559#define PCI_EXP_SLTCTL_ATNB0x0001/* Attention Button Pressed Enable */
560#define PCI_EXP_SLTCTL_PWRF0x0002/* Power Fault Detected Enable */
561#define PCI_EXP_SLTCTL_MRLS0x0004/* MRL Sensor Changed Enable */
562#define PCI_EXP_SLTCTL_PRSD0x0008/* Presence Detect Changed Enable */
563#define PCI_EXP_SLTCTL_CMDC0x0010/* Command Completed Interrupt Enable */
564#define PCI_EXP_SLTCTL_HPIE0x0020/* Hot-Plug Interrupt Enable */
565#define PCI_EXP_SLTCTL_ATNI0x00c0/* Attention Indicator Control */
566#define PCI_EXP_SLTCTL_PWRI0x0300/* Power Indicator Control */
567#define PCI_EXP_SLTCTL_PWRC0x0400/* Power Controller Control */
568#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
569#define PCI_EXP_SLTCTL_LLCHG0x1000/* Data Link Layer State Changed Enable */
570#define PCI_EXP_SLTSTA0x1a/* Slot Status */
571#define PCI_EXP_SLTSTA_ATNB0x0001/* Attention Button Pressed */
572#define PCI_EXP_SLTSTA_PWRF0x0002/* Power Fault Detected */
573#define PCI_EXP_SLTSTA_MRLS0x0004/* MRL Sensor Changed */
574#define PCI_EXP_SLTSTA_PRSD0x0008/* Presence Detect Changed */
575#define PCI_EXP_SLTSTA_CMDC0x0010/* Command Completed */
576#define PCI_EXP_SLTSTA_MRL_ST0x0020/* MRL Sensor State */
577#define PCI_EXP_SLTSTA_PRES0x0040/* Presence Detect State */
578#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
579#define PCI_EXP_SLTSTA_LLCHG0x0100/* Data Link Layer State Changed */
580#define PCI_EXP_RTCTL0x1c/* Root Control */
581#define PCI_EXP_RTCTL_SECEE0x0001/* System Error on Correctable Error */
582#define PCI_EXP_RTCTL_SENFEE0x0002/* System Error on Non-Fatal Error */
583#define PCI_EXP_RTCTL_SEFEE0x0004/* System Error on Fatal Error */
584#define PCI_EXP_RTCTL_PMEIE0x0008/* PME Interrupt Enable */
585#define PCI_EXP_RTCTL_CRSVIS0x0010/* Configuration Request Retry Status Visible to SW */
586#define PCI_EXP_RTCAP0x1e/* Root Capabilities */
587#define PCI_EXP_RTCAP_CRSVIS0x0010/* Configuration Request Retry Status Visible to SW */
588#define PCI_EXP_RTSTA0x20/* Root Status */
589#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
590#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
591#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
592#define PCI_EXP_DEVCAP20x24/* Device capabilities 2 */
593#define PCI_EXP_DEVCTL20x28/* Device Control */
594#define PCI_EXP_DEV2_TIMEOUT_RANGE(x)((x) & 0xf) /* Completion Timeout Ranges Supported */
595#define PCI_EXP_DEV2_TIMEOUT_VALUE(x)((x) & 0xf) /* Completion Timeout Value */
596#define PCI_EXP_DEV2_TIMEOUT_DIS0x0010/* Completion Timeout Disable Supported */
597#define PCI_EXP_DEV2_ARI0x0020/* ARI Forwarding */
598#define PCI_EXP_DEVSTA20x2a/* Device Status */
599#define PCI_EXP_LNKCAP20x2c/* Link Capabilities */
600#define PCI_EXP_LNKCTL20x30/* Link Control */
601#define PCI_EXP_LNKCTL2_SPEED(x)((x) & 0xf) /* Target Link Speed */
602#define PCI_EXP_LNKCTL2_CMPLNC0x0010/* Enter Compliance */
603#define PCI_EXP_LNKCTL2_SPEED_DIS0x0020/* Hardware Autonomous Speed Disable */
604#define PCI_EXP_LNKCTL2_DEEMPHASIS(x)(((x) >> 6) & 1) /* Selectable De-emphasis */
605#define PCI_EXP_LNKCTL2_MARGIN(x)(((x) >> 7) & 7) /* Transmit Margin */
606#define PCI_EXP_LNKCTL2_MOD_CMPLNC0x0400/* Enter Modified Compliance */
607#define PCI_EXP_LNKCTL2_CMPLNC_SOS0x0800/* Compliance SOS */
608#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
609#define PCI_EXP_LNKSTA20x32/* Link Status */
610#define PCI_EXP_LINKSTA2_DEEMPHASIS(x)((x) & 1)/* Current De-emphasis Level */
611#define PCI_EXP_SLTCAP20x34/* Slot Capabilities */
612#define PCI_EXP_SLTCTL20x38/* Slot Control */
613#define PCI_EXP_SLTSTA20x3a/* Slot Status */
614
615/* MSI-X */
616#define PCI_MSIX_ENABLE0x8000
617#define PCI_MSIX_MASK0x4000
618#define PCI_MSIX_TABSIZE0x03ff
619#define PCI_MSIX_TABLE4
620#define PCI_MSIX_PBA8
621#define PCI_MSIX_BIR0x7
622
623/* Subsystem vendor/device ID for PCI bridges */
624#define PCI_SSVID_VENDOR4
625#define PCI_SSVID_DEVICE6
626
627/* Advanced Error Reporting */
628#define PCI_ERR_UNCOR_STATUS4/* Uncorrectable Error Status */
629#define PCI_ERR_UNC_TRAIN0x00000001/* Undefined in PCIe rev1.1 & 2.0 spec */
630#define PCI_ERR_UNC_DLP0x00000010/* Data Link Protocol */
631#define PCI_ERR_UNC_SDES0x00000020/* Surprise Down Error */
632#define PCI_ERR_UNC_POISON_TLP0x00001000/* Poisoned TLP */
633#define PCI_ERR_UNC_FCP0x00002000/* Flow Control Protocol */
634#define PCI_ERR_UNC_COMP_TIME0x00004000/* Completion Timeout */
635#define PCI_ERR_UNC_COMP_ABORT0x00008000/* Completer Abort */
636#define PCI_ERR_UNC_UNX_COMP0x00010000/* Unexpected Completion */
637#define PCI_ERR_UNC_RX_OVER0x00020000/* Receiver Overflow */
638#define PCI_ERR_UNC_MALF_TLP0x00040000/* Malformed TLP */
639#define PCI_ERR_UNC_ECRC0x00080000/* ECRC Error Status */
640#define PCI_ERR_UNC_UNSUP0x00100000/* Unsupported Request */
641#define PCI_ERR_UNC_ACS_VIOL0x00200000/* ACS Violation */
642#define PCI_ERR_UNCOR_MASK8/* Uncorrectable Error Mask */
643/* Same bits as above */
644#define PCI_ERR_UNCOR_SEVER12/* Uncorrectable Error Severity */
645/* Same bits as above */
646#define PCI_ERR_COR_STATUS16/* Correctable Error Status */
647#define PCI_ERR_COR_RCVR0x00000001/* Receiver Error Status */
648#define PCI_ERR_COR_BAD_TLP0x00000040/* Bad TLP Status */
649#define PCI_ERR_COR_BAD_DLLP0x00000080/* Bad DLLP Status */
650#define PCI_ERR_COR_REP_ROLL0x00000100/* REPLAY_NUM Rollover */
651#define PCI_ERR_COR_REP_TIMER0x00001000/* Replay Timer Timeout */
652#define PCI_ERR_COR_REP_ANFE0x00002000/* Advisory Non-Fatal Error */
653#define PCI_ERR_COR_MASK20/* Correctable Error Mask */
654/* Same bits as above */
655#define PCI_ERR_CAP24/* Advanced Error Capabilities */
656#define PCI_ERR_CAP_FEP(x)((x) & 31)/* First Error Pointer */
657#define PCI_ERR_CAP_ECRC_GENC0x00000020/* ECRC Generation Capable */
658#define PCI_ERR_CAP_ECRC_GENE0x00000040/* ECRC Generation Enable */
659#define PCI_ERR_CAP_ECRC_CHKC0x00000080/* ECRC Check Capable */
660#define PCI_ERR_CAP_ECRC_CHKE0x00000100/* ECRC Check Enable */
661#define PCI_ERR_HEADER_LOG28/* Header Log Register (16 bytes) */
662#define PCI_ERR_ROOT_COMMAND44/* Root Error Command */
663#define PCI_ERR_ROOT_STATUS48
664#define PCI_ERR_ROOT_COR_SRC52
665#define PCI_ERR_ROOT_SRC54
666
667/* Virtual Channel */
668#define PCI_VC_PORT_REG14
669#define PCI_VC_PORT_REG28
670#define PCI_VC_PORT_CTRL12
671#define PCI_VC_PORT_STATUS14
672#define PCI_VC_RES_CAP16
673#define PCI_VC_RES_CTRL20
674#define PCI_VC_RES_STATUS26
675
676/* Power Budgeting */
677#define PCI_PWR_DSR4/* Data Select Register */
678#define PCI_PWR_DATA8/* Data Register */
679#define PCI_PWR_DATA_BASE(x)((x) & 0xff) /* Base Power */
680#define PCI_PWR_DATA_SCALE(x)(((x) >> 8) & 3) /* Data Scale */
681#define PCI_PWR_DATA_PM_SUB(x)(((x) >> 10) & 7) /* PM Sub State */
682#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
683#define PCI_PWR_DATA_TYPE(x)(((x) >> 15) & 7) /* Type */
684#define PCI_PWR_DATA_RAIL(x)(((x) >> 18) & 7) /* Power Rail */
685#define PCI_PWR_CAP12/* Capability */
686#define PCI_PWR_CAP_BUDGET(x)((x) & 1)/* Included in system budget */
687
688/* Access Control Services */
689#define PCI_ACS_CAP0x04/* ACS Capability Register */
690#define PCI_ACS_CAP_VALID0x0001/* ACS Source Validation */
691#define PCI_ACS_CAP_BLOCK0x0002/* ACS Translation Blocking */
692#define PCI_ACS_CAP_REQ_RED0x0004/* ACS P2P Request Redirect */
693#define PCI_ACS_CAP_CMPLT_RED0x0008/* ACS P2P Completion Redirect */
694#define PCI_ACS_CAP_FORWARD0x0010/* ACS Upstream Forwarding */
695#define PCI_ACS_CAP_EGRESS0x0020/* ACS P2P Egress Control */
696#define PCI_ACS_CAP_TRANS0x0040/* ACS Direct Translated P2P */
697#define PCI_ACS_CAP_VECTOR(x)(((x) >> 8) & 0xff) /* Egress Control Vector Size */
698#define PCI_ACS_CTRL0x06/* ACS Control Register */
699#define PCI_ACS_CTRL_VALID0x0001/* ACS Source Validation Enable */
700#define PCI_ACS_CTRL_BLOCK0x0002/* ACS Translation Blocking Enable */
701#define PCI_ACS_CTRL_REQ_RED0x0004/* ACS P2P Request Redirect Enable */
702#define PCI_ACS_CTRL_CMPLT_RED0x0008/* ACS P2P Completion Redirect Enable */
703#define PCI_ACS_CTRL_FORWARD0x0010/* ACS Upstream Forwarding Enable */
704#define PCI_ACS_CTRL_EGRESS0x0020/* ACS P2P Egress Control Enable */
705#define PCI_ACS_CTRL_TRANS0x0040/* ACS Direct Translated P2P Enable */
706#define PCI_ACS_EGRESS_CTRL0x08/* Egress Control Vector */
707
708/* Alternative Routing-ID Interpretation */
709#define PCI_ARI_CAP0x04/* ARI Capability Register */
710#define PCI_ARI_CAP_MFVC0x0001/* MFVC Function Groups Capability */
711#define PCI_ARI_CAP_ACS0x0002/* ACS Function Groups Capability */
712#define PCI_ARI_CAP_NFN(x)(((x) >> 8) & 0xff) /* Next Function Number */
713#define PCI_ARI_CTRL0x06/* ARI Control Register */
714#define PCI_ARI_CTRL_MFVC0x0001/* MFVC Function Groups Enable */
715#define PCI_ARI_CTRL_ACS0x0002/* ACS Function Groups Enable */
716#define PCI_ARI_CTRL_FG(x)(((x) >> 4) & 7) /* Function Group */
717
718/* Address Translation Service */
719#define PCI_ATS_CAP0x04/* ATS Capability Register */
720#define PCI_ATS_CAP_IQD(x)((x) & 0x1f) /* Invalidate Queue Depth */
721#define PCI_ATS_CTRL0x06/* ATS Control Register */
722#define PCI_ATS_CTRL_STU(x)((x) & 0x1f) /* Smallest Translation Unit */
723#define PCI_ATS_CTRL_ENABLE0x8000/* ATS Enable */
724
725/* Single Root I/O Virtualization */
726#define PCI_IOV_CAP0x04/* SR-IOV Capability Register */
727#define PCI_IOV_CAP_VFM0x00000001 /* VF Migration Capable */
728#define PCI_IOV_CAP_IMN(x)((x) >> 21) /* VF Migration Interrupt Message Number */
729#define PCI_IOV_CTRL0x08/* SR-IOV Control Register */
730#define PCI_IOV_CTRL_VFE0x0001/* VF Enable */
731#define PCI_IOV_CTRL_VFME0x0002/* VF Migration Enable */
732#define PCI_IOV_CTRL_VFMIE0x0004/* VF Migration Interrupt Enable */
733#define PCI_IOV_CTRL_MSE0x0008/* VF MSE */
734#define PCI_IOV_CTRL_ARI0x0010/* ARI Capable Hierarchy */
735#define PCI_IOV_STATUS0x0a/* SR-IOV Status Register */
736#define PCI_IOV_STATUS_MS0x0001/* VF Migration Status */
737#define PCI_IOV_INITIALVF0x0c/* Number of VFs that are initially associated */
738#define PCI_IOV_TOTALVF0x0e/* Maximum number of VFs that could be associated */
739#define PCI_IOV_NUMVF0x10/* Number of VFs that are available */
740#define PCI_IOV_FDL0x12/* Function Dependency Link */
741#define PCI_IOV_OFFSET0x14/* First VF Offset */
742#define PCI_IOV_STRIDE0x16/* Routing ID offset from one VF to the next one */
743#define PCI_IOV_DID0x1a/* VF Device ID */
744#define PCI_IOV_SUPPS0x1c/* Supported Page Sizes */
745#define PCI_IOV_SYSPS0x20/* System Page Size */
746#define PCI_IOV_BAR_BASE0x24/* VF BAR0, VF BAR1, ... VF BAR5 */
747#define PCI_IOV_NUM_BAR6/* Number of VF BARs */
748#define PCI_IOV_MSAO0x3c/* VF Migration State Array Offset */
749#define PCI_IOV_MSA_BIR(x)((x) & 7) /* VF Migration State BIR */
750#define PCI_IOV_MSA_OFFSET(x)((x) & 0xfffffff8) /* VF Migration State Offset */
751
752/*
753 * The PCI interface treats multi-function devices as independent
754 * devices. The slot/function address of each device is encoded
755 * in a single byte as follows:
756 *
757 *7:3 = slot
758 *2:0 = function
759 */
760#define PCI_DEVFN(slot,func)((((slot) & 0x1f) << 3) | ((func) & 0x07))
761#define PCI_SLOT(devfn)(((devfn) >> 3) & 0x1f)
762#define PCI_FUNC(devfn)((devfn) & 0x07)
763
764/* Device classes and subclasses */
765
766#define PCI_CLASS_NOT_DEFINED0x0000
767#define PCI_CLASS_NOT_DEFINED_VGA0x0001
768
769#define PCI_BASE_CLASS_STORAGE0x01
770#define PCI_CLASS_STORAGE_SCSI0x0100
771#define PCI_CLASS_STORAGE_IDE0x0101
772#define PCI_CLASS_STORAGE_FLOPPY0x0102
773#define PCI_CLASS_STORAGE_IPI0x0103
774#define PCI_CLASS_STORAGE_RAID0x0104
775#define PCI_CLASS_STORAGE_ATA0x0105
776#define PCI_CLASS_STORAGE_SATA0x0106
777#define PCI_CLASS_STORAGE_SAS0x0107
778#define PCI_CLASS_STORAGE_OTHER0x0180
779
780#define PCI_BASE_CLASS_NETWORK0x02
781#define PCI_CLASS_NETWORK_ETHERNET0x0200
782#define PCI_CLASS_NETWORK_TOKEN_RING0x0201
783#define PCI_CLASS_NETWORK_FDDI0x0202
784#define PCI_CLASS_NETWORK_ATM0x0203
785#define PCI_CLASS_NETWORK_ISDN0x0204
786#define PCI_CLASS_NETWORK_OTHER0x0280
787
788#define PCI_BASE_CLASS_DISPLAY0x03
789#define PCI_CLASS_DISPLAY_VGA0x0300
790#define PCI_CLASS_DISPLAY_XGA0x0301
791#define PCI_CLASS_DISPLAY_3D0x0302
792#define PCI_CLASS_DISPLAY_OTHER0x0380
793
794#define PCI_BASE_CLASS_MULTIMEDIA0x04
795#define PCI_CLASS_MULTIMEDIA_VIDEO0x0400
796#define PCI_CLASS_MULTIMEDIA_AUDIO0x0401
797#define PCI_CLASS_MULTIMEDIA_PHONE0x0402
798#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV0x0403
799#define PCI_CLASS_MULTIMEDIA_OTHER0x0480
800
801#define PCI_BASE_CLASS_MEMORY0x05
802#define PCI_CLASS_MEMORY_RAM0x0500
803#define PCI_CLASS_MEMORY_FLASH0x0501
804#define PCI_CLASS_MEMORY_OTHER0x0580
805
806#define PCI_BASE_CLASS_BRIDGE0x06
807#define PCI_CLASS_BRIDGE_HOST0x0600
808#define PCI_CLASS_BRIDGE_ISA0x0601
809#define PCI_CLASS_BRIDGE_EISA0x0602
810#define PCI_CLASS_BRIDGE_MC0x0603
811#define PCI_CLASS_BRIDGE_PCI0x0604
812#define PCI_CLASS_BRIDGE_PCMCIA0x0605
813#define PCI_CLASS_BRIDGE_NUBUS0x0606
814#define PCI_CLASS_BRIDGE_CARDBUS0x0607
815#define PCI_CLASS_BRIDGE_RACEWAY0x0608
816#define PCI_CLASS_BRIDGE_PCI_SEMI0x0609
817#define PCI_CLASS_BRIDGE_IB_TO_PCI0x060a
818#define PCI_CLASS_BRIDGE_OTHER0x0680
819
820#define PCI_BASE_CLASS_COMMUNICATION0x07
821#define PCI_CLASS_COMMUNICATION_SERIAL0x0700
822#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
823#define PCI_CLASS_COMMUNICATION_MSERIAL0x0702
824#define PCI_CLASS_COMMUNICATION_MODEM0x0703
825#define PCI_CLASS_COMMUNICATION_OTHER0x0780
826
827#define PCI_BASE_CLASS_SYSTEM0x08
828#define PCI_CLASS_SYSTEM_PIC0x0800
829#define PCI_CLASS_SYSTEM_DMA0x0801
830#define PCI_CLASS_SYSTEM_TIMER0x0802
831#define PCI_CLASS_SYSTEM_RTC0x0803
832#define PCI_CLASS_SYSTEM_PCI_HOTPLUG0x0804
833#define PCI_CLASS_SYSTEM_OTHER0x0880
834
835#define PCI_BASE_CLASS_INPUT0x09
836#define PCI_CLASS_INPUT_KEYBOARD0x0900
837#define PCI_CLASS_INPUT_PEN0x0901
838#define PCI_CLASS_INPUT_MOUSE0x0902
839#define PCI_CLASS_INPUT_SCANNER0x0903
840#define PCI_CLASS_INPUT_GAMEPORT0x0904
841#define PCI_CLASS_INPUT_OTHER0x0980
842
843#define PCI_BASE_CLASS_DOCKING0x0a
844#define PCI_CLASS_DOCKING_GENERIC0x0a00
845#define PCI_CLASS_DOCKING_OTHER0x0a80
846
847#define PCI_BASE_CLASS_PROCESSOR0x0b
848#define PCI_CLASS_PROCESSOR_3860x0b00
849#define PCI_CLASS_PROCESSOR_4860x0b01
850#define PCI_CLASS_PROCESSOR_PENTIUM0x0b02
851#define PCI_CLASS_PROCESSOR_ALPHA0x0b10
852#define PCI_CLASS_PROCESSOR_POWERPC0x0b20
853#define PCI_CLASS_PROCESSOR_MIPS0x0b30
854#define PCI_CLASS_PROCESSOR_CO0x0b40
855
856#define PCI_BASE_CLASS_SERIAL0x0c
857#define PCI_CLASS_SERIAL_FIREWIRE0x0c00
858#define PCI_CLASS_SERIAL_ACCESS0x0c01
859#define PCI_CLASS_SERIAL_SSA0x0c02
860#define PCI_CLASS_SERIAL_USB0x0c03
861#define PCI_CLASS_SERIAL_FIBER0x0c04
862#define PCI_CLASS_SERIAL_SMBUS0x0c05
863#define PCI_CLASS_SERIAL_INFINIBAND0x0c06
864
865#define PCI_BASE_CLASS_WIRELESS0x0d
866#define PCI_CLASS_WIRELESS_IRDA0x0d00
867#define PCI_CLASS_WIRELESS_CONSUMER_IR0x0d01
868#define PCI_CLASS_WIRELESS_RF0x0d10
869#define PCI_CLASS_WIRELESS_OTHER0x0d80
870
871#define PCI_BASE_CLASS_INTELLIGENT0x0e
872#define PCI_CLASS_INTELLIGENT_I2O0x0e00
873
874#define PCI_BASE_CLASS_SATELLITE0x0f
875#define PCI_CLASS_SATELLITE_TV0x0f00
876#define PCI_CLASS_SATELLITE_AUDIO0x0f01
877#define PCI_CLASS_SATELLITE_VOICE0x0f03
878#define PCI_CLASS_SATELLITE_DATA0x0f04
879
880#define PCI_BASE_CLASS_CRYPT0x10
881#define PCI_CLASS_CRYPT_NETWORK0x1000
882#define PCI_CLASS_CRYPT_ENTERTAINMENT0x1010
883#define PCI_CLASS_CRYPT_OTHER0x1080
884
885#define PCI_BASE_CLASS_SIGNAL0x11
886#define PCI_CLASS_SIGNAL_DPIO0x1100
887#define PCI_CLASS_SIGNAL_PERF_CTR0x1101
888#define PCI_CLASS_SIGNAL_SYNCHRONIZER0x1110
889#define PCI_CLASS_SIGNAL_OTHER0x1180
890
891#define PCI_CLASS_OTHERS0xff
892
893/* Several ID's we need in the library */
894
895#define PCI_VENDOR_ID_APPLE0x106b
896#define PCI_VENDOR_ID_AMD0x1002
897#define PCI_VENDOR_ID_ATI0x1002
898#define PCI_VENDOR_ID_INTEL0x8086
899#define PCI_VENDOR_ID_NVIDIA0x10de
900#define PCI_VENDOR_ID_REALTEK0x10ec
901#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS0x104c
902#define PCI_VENDOR_ID_VIA0x1106
903
904#endif /* !__LIBSAIO_PCI_H */
905

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