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Root/branches/Kabyl/i386/libsaio/spd.c

1/*
2 * spd.c - serial presence detect memory information
3 *
4 * Originally restored from pcefi10.5
5 * Dynamic mem detection original impl. by Rekursor
6 * System profiler fix and other fixes by Mozodojo.
7 */
8
9#include "libsaio.h"
10#include "pci.h"
11#include "platform.h"
12#include "spd.h"
13#include "cpu.h"
14#include "saio_internal.h"
15#include "bootstruct.h"
16#include "memvendors.h"
17
18#ifndef DEBUG_SPD
19#define DEBUG_SPD 0
20#endif
21
22#if DEBUG_SPD
23#define DBG(x...)printf(x)
24#else
25#define DBG(x...)msglog(x)
26#endif
27
28static const char *spd_memory_types[] =
29{
30"RAM", /* 00h Undefined */
31"FPM", /* 01h FPM */
32"EDO", /* 02h EDO */
33"",/* 03h PIPELINE NIBBLE */
34"SDRAM", /* 04h SDRAM */
35"",/* 05h MULTIPLEXED ROM */
36"DDR SGRAM",/* 06h SGRAM DDR */
37"DDR SDRAM",/* 07h SDRAM DDR */
38"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
39"",/* 09h Undefined */
40"",/* 0Ah Undefined */
41"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */
42};
43
44#define UNKNOWN_MEM_TYPE 2
45static uint8_t spd_mem_to_smbios[] =
46{
47UNKNOWN_MEM_TYPE, /* 00h Undefined */
48UNKNOWN_MEM_TYPE, /* 01h FPM */
49UNKNOWN_MEM_TYPE, /* 02h EDO */
50UNKNOWN_MEM_TYPE, /* 03h PIPELINE NIBBLE */
51SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */
52SMB_MEM_TYPE_ROM, /* 05h MULTIPLEXED ROM */
53SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */
54SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */
55SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */
56UNKNOWN_MEM_TYPE, /* 09h Undefined */
57UNKNOWN_MEM_TYPE, /* 0Ah Undefined */
58SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */
59};
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))
61
62#define rdtsc(low,high) \
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
64
65#define SMBHSTSTS 0
66#define SMBHSTCNT 2
67#define SMBHSTCMD 3
68#define SMBHSTADD 4
69#define SMBHSTDAT 5
70#define SBMBLKDAT 7
71
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */
73unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)
74{
75 int l1, h1, l2, h2;
76 unsigned long long t;
77
78 outb(base + SMBHSTSTS, 0x1f);// reset SMBus Controller
79 outb(base + SMBHSTDAT, 0xff);
80
81 while( inb(base + SMBHSTSTS) & 0x01);// wait until ready
82
83 outb(base + SMBHSTCMD, cmd);
84 outb(base + SMBHSTADD, (adr << 1) | 0x01 );
85 outb(base + SMBHSTCNT, 0x48 );
86
87 rdtsc(l1, h1);
88
89 while (!( inb(base + SMBHSTSTS) & 0x02))// wait til command finished
90{
91rdtsc(l2, h2);
92t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);
93if (t > 5)
94break;// break after 5ms
95 }
96 return inb(base + SMBHSTDAT);
97}
98
99/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */
100#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)
101
102int spd_indexes[] = {
103SPD_MEMORY_TYPE,
104SPD_DDR3_MEMORY_BANK,
105SPD_DDR3_MEMORY_CODE,
106SPD_NUM_ROWS,
107SPD_NUM_COLUMNS,
108SPD_NUM_DIMM_BANKS,
109SPD_NUM_BANKS_PER_SDRAM,
1104,7,8,9,12,64, /* TODO: give names to these values */
11195,96,97,98, 122,123,124,125 /* UIS */
112};
113#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))
114
115/** Read from spd *used* values only*/
116static void init_spd(char * spd, uint32_t base, int slot)
117{
118int i;
119for (i=0; i< SPD_INDEXES_SIZE; i++) {
120READ_SPD(spd, base, slot, spd_indexes[i]);
121}
122}
123
124/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,
125 have different formats, always return a valid ptr.*/
126const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)
127{
128 uint8_t bank = 0;
129 uint8_t code = 0;
130 int i = 0;
131 uint8_t * spd = (uint8_t *) slot->spd;
132
133 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3
134 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1
135 code = spd[SPD_DDR3_MEMORY_CODE];
136 for (i=0; i < VEN_MAP_SIZE; i++)
137 if (bank==vendorMap[i].bank && code==vendorMap[i].code)
138 return vendorMap[i].name;
139 }
140 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {
141 if(spd[64]==0x7f) {
142 for (i=64; i<72 && spd[i]==0x7f;i++) {
143 bank++;
144 READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop
145}
146READ_SPD(spd, base, slot_num,i);
147 code = spd[i];
148 } else {
149 code = spd[64];
150 bank = 0;
151 }
152 for (i=0; i < VEN_MAP_SIZE; i++)
153 if (bank==vendorMap[i].bank && code==vendorMap[i].code)
154 return vendorMap[i].name;
155 }
156 /* OK there is no vendor id here lets try to match the partnum if it exists */
157 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint
158 return "Unifosa";
159 return "NoName";
160}
161
162/** Get Default Memory Module Speed (no overclocking handled) */
163int getDDRspeedMhz(const char * spd)
164{
165 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {
166 switch(spd[12]) {
167 case 0x0f:
168 return 1066;
169 case 0x0c:
170 return 1333;
171 case 0x0a:
172 return 1600;
173 case 0x14:
174 default:
175 return 800;
176 }
177 }
178 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {
179 switch(spd[9]) {
180 case 0x50:
181 return 400;
182 case 0x3d:
183 return 533;
184 case 0x30:
185 return 667;
186 case 0x25:
187 default:
188 return 800;
189 }
190 }
191 return 800; // default freq for unknown types
192}
193
194#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))
195#define SLST(a) ((uint8_t)(spd[a] & 0x0f))
196
197/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */
198const char *getDDRSerial(const char* spd)
199{
200 static char asciiSerial[16];
201
202 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3
203 {
204sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));
205 }
206 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR
207 {
208sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));
209 }
210
211 return strdup(asciiSerial);
212}
213
214/** Get DDR3 or DDR2 Part Number, always return a valid ptr */
215const char * getDDRPartNum(char* spd, uint32_t base, int slot)
216{
217static char asciiPartNo[32];
218int i, start=0, index = 0;
219
220 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {
221start = 128;
222}
223 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {
224start = 73;
225}
226
227 // Check that the spd part name is zero terminated and that it is ascii:
228 bzero(asciiPartNo, sizeof(asciiPartNo));
229char c;
230for (i=start; i < start + sizeof(asciiPartNo); i++) {
231READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)
232c = spd[i];
233if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...
234asciiPartNo[index++] = c;
235else if (!isascii(c))
236break;
237}
238
239return strdup(asciiPartNo);
240 return NULL;
241}
242
243int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};
244
245
246/** Read from smbus the SPD content and interpret it for detecting memory attributes */
247static void read_smb_intel(pci_dt_t *smbus_dev)
248{
249 int i, speed;
250 uint8_t spd_size, spd_type;
251 uint32_t base, mmio, hostc;
252 bool dump = false;
253 RamSlotInfo_t* slot;
254
255uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);
256DBG("SMBus CmdReg: 0x%x\n", cmd);
257pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);
258
259mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;
260 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;
261hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);
262 verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",
263smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);
264
265 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);
266// needed at least for laptops
267 bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;
268
269char spdbuf[MAX_SPD_SIZE];
270 // Search MAX_RAM_SLOTS slots
271 for (i = 0; i < MAX_RAM_SLOTS; i++){
272 slot = &Platform.RAM.DIMM[i];
273 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
274DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);
275 // Check spd is present
276 if (spd_size && (spd_size != 0xff))
277 {
278
279slot->spd = spdbuf;
280 slot->InUse = true;
281
282 bzero(slot->spd, spd_size);
283
284 // Copy spd data into buffer
285
286//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);
287 init_spd(slot->spd, base, i);
288
289 switch (slot->spd[SPD_MEMORY_TYPE]) {
290 case SPD_MEMORY_TYPE_SDRAM_DDR2:
291
292 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) *
293 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);
294 break;
295
296 case SPD_MEMORY_TYPE_SDRAM_DDR3:
297
298 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );
299 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;
300 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));
301
302 break;
303 }
304
305 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);
306 slot->Type = spd_mem_to_smbios[spd_type];
307 slot->PartNo = getDDRPartNum(slot->spd, base, i);
308 slot->Vendor = getVendorName(slot, base, i);
309 slot->SerialNo = getDDRSerial(slot->spd);
310
311 // determine spd speed
312 speed = getDDRspeedMhz(slot->spd);
313 if (slot->Frequency<speed) slot->Frequency = speed;
314
315// pci memory controller if available, is more reliable
316if (Platform.RAM.Frequency > 0) {
317uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;
318// now round off special cases
319uint32_t fmod100 = freq %100;
320switch(fmod100) {
321case 1:freq--;break;
322case 32:freq++;break;
323case 65:freq++; break;
324case 98:freq+=2;break;
325case 99:freq++; break;
326}
327slot->Frequency = freq;
328}
329
330verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n",
331 i,
332 (int)slot->Type,
333 slot->ModuleSize,
334 spd_memory_types[spd_type],
335 slot->Frequency,
336 slot->Vendor,
337 slot->PartNo,
338 slot->SerialNo);
339
340#if DEBUG_SPD
341 dumpPhysAddr("spd content: ", slot->spd, spd_size);
342 getc();
343#endif
344 }
345
346 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:
347 Platform.DMI.DIMM[i]=
348 i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ?
349 mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this
350
351slot->spd = NULL;
352
353 } // for
354}
355
356static struct smbus_controllers_t smbus_controllers[] = {
357
358{0x8086, 0x269B, "ESB2", read_smb_intel },
359{0x8086, 0x25A4, "6300ESB", read_smb_intel },
360{0x8086, 0x24C3, "ICH4", read_smb_intel },
361{0x8086, 0x24D3, "ICH5", read_smb_intel },
362{0x8086, 0x266A, "ICH6", read_smb_intel },
363{0x8086, 0x27DA, "ICH7", read_smb_intel },
364{0x8086, 0x283E, "ICH8", read_smb_intel },
365{0x8086, 0x2930, "ICH9", read_smb_intel },
366{0x8086, 0x3A30, "ICH10R", read_smb_intel },
367{0x8086, 0x3A60, "ICH10B", read_smb_intel },
368{0x8086, 0x3B30, "P55", read_smb_intel },
369{0x8086, 0x5032, "EP80579", read_smb_intel }
370
371};
372
373// initial call : pci_dt = root_pci_dev;
374// find_and_read_smbus_controller(root_pci_dev);
375bool find_and_read_smbus_controller(pci_dt_t* pci_dt)
376{
377 pci_dt_t*current = pci_dt;
378 int i;
379
380 while (current) {
381#if 0
382 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n",
383 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func,
384 current->class_id, current->vendor_id, current->device_id,
385 get_pci_dev_path(current));
386#endif
387for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )
388 {
389 if (current->vendor_id == smbus_controllers[i].vendor &&
390 current->device_id == smbus_controllers[i].device)
391 {
392 smbus_controllers[i].read_smb(current); // read smb
393 return true;
394 }
395 }
396 find_and_read_smbus_controller(current->children);
397 current = current->next;
398 }
399 return false; // not found
400}
401
402void scan_spd(PlatformInfo_t *p)
403{
404 find_and_read_smbus_controller(root_pci_dev);
405}
406
407

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