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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8//#include "mem.h"␊
9#include "smbios_patcher.h"␊
10#include "cpu.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 1␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22␊
23/*␊
24 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
25 */␊
26static uint64_t measure_tsc_frequency(void)␊
27{␊
28 uint64_t tscStart;␊
29 uint64_t tscEnd;␊
30 uint64_t tscDelta = 0xffffffffffffffffULL;␊
31 unsigned long pollCount;␊
32 uint64_t retval = 0;␊
33 int i;␊
34␊
35 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
36 * counter 2. We run this loop 3 times to make sure the cache␊
37 * is hot and we take the minimum delta from all of the runs.␊
38 * That is to say that we're biased towards measuring the minimum␊
39 * number of TSC ticks that occur while waiting for the timer to␊
40 * expire. That theoretically helps avoid inconsistencies when␊
41 * running under a VM if the TSC is not virtualized and the host␊
42 * steals time. The TSC is normally virtualized for VMware.␊
43 */␊
44 for(i = 0; i < 10; ++i)␊
45 {␊
46 enable_PIT2();␊
47 set_PIT2_mode0(CALIBRATE_LATCH);␊
48 tscStart = rdtsc64();␊
49 pollCount = poll_PIT2_gate();␊
50 tscEnd = rdtsc64();␊
51 /* The poll loop must have run at least a few times for accuracy */␊
52 if(pollCount <= 1)␊
53 continue;␊
54 /* The TSC must increment at LEAST once every millisecond. We␊
55 * should have waited exactly 30 msec so the TSC delta should␊
56 * be >= 30. Anything less and the processor is way too slow.␊
57 */␊
58 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
59 continue;␊
60 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
61 if( (tscEnd - tscStart) < tscDelta )␊
62 tscDelta = tscEnd - tscStart;␊
63 }␊
64 /* tscDelta is now the least number of TSC ticks the processor made in␊
65 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
66 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
67 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
68 * Hz so we need to convert our milliseconds to seconds. Since we're␊
69 * dividing by the milliseconds, we simply multiply by 1000.␊
70 */␊
71␊
72 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
73 * that we're going to multiply by 1000 first so we do need at least some␊
74 * arithmetic headroom. For now, 32-bit should be enough.␊
75 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
76 */␊
77 if(tscDelta > (1ULL<<32))␊
78 retval = 0;␊
79 else␊
80 {␊
81 retval = tscDelta * 1000 / 30;␊
82 }␊
83 disable_PIT2();␊
84 return retval;␊
85}␊
86␊
87/*␊
88 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
89 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
90 * a max multi. (used to calculate the FSB freq.),␊
91 * and a current multi. (used to calculate the CPU freq.)␊
92 * - fsbFrequency = tscFrequency / multi␊
93 * - cpuFrequency = fsbFrequency * multi␊
94 */␊
95␊
96void scan_cpu() //PlatformInfo_t *p)␊
97{␊
98␉PlatformInfo_t *p = Platform;␊
99␉int i = 0;␊
100␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
101␉uint64_t␉msr; //, flex_ratio;␊
102␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv, mindiv;␊
103␊
104␉maxcoef = maxdiv = currcoef = currdiv = mindiv = 0;␊
105␊
106␉/* get cpuid values */␊
107␉for( ; i <= 3; i++)␊
108␉{␊
109␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
110␉}␊
111␉␊
112␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
113␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
114␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
115␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
116␉}␊
117#if DEBUG_CPU␊
118␉{␊
119␉␉int␉␉i;␊
120␉␉DBG("CPUID Raw Values:\n");␊
121␉␉for (i=0; i<CPUID_MAX; i++) {␊
122␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊
123␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
124␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
125␉␉}␊
126␉}␊
127#endif␊
128␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
129␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
130␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
131␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
132␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
133␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
134␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
135␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
136␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
137␊
138␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
139␉␊
140␉/* get brand string (if supported) */␊
141␉/* Copyright: from Apple's XNU cpuid.c */␊
142␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
143␉␉uint32_t␉reg[4];␊
144 char str[128], *s;␊
145␉␉/*␊
146␉␉ * The brand string 48 bytes (max), guaranteed to␊
147␉␉ * be NUL terminated.␊
148␉␉ */␊
149␉␉do_cpuid(0x80000002, reg);␊
150␉␉bcopy((char *)reg, &str[0], 16);␊
151␉␉do_cpuid(0x80000003, reg);␊
152␉␉bcopy((char *)reg, &str[16], 16);␊
153␉␉do_cpuid(0x80000004, reg);␊
154␉␉bcopy((char *)reg, &str[32], 16);␊
155␉␉for (s = str; *s != '\0'; s++) {␊
156␉␉␉if (*s != ' ') break;␊
157␉␉}␊
158␉␉␊
159␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
160␉␉␊
161␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
162␉␉␉ /*␊
163␉␉␉ * This string means we have a firmware-programmable brand string,␊
164␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
165␉␉␉ */␊
166␉␉␉ p->CPU.BrandString[0] = '\0';␊
167␉␉ }␊
168␉}␊
169␉␊
170␉/* setup features */␊
171␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR) & p->CPU.CPUID[CPUID_1][3];␊
172␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42) & p->CPU.CPUID[CPUID_1][2];␉␊
173␉p->CPU.Features |= (CPU_FEATURE_EM64T) & p->CPU.CPUID[CPUID_81][3];␊
174␊
175␊
176␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
177␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
178␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
179␉}␊
180␉ ␊
181␊
182␉tscFrequency = measure_tsc_frequency();␊
183␉DBG("measure_tsc_frequency = %dMHz\n", tscFrequency / MEGA);␊
184␉fsbFrequency = 0;␊
185␉cpuFrequency = 0;␊
186␊
187␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ␊
188␉␉((p->CPU.Family == 0x06) || ␊
189␉␉ (p->CPU.Family == 0x0f)))␊
190␉{␊
191␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || ␊
192␉␉␉(p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
193␉␉{␊
194␉␉␉/* Nehalem CPU model */␊
195␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e ||␊
196␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == 0x1f || p->CPU.Model == 0x25 ||␊
197␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == 0x19 || p->CPU.Model == 0x2c)) ␊
198␉␉␉{␊
199␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
200␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
201␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊
202␉␉␉␉mindiv = (msr >> 40) & 0xff;␊
203␉␉␉␉maxcoef = (msr >> 8) & 0xff; ␊
204␉␉␉␉//Slice - doesn't work␊
205␉␉␉␉/*␊
206␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
207␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊
208␉␉␉␉if ((msr >> 16) & 0x01) {␊
209␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
210␉␉␉␉␉if (currcoef > flex_ratio) {␊
211␉␉␉␉␉␉currcoef = flex_ratio;␊
212␉␉␉␉␉}␊
213␉␉␉␉}*/␊
214␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
215␉␉␉␉if (msr) {␊
216␉␉␉␉␉currcoef = msr & 0x1f;␊
217␉␉␉␉}␊
218␉␉␉␉␊
219␉␉␉␉if (!currcoef) {␊
220␉␉␉␉␉currcoef = maxcoef;␊
221␉␉␉␉}␊
222␉␉␉␉␊
223␉␉␉␉if (currcoef < mindiv) {␊
224␉␉␉␉␉currcoef = mindiv;␊
225␉␉␉␉}␊
226␉␉␉␉␊
227␉␉␉␉if (currcoef) {␊
228␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
229␉␉␉␉}␊
230␉␉␉␉cpuFrequency = tscFrequency;␊
231␉␉␉} ␊
232␉␉␉else //not nehalem␊
233␉␉␉{␊
234␉␉␉␉//Slice - it is not FSB frequency. It is System Bus Speed: FSB = SBS * 4;␉␊
235␉␉␉␉if (p->CPU.Family != 0x0d){␊
236␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
237␉␉␉␉␉switch (msr & 7) {␊
238␉␉␉␉␉␉case 0:␊
239␉␉␉␉␉␉␉fsbFrequency = 266670 * 1000;␊
240␉␉␉␉␉␉␉break;␊
241␉␉␉␉␉␉case 1:␊
242␉␉␉␉␉␉␉fsbFrequency = 133330 * 1000;␊
243␉␉␉␉␉␉␉break;␊
244␉␉␉␉␉␉case 2:␊
245␉␉␉␉␉␉␉fsbFrequency = 200000 * 1000;␊
246␉␉␉␉␉␉␉break;␊
247␉␉␉␉␉␉case 3:␊
248␉␉␉␉␉␉␉fsbFrequency = 166670 * 1000;␊
249␉␉␉␉␉␉␉break;␊
250␉␉␉␉␉␉case 4:␊
251␉␉␉␉␉␉␉fsbFrequency = 333330 * 1000;␊
252␉␉␉␉␉␉␉break;␊
253␉␉␉␉␉␉case 5:␊
254␉␉␉␉␉␉␉fsbFrequency = 200000 * 1000;␊
255␉␉␉␉␉␉␉break;␊
256␉␉␉␉␉␉case 6:␊
257␉␉␉␉␉␉␉fsbFrequency = 400000 * 1000;␊
258␉␉␉␉␉␉␉break;␊
259␉␉␉␉␉␉default:␊
260␉␉␉␉␉␉␉fsbFrequency = 0;␊
261␉␉␉␉␉␉␉break;␊
262␉␉␉␉␉}␊
263␉␉␉␉␉DBG("msr(0x%04x): MSR_FSB_FREQ %dMHz\n", MSR_FSB_FREQ, fsbFrequency/MEGA);␊
264␉␉␉␉}␊
265␉␉␉␉␊
266␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
267␉␉␉␉uint32_t m2 = msr >> 32;␊
268␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
269␉␉␉␉␉m2 & 0xffffffff, msr & 0xffffffff);␊
270␉␉␉␉␊
271␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
272␉␉␉␉m2 = msr >> 32;␊
273␉␉␉␉DBG("msr(0x%04x): MSR_IA32_PERF_STATUS %08x-%08x\n", MSR_IA32_PERF_STATUS,␊
274␉␉␉␉␉m2 & 0xffffffff, msr & 0xffffffff);␊
275␉␉␉␉␊
276␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
277␉␉␉␉mindiv = (msr >> 24) & 0xf;␊
278␉␉␉␉if (currcoef < mindiv) {␊
279␉␉␉␉␉currcoef = mindiv;␊
280␉␉␉␉}␊
281␉␉␉␉␊
282␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
283␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
284␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
285␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
286␊
287␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || ␊
288␉␉␉␉␉(p->CPU.Family == 0x0f)) // This will always be model >= 3␊
289␉␉␉␉{␊
290␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
291␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
292␉␉␉␉} ␊
293␉␉␉␉else ␊
294␉␉␉␉{␊
295␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
296␉␉␉␉␉/* XXX */␊
297␉␉␉␉␉maxcoef = currcoef;␊
298␉␉␉␉}␊
299␊
300␉␉␉␉if (maxcoef) ␊
301␉␉␉␉{␊
302␉␉␉␉␉if (!fsbFrequency) {␊
303␉␉␉␉␉␉if (maxdiv)␊
304␉␉␉␉␉␉{␊
305␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
306␉␉␉␉␉␉}␊
307␉␉␉␉␉␉else ␊
308␉␉␉␉␉␉{␊
309␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
310␉␉␉␉␉␉}␊
311␉␉␉␉␉␉␊
312␉␉␉␉␉}␊
313␉␉␉␉␉␊
314␉␉␉␉␉if (currdiv) ␊
315␉␉␉␉␉{␊
316␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
317␉␉␉␉␉}␊
318␉␉␉␉␉else ␊
319␉␉␉␉␉{␊
320␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
321␉␉␉␉␉}␊
322␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
323␉␉␉␉}␊
324␉␉␉}␊
325␉␉}␊
326␉␉/* Mobile CPU ? */␊
327//Slice ␊
328␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
329␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊
330␉␉if (!scanDMI() && msr) {␊
331␉␉␉p->CPU.Mobile = FALSE;␊
332␉␉␉switch (p->CPU.Model) {␊
333␉␉␉␉case 0x0D:␊
334␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊
335␉␉␉␉␉break;␊
336␉␉␉␉case 0x0F:␊
337␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊
338␉␉␉␉␉break;␊
339␉␉␉␉case 0x02:␊
340␉␉␉␉case 0x03:␊
341␉␉␉␉case 0x04:␊
342␉␉␉␉case 0x06:␉␊
343␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊
344␉␉␉␉␉break;␊
345␉␉␉␉default:␊
346␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊
347␉␉␉␉␉break;␊
348␉␉␉}␊
349␉␉␉if (p->CPU.Mobile) {␊
350␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
351␉␉␉}␊
352␉␉}␊
353␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊
354␉␉␉␊
355␉}␊
356#if 0␊
357␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f))␊
358␉{␊
359␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
360␉␉{␊
361␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
362␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
363␉␉␉currdiv = (msr & 0x01) * 2;␊
364␉␉} ␊
365␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
366␉␉{␊
367␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
368␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
369␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
370␉␉␉else /* K11+ */␊
371␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
372␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
373␉␉}␊
374␊
375␉␉if (currcoef) ␊
376␉␉{␊
377␉␉␉if (currdiv) ␊
378␉␉␉{␊
379␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
380␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
381␉␉␉}␊
382␉␉␉else␊
383␉␉␉{␊
384␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
385␉␉␉␉DBG("%d\n", currcoef);␊
386␉␉␉}␊
387␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
388␉␉␉cpuFrequency = tscFrequency;␊
389␉␉}␊
390␉}␊
391#endif␊
392␉else if(p->CPU.Vendor == 0x746e6543 && p->CPU.Family == 6)␊
393␉{␊
394␉␉switch (p->CPU.Model) {␊
395␉␉␉case CPU_VIA_NANO:␊
396␉␉␉␉// NOTE: TSC is constant, irrelevent of speed steping ␊
397␉␉␉␉break;␊
398␉␉␉default:␊
399␉␉␉␉break;␊
400␉␉}␊
401␉␉␊
402␉␉msr = rdmsr64(MSR_NANO_FCR2);␊
403␉␉printf("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊
404␉␉␊
405␉␉//msr = msr >> 32;␊
406␉␉msr |= VIA_ALTERNATIVE_VENDOR_BIT;␊
407␉␉//msr = msr << 32;␊
408␉␉␊
409␉␉printf("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊
410␉␉wrmsr64(MSR_NANO_FCR2, msr);␊
411␉␉msr = rdmsr64(MSR_NANO_FCR2);␊
412␉␉printf("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊
413␉␉␊
414␉␉␊
415␉␉/* get cpuid values */␊
416␉␉for( ; i <= 3; i++)␊
417␉␉{␊
418␉␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
419␉␉}␊
420␉␉//int numcpuid_supported = p->CPU.CPUID[CPUID_0][0];␉// max number cpuid call␊
421␉␉//int numextcpuid = p->CPU.CPUID[CPUID_80][0];␊
422␉␉␉␉␉␉␉␉␉␉␉␉␉␉␉//p->CPU.Features = 0;␊
423␉␉␉␉␉␉␉␉␉␉␉␉␉␉␉//␉␉bitfield(p->CPU.CPUID[CPUID_1][1], 0, 0) FEATURE_C␊
424␉␉␊
425␉␉// CPUID_0 -> largest cpuid val in EAX␊
426␉␉// CPUID_0 -> rem = vendor string␊
427␉␉/*␊
428␉␉CPUID_1 EDX:␊
429␉␉ 0 -> FPU␊
430␉␉ 1 -> VME␊
431␉␉ 2 -> DE␊
432␉␉ 3 -> PSE␊
433␉␉ 4 -> TSC␊
434␉␉ 5 -> MSR␊
435␉␉ 6 -> PAE␊
436␉␉ 7 -> MCE␊
437␉␉ 8 -> CX8␊
438␉␉ 9 -> APIC␊
439␉␉ 10 -> Reserved␊
440␉␉ 11 -> Fast Call␊
441␉␉ 12 -> MTTR␊
442␉␉ 13 -> PGE␊
443␉␉ 14 -> MCA␊
444␉␉ 15 -> CMOV␊
445␉␉ 16 -> PAT␊
446␉␉ 17 -> PSE36␊
447␉␉ 18 -> Serial Number ␊
448␉␉ 23 -> MMX␊
449␉␉ 24 -> FXSR␊
450␉␉ 25 -> SSE␊
451␉␉ */␊
452␉␉␊
453␉␉//CPUID_80 -> largest excpuid value in EAX␊
454␉␉//CPUID_81,EAX -> Signature␊
455␉␉//CPUID_80,EDX -> Ext Features␊
456␉␉//CPUID_82 -> CPU String␊
457␉␉//CPUID_83 -> CPU String␊
458␉␉//CPUID_84 -> CPU String␊
459␉␉p->CPU.NoThreads = p->CPU.NoCores;␊
460␉␉␊
461␉}␊
462␉␊
463␉if (!fsbFrequency) {␊
464␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
465␉␉cpuFrequency = tscFrequency;␊
466␉␉msglog("CPU: fsb=0 ! using the default value 100MHz !\n");␊
467␉}␊
468␉␊
469/*␉␊
470␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
471␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
472␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
473␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
474␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
475␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
476␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
477␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
478*/␉␊
479␊
480␊
481␉p->CPU.MaxCoef = maxcoef;␊
482␉p->CPU.MaxDiv = maxdiv;␊
483␉p->CPU.MinCoef = mindiv;␊
484␉p->CPU.CurrCoef = currcoef;␊
485␉p->CPU.CurrDiv = currdiv;␊
486␉p->CPU.TSCFrequency = tscFrequency;␊
487␉p->CPU.FSBFrequency = fsbFrequency;␊
488␉p->CPU.CPUFrequency = cpuFrequency;␊
489␊
490␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
491␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
492␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
493␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊
494␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
495␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
496␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
497␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
498␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
499#if DEBUG_CPU␊
500␉pause();␊
501#endif␊
502}␊
503

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