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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * valv: 2010: fine-tuning and additions␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "boot.h"␊
11#include "bootstruct.h"␊
12␊
13#ifndef DEBUG_CPU␊
14#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18#define DBG(x...)␉␉printf(x)␊
19#else␊
20#define DBG(x...)␉␉msglog(x)␊
21#endif␊
22␊
23/*␊
24 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
25 */␊
26static uint64_t measure_tsc_frequency(void)␊
27{␊
28 uint64_t tscStart;␊
29 uint64_t tscEnd;␊
30 uint64_t tscDelta = 0xffffffffffffffffULL;␊
31 unsigned long pollCount;␊
32 uint64_t retval = 0;␊
33 int i;␊
34␊
35 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
36 * counter 2. We run this loop 3 times to make sure the cache␊
37 * is hot and we take the minimum delta from all of the runs.␊
38 * That is to say that we're biased towards measuring the minimum␊
39 * number of TSC ticks that occur while waiting for the timer to␊
40 * expire. That theoretically helps avoid inconsistencies when␊
41 * running under a VM if the TSC is not virtualized and the host␊
42 * steals time. The TSC is normally virtualized for VMware.␊
43 */␊
44 for(i = 0; i < 10; ++i)␊
45 {␊
46 enable_PIT2();␊
47 set_PIT2_mode0(CALIBRATE_LATCH);␊
48 tscStart = rdtsc64();␊
49 pollCount = poll_PIT2_gate();␊
50 tscEnd = rdtsc64();␊
51 /* The poll loop must have run at least a few times for accuracy */␊
52 if(pollCount <= 1)␊
53 continue;␊
54 /* The TSC must increment at LEAST once every millisecond. We␊
55 * should have waited exactly 30 msec so the TSC delta should␊
56 * be >= 30. Anything less and the processor is way too slow.␊
57 */␊
58 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
59 continue;␊
60 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
61 if( (tscEnd - tscStart) < tscDelta )␊
62 tscDelta = tscEnd - tscStart;␊
63 }␊
64 /* tscDelta is now the least number of TSC ticks the processor made in␊
65 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
66 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
67 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
68 * Hz so we need to convert our milliseconds to seconds. Since we're␊
69 * dividing by the milliseconds, we simply multiply by 1000.␊
70 */␊
71␊
72 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
73 * that we're going to multiply by 1000 first so we do need at least some␊
74 * arithmetic headroom. For now, 32-bit should be enough.␊
75 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
76 */␊
77 if(tscDelta > (1ULL<<32))␊
78 retval = 0;␊
79 else␊
80 {␊
81 retval = tscDelta * 1000 / 30;␊
82 }␊
83 disable_PIT2();␊
84 return retval;␊
85}␊
86␊
87␊
88/*␊
89 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
90 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
91 * a max multi. (used to calculate the FSB freq.),␊
92 * and a current multi. (used to calculate the CPU freq.)␊
93 * - fsbFrequency = tscFrequency / multi␊
94 * - cpuFrequency = fsbFrequency * multi␊
95 */␊
96␊
97void scan_cpu(PlatformInfo_t *p)␊
98{␊
99␉const char␉*newratio, *newfsb;␊
100␉int␉␉␉len, myfsb, i;␊
101␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, fsbi;␊
102␉uint64_t␉msr, flex_ratio = 0;␊
103␉uint32_t␉tms, ida, amo, max_ratio, min_ratio;␊
104␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊
105␉bool␉␉fix_fsb, did, core_i, turbo;␊
106␊
107␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊
108␊
109␉/* get cpuid values */␊
110␉for( ; i <= 3; i++)␊
111␉{␊
112␉␉do_cpuid(i, p->CPU.CPUID[i]);␊
113␉}␊
114␉␊
115␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
116␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
117␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
118␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
119␉}␊
120#if DEBUG_CPU␊
121␉{␊
122␉␉int␉␉i;␊
123␉␉printf("CPUID Raw Values:\n");␊
124␉␉for (i=0; i<CPUID_MAX; i++) {␊
125␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
126␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
127␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
128␉␉}␊
129␉}␊
130#endif␊
131␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
132␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
133␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
134␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
135␉p->CPU.Type␉␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊
136␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
137␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
138␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
139␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
140␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
141␊
142␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
143␊
144␉/* get brand string (if supported) */␊
145␉/* Copyright: from Apple's XNU cpuid.c */␊
146␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
147␉␉uint32_t␉reg[4];␊
148 char str[128], *s;␊
149␉␉/*␊
150␉␉ * The brand string 48 bytes (max), guaranteed to␊
151␉␉ * be NUL terminated.␊
152␉␉ */␊
153␉␉do_cpuid(0x80000002, reg);␊
154␉␉bcopy((char *)reg, &str[0], 16);␊
155␉␉do_cpuid(0x80000003, reg);␊
156␉␉bcopy((char *)reg, &str[16], 16);␊
157␉␉do_cpuid(0x80000004, reg);␊
158␉␉bcopy((char *)reg, &str[32], 16);␊
159␉␉for (s = str; *s != '\0'; s++) {␊
160␉␉␉if (*s != ' ') break;␊
161␉␉}␊
162␉␉␊
163␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
164␉␉␊
165␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
166␉␉␉ /*␊
167␉␉␉ * This string means we have a firmware-programmable brand string,␊
168␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
169␉␉␉ */␊
170␉␉␉ p->CPU.BrandString[0] = '\0';␊
171␉␉ }␊
172␉}␊
173␉␊
174␉/* setup features */␊
175␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊
176␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊
177␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊
178␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊
179␊
180␊
181␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
182␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
183␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
184␉}␊
185␉ ␊
186␊
187␉tscFrequency = measure_tsc_frequency();␊
188␉fsbFrequency = 0;␊
189␉cpuFrequency = 0;␊
190␉fsbi = 0;␊
191␉fix_fsb = false;␊
192␉did = false;␊
193␉core_i = false;␊
194␉turbo = false;␊
195␊
196␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
197␉{␊
198␉␉verbose("CPU: ");␊
199␉␉int tjmax = 0;␊
200␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
201␉␉if((((msr >> 50) & 0x01) == 1) || (rdmsr64(0x17) & (1<<28)))␊
202␉␉{␊
203␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
204␉␉␉verbose("Mobile ");␊
205␉␉}␊
206␉␉verbose("%s\n", p->CPU.BrandString);␊
207␉␉␊
208␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
209␉␉{␊
210␉␉␉if (p->CPU.Family == 0x06)␊
211␉␉␉{␊
212␉␉␉␉int intelCPU = p->CPU.Model;␊
213␉␉␉␉int Stepp = p->CPU.Stepping;␊
214␉␉␉␉int bus;␊
215␊
216␉␉␉␉switch (intelCPU)␊
217␉␉␉␉{␊
218␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊
219␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊
220␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊
221␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm␊
222␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm␊
223␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex Xeon, "Beckton"␊
224␉␉␉␉␉case 0x2f:␉␉// Core i7, Nehalem-Ex Xeon, "Eagleton"␊
225␉␉␉␉␉␉core_i = true;␊
226␉␉␉␉␉␉tjmax = (rdmsr64(MSR_THERMAL_TARGET) >> 16) & 0xff;␊
227␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
228␉␉␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
229␉␉␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
230␉␉␉␉␉␉verbose("CPU: Flex-Ratio = %d ", bus_ratio_max);␊
231␉␉␉␉␉␉min_ratio = bus_ratio_min * 10;␊
232␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
233␉␉␉␉␉␉if ((msr >> 16) & 0x01)␊
234␉␉␉␉␉␉{␊
235␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
236␉␉␉␉␉␉␉verbose(">> %d", flex_ratio);␊
237␉␉␉␉␉␉␉if(bus_ratio_max > flex_ratio) bus_ratio_max = flex_ratio;␊
238␉␉␉␉␉␉}␊
239␉␉␉␉␉␉verbose("\n");␊
240␉␉␉␉␉␉if(bus_ratio_max) fsbFrequency = (tscFrequency / bus_ratio_max);␊
241␊
242␉␉␉␉␉␉//valv: Turbo Ratio Limit␊
243␉␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
244␉␉␉␉␉␉{␊
245␉␉␉␉␉␉␉turbo = true;␊
246␉␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
247␉␉␉␉␉␉␉␊
248␉␉␉␉␉␉␉p->CPU.Tone = (msr >> 0) & 0xff;␊
249␉␉␉␉␉␉␉p->CPU.Ttwo = (msr >> 8) & 0xff;␊
250␉␉␉␉␉␉␉p->CPU.Tthr = (msr >> 16) & 0xff;␊
251␉␉␉␉␉␉␉p->CPU.Tfor = (msr >> 24) & 0xff;␊
252␊
253␉␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
254␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
255␉␉␉␉␉␉}␊
256␉␉␉␉␉␉else cpuFrequency = tscFrequency;␊
257␊
258␉␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
259␉␉␉␉␉␉{␊
260␉␉␉␉␉␉␉max_ratio = atoi(newratio);␊
261␉␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
262␉␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
263␊
264␉␉␉␉␉␉␉verbose("Bus-Ratio: min=%d%s, max=%d%s\n", bus_ratio_min, bus_ratio_max);␊
265␊
266␉␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
267␉␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
268␉␉␉␉␉␉␉{␊
269␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
270␉␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
271␉␉␉␉␉␉␉␉else maxdiv = 0;␊
272␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
273␉␉␉␉␉␉␉}␊
274␉␉␉␉␉␉␉else max_ratio = (bus_ratio_max * 10);␊
275␉␉␉␉␉␉}␊
276␉␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
277␉␉␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
278␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
279␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
280␉␉␉␉␉␉␊
281␉␉␉␉␉␉fsbi = fsbFrequency;␊
282␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊
283␉␉␉␉␉␉break;␊
284␉␉␉␉␉case 0xd:␉␉// Pentium D; valv: is this the right place ?␊
285␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊
286␉␉␉␉␉␉goto teleport;␊
287␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊
288␉␉␉␉␉␉switch (Stepp)␊
289␉␉␉␉␉␉{␊
290␉␉␉␉␉␉␉case 0x2:␊
291␉␉␉␉␉␉␉␉tjmax = 95;␊
292␉␉␉␉␉␉␉␉break;␊
293␉␉␉␉␉␉␉case 0x6:␊
294␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 2) tjmax = 80;␊
295␉␉␉␉␉␉␉␉if (p->CPU.NoCores = 4) tjmax = 90;␊
296␉␉␉␉␉␉␉␉else tjmax = 85;␊
297␉␉␉␉␉␉␉␉break;␊
298␉␉␉␉␉␉␉case 0xb:␊
299␉␉␉␉␉␉␉␉tjmax = 90;␊
300␉␉␉␉␉␉␉␉break;␊
301␉␉␉␉␉␉␉case 0xd:␊
302␉␉␉␉␉␉␉default:␊
303␉␉␉␉␉␉␉teleport:␊
304␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_EXT_CONFIG);␊
305␉␉␉␉␉␉␉␉if(msr & (1 << 30)) tjmax = 85;␊
306␉␉␉␉␉␉␉␉break;␊
307␉␉␉␉␉␉}␊
308␉␉␉␉␉case 0x1c:␉␉// Atom :)␊
309␉␉␉␉␉␉switch (Stepp)␊
310␉␉␉␉␉␉{␊
311␉␉␉␉␉␉␉case 0xa:␊
312␉␉␉␉␉␉␉␉tjmax = 100;␊
313␉␉␉␉␉␉␉␉break;␊
314␉␉␉␉␉␉␉case 0x2:␊
315␉␉␉␉␉␉␉default:␊
316␉␉␉␉␉␉␉␉tjmax = 90;␊
317␉␉␉␉␉␉␉␉break;␊
318␉␉␉␉␉␉}␊
319␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊
320␉␉␉␉␉␉switch (Stepp)␊
321␉␉␉␉␉␉{␊
322␉␉␉␉␉␉␉case 0x6:␉␉// Mobile Core2 Duo␊
323␉␉␉␉␉␉␉␉tjmax = 104;␊
324␉␉␉␉␉␉␉␉break;␊
325␉␉␉␉␉␉␉case 0xa:␉␉// Mobile Centrino 2␊
326␉␉␉␉␉␉␉␉tjmax = 105;␊
327␉␉␉␉␉␉␉␉break;␊
328␉␉␉␉␉␉␉default:␊
329␉␉␉␉␉␉␉␉if (platformCPUFeature(CPU_FEATURE_MOBILE)) tjmax = 105;␊
330␉␉␉␉␉␉␉␉break;␊
331␉␉␉␉␉␉}␊
332␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊
333␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊
334␉␉␉␉␉␉core_i = false;␊
335␉␉␉␉␉␉//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2␊
336␉␉␉␉␉␉//also, if bit 3 of misc_enable is cleared the above would have no effect␊
337␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM1))␊
338␉␉␉␉␉␉{␊
339␉␉␉␉␉␉␉msr_t msr32;␊
340␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
341␊
342␉␉␉␉␉␉␉//thermally-initiated on-die modulation of the stop-clock duty cycle␊
343␉␉␉␉␉␉␉if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);␊
344␉␉␉␉␉␉␉verbose("CPU: Thermal Monitor: TM, ");␊
345␉␉␉␉␉␉␉␊
346␉␉␉␉␉␉␉//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set␊
347␉␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM2))␊
348␉␉␉␉␉␉␉{␊
349␉␉␉␉␉␉␉␉//thermally-initiated frequency transitions␊
350␉␉␉␉␉␉␉␉msr32.lo |= (1 << 13);␊
351␉␉␉␉␉␉␉␉verbose("TM2, ");␊
352␉␉␉␉␉␉␉}␊
353␉␉␉␉␉␉␉msr32.lo |= (1 << 17);␊
354␉␉␉␉␉␉␉verbose("PROCHOT, ");␊
355␉␉␉␉␉␉␉msr32.lo |= (1 << 10);␊
356␉␉␉␉␉␉␉verbose("FERR\n");␊
357␉␉␉␉␉␉␉␊
358␉␉␉␉␉␉␉bool oem_ssdt, tmpval;␊
359␉␉␉␉␉␉␉oem_ssdt = false;␊
360␉␉␉␉␉␉␉␊
361␉␉␉␉␉␉␉oem_ssdt = getBoolForKey(kOEMSSDT, &tmpval, &bootInfo->bootConfig)&&tmpval;␊
362␉␉␉␉␉␉␉if(oem_ssdt)␊
363␉␉␉␉␉␉␉{␊
364␉␉␉␉␉␉␉␉bool c2e, c4e, hc4e;␊
365␉␉␉␉␉␉␉␉c2e = c4e = hc4e = false;␊
366␊
367␉␉␉␉␉␉␉␉getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig);␊
368␉␉␉␉␉␉␉␉if(c2e) msr32.lo |= (1 << 26);␊
369␉␉␉␉␉␉␉␉␊
370␉␉␉␉␉␉␉␉getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig);␊
371␉␉␉␉␉␉␉␉if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));␊
372␉␉␉␉␉␉␉␉getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);␊
373␉␉␉␉␉␉␉␉if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));␊
374␉␉␉␉␉␉␉}␊
375␉␉␉␉␉␉␉␊
376␉␉␉␉␉␉␉msr32.hi |= (1 << (36 - 32)); // EMTTM␊
377␊
378␉␉␉␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
379␉␉␉␉␉␉␉␊
380␉␉␉␉␉␉␉msr32 = rdmsr(PIC_SENS_CFG);␊
381␉␉␉␉␉␉␉msr32.lo |= (1 << 21);␊
382␉␉␉␉␉␉␉wrmsr(PIC_SENS_CFG, msr32);␊
383␉␉␉␉␉␉}␊
384␉␉␉␉␉␉␊
385␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊
386␉␉␉␉␉␉{␊
387␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));␊
388␉␉␉␉␉␉␉delay(1);␊
389␉␉␉␉␉␉␉did = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊
390␉␉␉␉␉␉}␊
391␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
392␉␉␉␉␉␉if(fix_fsb)␊
393␉␉␉␉␉␉{␊
394␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
395␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊
396␉␉␉␉␉␉␉switch (bus)␊
397␉␉␉␉␉␉␉{␊
398␉␉␉␉␉␉␉␉case 0:␊
399␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
400␉␉␉␉␉␉␉␉␉myfsb = 266;␊
401␉␉␉␉␉␉␉␉␉break;␊
402␉␉␉␉␉␉␉␉case 1:␊
403␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
404␉␉␉␉␉␉␉␉␉myfsb = 133;␊
405␉␉␉␉␉␉␉␉␉break;␊
406␉␉␉␉␉␉␉␉case 3:␊
407␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
408␉␉␉␉␉␉␉␉␉myfsb = 166;␊
409␉␉␉␉␉␉␉␉␉break;␊
410␉␉␉␉␉␉␉␉case 4:␊
411␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
412␉␉␉␉␉␉␉␉␉myfsb = 333;␊
413␉␉␉␉␉␉␉␉␉break;␊
414␉␉␉␉␉␉␉␉case 5:␊
415␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
416␉␉␉␉␉␉␉␉␉myfsb = 100;␊
417␉␉␉␉␉␉␉␉␉break;␊
418␉␉␉␉␉␉␉␉case 6:␊
419␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
420␉␉␉␉␉␉␉␉␉myfsb = 400;␊
421␉␉␉␉␉␉␉␉␉break;␊
422␉␉␉␉␉␉␉␉case 2:␊
423␉␉␉␉␉␉␉␉default:␊
424␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
425␉␉␉␉␉␉␉␉␉myfsb = 200;␊
426␉␉␉␉␉␉␉␉␉break;␊
427␉␉␉␉␉␉␉}␊
428␉␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
429␉␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency)) fsbFrequency = 200000000;␊
430␉␉␉␉␉␉␉goto ratio;␊
431␉␉␉␉␉␉}␊
432␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊
433␉␉␉␉␉// for 0x2a & 0x2b turbo is true;␊
434␉␉␉␉␉//case 0x2a:␉␉// SNB␊
435␉␉␉␉␉//case 0x2b:␉␉// SNB Xeon␊
436␉␉␉␉␉default:␊
437␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig))␊
438␉␉␉␉␉␉{␊
439␉␉␉␉␉␉␉forcefsb:␊
440␉␉␉␉␉␉␉switch(myfsb)␊
441␉␉␉␉␉␉␉{␊
442␉␉␉␉␉␉␉␉case 133:␊
443␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
444␉␉␉␉␉␉␉␉␉break;␊
445␉␉␉␉␉␉␉␉case 166:␊
446␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
447␉␉␉␉␉␉␉␉␉break;␊
448␉␉␉␉␉␉␉␉case 233:␊
449␉␉␉␉␉␉␉␉␉fsbFrequency = 233333333;␊
450␉␉␉␉␉␉␉␉␉break;␊
451␉␉␉␉␉␉␉␉case 266:␊
452␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
453␉␉␉␉␉␉␉␉␉break;␊
454␉␉␉␉␉␉␉␉case 333:␊
455␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
456␉␉␉␉␉␉␉␉␉break;␊
457␉␉␉␉␉␉␉␉case 100:␊
458␉␉␉␉␉␉␉␉case 200:␊
459␉␉␉␉␉␉␉␉case 400:␊
460␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
461␉␉␉␉␉␉␉␉␉break;␊
462␉␉␉␉␉␉␉␉default:␊
463␉␉␉␉␉␉␉␉␉getValueForKey(kForceFSB, &newfsb, &len, &bootInfo->bootConfig);␊
464␉␉␉␉␉␉␉␉␉if((len <= 3) && (myfsb < 400))␊
465␉␉␉␉␉␉␉␉␉{␊
466␉␉␉␉␉␉␉␉␉␉fsbFrequency = (myfsb * 1000000);␊
467␉␉␉␉␉␉␉␉␉␉verbose("Specified FSB: %dMhz. Assuming you know what you 're doing !\n", myfsb);␊
468␉␉␉␉␉␉␉␉␉}␊
469␉␉␉␉␉␉␉␉␉else if(core_i) fsbFrequency = 133333333;␊
470␉␉␉␉␉␉␉␉␉else fsbFrequency = 200000000;␊
471␉␉␉␉␉␉␉␉␉break;␊
472␉␉␉␉␉␉␉}␊
473␉␉␉␉␉␉␉if(core_i)␊
474␉␉␉␉␉␉␉{␊
475␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
476␉␉␉␉␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
477␉␉␉␉␉␉␉␉break;␊
478␉␉␉␉␉␉␉}␊
479␉␉␉␉␉␉␉fix_fsb = true;␊
480␉␉␉␉␉␉}␊
481␉␉␉␉␉␉goto ratio;␊
482␉␉␉␉␉␉break;␊
483␉␉␉␉}␊
484␉␉␉}␊
485␉␉␉else␊
486␉␉␉{␊
487␉␉␉␉ratio:␊
488␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
489␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
490␉␉␉␉//valv: this seems to be bit 15 instead of 14.␊
491␉␉␉␉currdiv = (msr >> 15) & 0x01;␊
492␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊
493␊
494␉␉␉␉msr_t msr;␊
495␉␉␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊
496␉␉␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊
497␉␉␉␉min_ratio = bus_ratio_min * 10;␊
498␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊
499␉␉␉␉␊
500␉␉␉␉if(XE) bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊
501␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊
502␊
503␉␉␉␉if(fix_fsb)␊
504␉␉␉␉{␊
505␉␉␉␉␉if (bus_ratio_max)␊
506␉␉␉␉␉{␊
507␉␉␉␉␉␉if (maxdiv) fsbi = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
508␉␉␉␉␉␉else fsbi = (tscFrequency / bus_ratio_max);␊
509␉␉␉␉␉}␊
510␉␉␉␉␉ratio_gn:␊
511␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4))␊
512␉␉␉␉␉{␊
513␉␉␉␉␉␉max_ratio = atoi(newratio);␊
514␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
515␉␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
516␊
517␉␉␉␉␉␉verbose("Bus-Ratio defaults: min=%d%s, max=%d%s\n", bus_ratio_min, currdiv ? ".5" : "", bus_ratio_max, maxdiv ? ".5" : "");␊
518␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio < 200))␊
519␉␉␉␉␉␉{␊
520␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
521␉␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
522␉␉␉␉␉␉␉else maxdiv = 0;␊
523␉␉␉␉␉␉␉verbose("Sticking with [FSB: %dMhz, Bus-Ratio: %s]\n", myfsb, newratio);␊
524␉␉␉␉␉␉}␊
525␉␉␉␉␉␉else␊
526␉␉␉␉␉␉{␊
527␉␉␉␉␉␉␉printf("Bus-Ratio: Lowest allowed = %d%s. ", bus_ratio_min, currdiv ? ".5" : "");␊
528␉␉␉␉␉␉␉goto ratio_vldt;␊
529␉␉␉␉␉␉}␊
530␉␉␉␉␉}␊
531␉␉␉␉␉else ␊
532␉␉␉␉␉{␊
533␉␉␉␉␉␉ratio_vldt:␊
534␉␉␉␉␉␉if (maxdiv)␊
535␉␉␉␉␉␉{␊
536␉␉␉␉␉␉␉cpuFrequency = ((fsbFrequency * ((bus_ratio_max * 2) + 1)) / 2);␊
537␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10) + 5;␊
538␉␉␉␉␉␉}␊
539␉␉␉␉␉␉else␊
540␉␉␉␉␉␉{␊
541␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * bus_ratio_max);␊
542␉␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
543␉␉␉␉␉␉}␊
544␉␉␉␉␉␉verbose("CPU: Sticking with: [FSB: %dMhz, Bus-Ratio: %d%s] %s\n", myfsb, bus_ratio_max, maxdiv ? ".5" : "", newratio ? "instead" : "");␊
545␉␉␉␉␉}␊
546␉␉␉␉}␊
547␉␉␉␉else␊
548␉␉␉␉{␊
549␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
550␉␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊
551␊
552␉␉␉␉␉if (bus_ratio_max)␊
553␉␉␉␉␉{␊
554␉␉␉␉␉␉if (maxdiv)␊
555␉␉␉␉␉␉{␊
556␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1));␊
557␉␉␉␉␉␉␉max_ratio = ((bus_ratio_max * 10) + 5);␊
558␉␉␉␉␉␉}␊
559␉␉␉␉␉␉else␊
560␉␉␉␉␉␉{␊
561␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
562␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
563␉␉␉␉␉␉}␊
564␊
565␉␉␉␉␉␉myfsb = (fsbFrequency / 1000000);␊
566␉␉␉␉␉␉if (getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) goto ratio_gn;␊
567␉␉␉␉␉␉else cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
568␊
569␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", bus_ratio_max, maxdiv ? ".5" : "", bus_ratio_min, currdiv ? ".5" : "");␊
570␉␉␉␉␉}␊
571␉␉␉␉}␊
572␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
573␉␉␉␉p->CPU.MinRatio = min_ratio;␊
574␉␉␉}␊
575␉␉}␊
576␊
577␉␉// on-die sensor␊
578␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x6)␊
579␉␉{␊
580␉␉␉// Highest Basic Functions Number␊
581␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_81]);␊
582␉␉␉tms = bitfield(p->CPU.CPUID[CPUID_81][0], 0, 0);␊
583␉␉␉ida = bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1);␊
584␉␉␉if(tms != 0)␊
585␉␉␉{␊
586␉␉␉␉int temp, utjmax;␊
587␉␉␉␉if (tjmax == 0) tjmax = 100;␊
588␉␉␉␉if((getIntForKey(kTjmax, &utjmax, &bootInfo->bootConfig)) && ((70 <= utjmax) && (utjmax <= 110))) tjmax = utjmax;␊
589␉␉␉␉msr = rdmsr64(MSR_THERMAL_STATUS);␊
590␉␉␉␉//if ((msr & 0x3) == 0x3)␊
591␉␉␉␉if (((msr >> 31) & 0x1) == 1)␊
592␉␉␉␉{␊
593␉␉␉␉␉temp = tjmax - ((msr >> 16) & 0x7F);␊
594␉␉␉␉␉verbose("CPU: Tjmax ~ %d°C ␉ Temperature= ~ %d°C\n", tjmax, temp);␊
595␉␉␉␉}␊
596␉␉␉␉else temp = -1;␊
597␉␉␉}␊
598␉␉␉if(ida == 0)␊
599␉␉␉{␊
600␉␉␉␉verbose("CPU: Attempting to enable IDA ");␊
601␉␉␉␉msr_t msr;␊
602␉␉␉␉msr = rdmsr(MSR_IA32_MISC_ENABLE);␊
603␉␉␉␉msr.hi |= (0 << (38-32));␊
604␉␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr);␊
605␉␉␉␉delay(1);␊
606␉␉␉␉if(bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1) == 0) verbose("Failed!\n");␊
607␉␉␉␉else verbose("Succeded!\n");␊
608␉␉␉}␊
609␉␉␉else verbose("CPU: IDA: Enabled!\n");␊
610␉␉}␊
611␉}␊
612//#if 0␊
613␉else if(p->CPU.Vendor == 0x68747541 /* AMD */) // valv: work in progress␊
614␉{␊
615␉␉verbose("CPU: ");␊
616␉␉// valv: very experimental mobility check␊
617␉␉if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)␊
618␉␉{␊
619␉␉␉do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);␊
620␉␉␉amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);␊
621␉␉␉if (amo == 1)␊
622␉␉␉{␊
623␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
624␉␉␉␉if (!strstr(p->CPU.BrandString, "obile")) verbose("Mobile ");␊
625␉␉␉}␊
626␉␉}␊
627␉␉//valv: 2nd attemp; just in case␊
628␉␉if (!platformCPUFeature(CPU_FEATURE_MOBILE))␊
629␉␉{␊
630␉␉␉if (strstr(p->CPU.BrandString, "obile"))␊
631␉␉␉{␊
632␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
633␉␉␉}␊
634␉␉}␊
635␉␉verbose("%s\n", p->CPU.BrandString);␊
636␉␉int amdCPU = p->CPU.Family;␊
637␉␉␊
638␉␉switch (amdCPU)␊
639␉␉{␊
640␉␉␉case 0x0f:␊
641␉␉␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
642␉␉␉␉{␊
643␉␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
644␉␉␉␉␉bus_ratio_max = (msr & 0x3f) / 2 + 4;␊
645␉␉␉␉␉currdiv = (msr & 0x01) * 2;␊
646␉␉␉␉}␊
647␉␉␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
648␉␉␉␉{␊
649␉␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
650␉␉␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
651␉␉␉␉␉␉bus_ratio_max = (msr & 0x3f) + 0x10;␊
652␉␉␉␉␉else /* K11+ */␊
653␉␉␉␉␉␉bus_ratio_max = (msr & 0x3f) + 0x08;␊
654␉␉␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
655␉␉␉␉}␊
656␉␉␉␉␊
657␉␉␉␉p->CPU.MaxRatio = bus_ratio_max * 10;␊
658␊
659␉␉␉␉if (bus_ratio_max)␊
660␉␉␉␉{␊
661␉␉␉␉␉if (currdiv)␊
662␉␉␉␉␉{␊
663␉␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊
664␉␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊
665␉␉␉␉␉}␊
666␉␉␉␉␉else␊
667␉␉␉␉␉{␊
668␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
669␉␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊
670␉␉␉␉␉}␊
671␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊
672␉␉␉␉␉cpuFrequency = tscFrequency; // ?␊
673␉␉␉␉}␊
674␉␉␉␉break;␊
675␉␉␉case 0x10:␉// phenom␊
676␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
677␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
678␉␉␉␉currdiv = (((msr) >> 6) & 0x07);␊
679␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);␊
680␉␉␉␉break;␊
681␉␉␉case 0x11:␉// shangai␊
682␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
683␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
684␉␉␉␉currdiv = (((msr) >> 6) & 0x07);␊
685␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);␊
686␉␉␉␉break;␊
687␉␉}␊
688␉}␊
689␊
690␉if (!fsbFrequency)␊
691␉{␊
692␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
693␉␉cpuFrequency = tscFrequency;␊
694␉␉DBG("0 ! using the default value for FSB !\n");␊
695␉}␊
696␊
697//#endif␊
698␊
699␉p->CPU.MaxDiv = maxdiv;␊
700␉p->CPU.CurrDiv = currdiv;␊
701␉p->CPU.TSCFrequency = tscFrequency;␊
702␉p->CPU.FSBFrequency = fsbFrequency;␊
703␉p->CPU.CPUFrequency = cpuFrequency;␊
704␉p->CPU.ISerie = false;␊
705␉p->CPU.Turbo = false;␊
706␊
707␉if(fsbi == 0) p->CPU.FSBIFrequency = fsbFrequency;␊
708␉else p->CPU.FSBIFrequency = fsbi;␊
709␊
710␉if (platformCPUFeature(CPU_FEATURE_EST))␊
711␉{␊
712␉␉msr_t msr32;␊
713␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
714␉␉if (!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16)))␊
715␉␉{␉//valv: we can also attempt to enable␊
716␉␉␉msr32.lo |= (1 << 16);␊
717␉␉␉// Lock till next reset!␊
718␉␉␉msr32.lo |= (1 << 20);␊
719␉␉␉wrmsr(MSR_IA32_MISC_ENABLE, msr32);␊
720␉␉␉delay(1);␊
721␉␉␉if(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 16))␊
722␉␉␉{␊
723␉␉␉␉p->CPU.EST = 1;␊
724␉␉␉␉verbose("CPU: EIST Successfully Enabled!\n");␊
725␉␉␉}␊
726␉␉␉else␊
727␉␉␉{␊
728␉␉␉␉p->CPU.EST = 0;␊
729␉␉␉␉verbose("CPU: EIST couldn't be enabled!\n");␊
730␉␉␉}␊
731␉␉}␊
732␊
733␉␉else p->CPU.EST = 1;␊
734␉}␊
735␉␊
736␉if(core_i) p->CPU.ISerie = true;␊
737␉␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
738␉␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
739␉␉DBG("CPU: Multipliers x10: max=%d, min=%d\n", p->CPU.MaxRatio, p->CPU.MinRatio);␊
740␉if(turbo)␊
741␉{␊
742␉␉DBG("Turbo Ratio: %d/%d/%d/%d\n", p->CPU.Tone, p->CPU.Ttwo, p->CPU.Tthr, p->CPU.Tfor);␊
743␉␉p->CPU.Turbo = true;␊
744␉}␊
745␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
746␉␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
747␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
748␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
749␉if(did)␊
750␉{␊
751␉␉p->CPU.SLFM = did;␊
752␉␉DBG("CPU: SLFM: %d\n", p->CPU.SLFM);␊
753␉}␊
754␉␉if(platformCPUFeature(CPU_FEATURE_EST))␊
755␉␉DBG("CPU: Enhanced SpeedStep: %d\n", p->CPU.EST);␊
756␉␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
757␉␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
758}␊
759

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