1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | * valv: 2010: fine-tuning and additions␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_CPU_H␊ |
8 | #define __LIBSAIO_CPU_H␊ |
9 | ␊ |
10 | #include "libsaio.h"␊ |
11 | ␊ |
12 | extern void scan_cpu(PlatformInfo_t *);␊ |
13 | ␊ |
14 | #define bit(n)␉␉␉(1UL << (n))␊ |
15 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
16 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
17 | ␊ |
18 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Typ"␊ |
19 | ␊ |
20 | #define MSR_FSB_FREQ 0xCD␊ |
21 | #define MSR_TURBO_RATIO_LIMIT 0x1AD␊ |
22 | #define MSR_IA32_PLATFORM_ID 0x17␊ |
23 | #define␉MSR_IA32_PERF_STATUS 0x198␊ |
24 | #define MSR_IA32_PERF_CONTROL 0x199␊ |
25 | #define MSR_IA32_EXT_CONFIG 0xEE␊ |
26 | #define MSR_FLEX_RATIO 0x194␊ |
27 | #define␉MSR_PLATFORM_INFO 0xCE␊ |
28 | #define MSR_IA32_MISC_ENABLE 0x1A0␊ |
29 | #define MSR_THERMAL_STATUS 0x19C␊ |
30 | #define MSR_IA32_CLOCK_MODULATION 0x19A␊ |
31 | #define MSR_THERMAL_TARGET 0x01A2␊ |
32 | #define PIC_SENS_CFG 0x1aa␊ |
33 | #define K8_FIDVID_STATUS 0xC0010042␊ |
34 | #define␉AMD_10H_11H_CONFIG 0xc0010064␊ |
35 | #define K10_COFVID_STATUS 0xC0010071␊ |
36 | ␊ |
37 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
38 | ␊ |
39 | // DFE: This constant comes from older xnu:␊ |
40 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
41 | ␊ |
42 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
43 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
44 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
45 | ␊ |
46 | static inline uint64_t rdtsc64(void)␊ |
47 | {␊ |
48 | ␉uint64_t ret;␊ |
49 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
50 | ␉return ret;␊ |
51 | }␊ |
52 | ␊ |
53 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
54 | {␊ |
55 | uint64_t ret;␊ |
56 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
57 | return ret;␊ |
58 | }␊ |
59 | ␊ |
60 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
61 | {␊ |
62 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
63 | }␊ |
64 | ␊ |
65 | typedef struct msr_struct␊ |
66 | {␊ |
67 | ␉unsigned lo;␊ |
68 | ␉unsigned hi;␊ |
69 | } msr_t;␊ |
70 | ␊ |
71 | static inline __attribute__((always_inline)) msr_t rdmsr(unsigned val)␊ |
72 | {␊ |
73 | ␉msr_t ret;␊ |
74 | ␉__asm__ volatile(␊ |
75 | ␉␉"rdmsr"␊ |
76 | ␉␉: "=a" (ret.lo), "=d" (ret.hi)␊ |
77 | ␉␉: "c" (val)␊ |
78 | ␉␉);␊ |
79 | ␉return ret;␊ |
80 | }␊ |
81 | ␊ |
82 | static inline __attribute__((always_inline)) void wrmsr(unsigned val, msr_t msr)␊ |
83 | {␊ |
84 | ␉__asm__ __volatile__ (␊ |
85 | ␉␉"wrmsr"␊ |
86 | ␉␉: /* No outputs */␊ |
87 | ␉␉: "c" (val), "a" (msr.lo), "d" (msr.hi)␊ |
88 | ␉␉);␊ |
89 | }␊ |
90 | ␊ |
91 | static inline void intel_waitforsts(void) {␊ |
92 | ␉uint32_t inline_timeout = 100000;␊ |
93 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
94 | }␊ |
95 | ␊ |
96 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
97 | {␊ |
98 | ␉asm volatile ("cpuid"␊ |
99 | ␉␉␉␉ : "=a" (data[0]),␊ |
100 | ␉␉␉␉ "=b" (data[1]),␊ |
101 | ␉␉␉␉ "=c" (data[2]),␊ |
102 | ␉␉␉␉ "=d" (data[3])␊ |
103 | ␉␉␉␉ : "a" (selector));␊ |
104 | }␊ |
105 | ␊ |
106 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
107 | {␊ |
108 | ␉asm volatile ("cpuid"␊ |
109 | ␉␉␉␉ : "=a" (data[0]),␊ |
110 | ␉␉␉␉ "=b" (data[1]),␊ |
111 | ␉␉␉␉ "=c" (data[2]),␊ |
112 | ␉␉␉␉ "=d" (data[3])␊ |
113 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
114 | }␊ |
115 | ␊ |
116 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
117 | ␊ |
118 | /*␊ |
119 | * Enable or disable timer 2.␊ |
120 | * Port 0x61 controls timer 2:␊ |
121 | * bit 0 gates the clock,␊ |
122 | * bit 1 gates output to speaker.␊ |
123 | */␊ |
124 | static inline void enable_PIT2(void)␊ |
125 | {␊ |
126 | /* Enable gate, disable speaker */␊ |
127 | __asm__ volatile(␊ |
128 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
129 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
130 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
131 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
132 | ␉␉␉␉␉ : : : "%al" );␊ |
133 | }␊ |
134 | ␊ |
135 | static inline void disable_PIT2(void)␊ |
136 | {␊ |
137 | /* Disable gate and output to speaker */␊ |
138 | __asm__ volatile(␊ |
139 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
140 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
141 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
142 | ␉␉␉␉␉ : : : "%al" );␊ |
143 | }␊ |
144 | ␊ |
145 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
146 | // roughly based on Linux code␊ |
147 | ␊ |
148 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
149 | In mode 0, the counter will initially set its gate low when the␊ |
150 | timer expires. For this to be useful, you ought to set it high␊ |
151 | before calling this function. The enable_PIT2 function does this.␊ |
152 | */␊ |
153 | static inline void set_PIT2_mode0(uint16_t value)␊ |
154 | {␊ |
155 | __asm__ volatile(␊ |
156 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
157 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
158 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
159 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
160 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
161 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
162 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
163 | }␊ |
164 | ␊ |
165 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
166 | static inline unsigned long poll_PIT2_gate(void)␊ |
167 | {␊ |
168 | unsigned long count = 0;␊ |
169 | unsigned char nmi_sc_val;␊ |
170 | do {␊ |
171 | ++count;␊ |
172 | __asm__ volatile(␊ |
173 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
174 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
175 | } while( (nmi_sc_val & 0x20) == 0);␊ |
176 | return count;␊ |
177 | }␊ |
178 | ␊ |
179 | #endif /* !__LIBSAIO_CPU_H */␊ |
180 | |